AD75019JP ,16 x 16 Crosspoint Switch ArraySpecifications subject to change without notice.PIN FUNCTION DESCRIPTIONS PIN CONFIGURATIONPin Name ..
AD75019JP ,16 x 16 Crosspoint Switch ArraySPECIFICATIONSA DD SS CCAD75019 Symbol Min Typ Max UnitsMULTIPLEXERInput Signal Range V V – 0.5 V + ..
AD75019JPZ , 16 3 16 Crosspoint Switch Array
AD7501JN ,4Specifications subject to change without notice.ABSOLUTE MAXIMUM RATINGS Operating Temperature(T = ..
AD7501JN. ,4CMOSa4-/8-Channel Analog MultiplexersAD7501/AD7502/AD7503
AD7501JQ ,4GENERAL DESCRIPTIONThe AD7501 and AD7503 are monolithic CMOS, 8-channelanalog multiplexers which sw ..
ADG201HSJP ,LC2MOS HIGH SPEED, QUAD SPST SWITCH
ADG202AKNZ , LC2MOS Quad SPST Switches
ADG211AKN ,LC2MOS QUAD SPST SWITCHESCHARACTERISTICS
Iomm1 Test Circuit4
tovl Test Circuit 5
tOFF1 Test Circuit 5
OFF Isolation Vs ..
ADG211AKNZ ,LC2MOS ±15 V Quad SPST Switchapplications, all switches exhibit break-before-make
switching action when driven simultaneously. ..
ADG211AKP ,LC2MOS QUAD SPST SWITCHESapplications, all switches exhibit break-before-make
switching action when driven simultaneously. ..
ADG211AKR ,LC2MOS QUAD SPST SWITCHESFEATURES
AAN Supply Maximum Rating
t 15V Analog Signal Range
Low RON (1150 max)
Low Lea ..
AD75019JP
16 x 16 Crosspoint Switch Array
REV. C
16 3 16 Crosspoint
Switch Array
FUNCTIONAL BLOCK DIAGRAM
FEATURES
256 Switches in a 16 3 16 Array
Wide Signal Range: to Supply Rails of 24 V or 612 V
Low On-Resistance: 200V Typ
TTL/CMOS/Microprocessor-Compatible Control Lines
Serial Input Simplifies Interface
Serial Output Allows Cascading for More Channels
Low Power Consumption: 2 mW Quiescent
Compact 44-Lead PLCC
PRODUCT DESCRIPTIONThe AD75019 contains 256 analog switches in a 16 · 16 array.
Any of the X or Y pins may serve as an input or output. Any or
all of the X terminals may be programmed to connect to any or
all of the Y terminals. The switches can accommodate signals
with amplitudes up to the supply rails and have a typical on-
resistance of 150 W.
Data is loaded serially via the SIN input and clocked into an on-
board 256-bit shift register via SCLK. When all the switch set-
tings have been programmed, data is transferred into a set of
256 latches via PCLK. The serial shift register is dynamic, so
there is a minimum clock rate of 20 kHz. The maximum clock
rate of 5 MHz allows loading times as short as 52 ms. The switch
control latches are static and will hold their data as long as power
is applied.
To extend the number of switches in the array, you may cascade
multiple AD75019s. The SOUT output is the end of the shift
register, and may be connected to the SIN input of the next
AD75019.
The AD75019 is fabricated in Analog Devices’ BiMOS II
process. This epitaxial BiCMOS process features CMOS
devices for low distortion switches and bipolar devices for
ESD protection.
AD75019–SPECIFICATIONS1DIGITAL OUTPUTS (SOUT)
NOTES
1All minimum and maximum specifications are guaranteed, and specifications shown in boldface are tested on all production units at final electrical test. Results from those tests
are used to calculate outgoing quality levels.
2Switch resistance matching is measured with zero volts at each analog input and refers to the difference between the maximum and minimum values.
Specifications subject to change without notice.
(TA = +258C, VDD and VSS = 612 V, VCC = +5 V unless otherwise noted)
PIN CONFIGURATION
X15
X14
Y15
Y14
Y13
Y12
Y11
Y10NCV
SINSCLKPCLKSOUT
DGNDV
PIN FUNCTION DESCRIPTIONS
(TA = TMIN to TMAX, rated power supplies unless otherwise noted)TIMING CHARACTERISTICS1NOTESTiming measurement reference level is 1.5 V.
Specifications subject to change without notice.
OPERATION TRUTH TABLE
APPLICATIONS INFORMATION
Loading DataData to control the switches is clocked serially into a 256-bit
shift register and then transferred in parallel to 256 bits of mem-
ory. The rising edge of SCLK, the serial clock input, loads data
into the shift register. The first bit loaded via SIN, the serial
data input, controls the switch at the intersection of row Y15
and column X15. The next bits control the remaining columns
(down to X0) of row Y15, and are followed by the bits for row
Y14, and so on down to the data for the switch at the intersec-
tion of row Y0 and column X0. The shift register is dynamic, so
there is a minimum clock rate, specified as 20 kHz.
After the shift register is filled with the new 256 bits of control
data, PCLK is activated (pulsed low) to transfer the data to the
parallel latches. Since the shift register is dynamic, there is a
maximum time delay specified before the data is lost: PCLK
must be activated and brought back high within 5 ms after fill-
ing the shift register. The switch control latches are static and
will hold their data as long as power is applied.
Power Supply Sequencing and BypassingAll junction-isolated parts operating on multiple power supplies
require proper attention to supply sequencing. Because BiMOS
II is a junction-isolated process, parasitic diodes exist between
VDD and VCC, and between VSS and DGND. As a result, VDD
must always be greater than (VCC – 0.5 V), and VSS must always
be less than (DGND + 0.5 V).
If you can’t ensure that system power supplies will sequence to
meet these conditions, external Schottky (e.g., 1N5818) or
silicon (e.g., 1N4001) diodes may be used. To protect the posi-
tive side, the anode would connect to VCC (Pin 42) and the
cathode to VDD (Pin 41). For the negative side, connect the
anode to VSS (Pin 4) and the cathode to DGND (Pin 43).
Each of the three power supply pins [VDD (Pin 41), VCC (Pin
42) and VSS (Pin 4)] should be bypassed to DGND (Pin 43)
through a 0.1 mF ceramic capacitor located close to the package
pins.
Transistor Count
TIMING DIAGRAM
SCLK
PCLK
1 = CLOSE
0 = OPEN
SIN
AD75019
ABSOLUTE MAXIMUM RATINGS*Power Dissipation
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only; functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected;
however, permanent damage may occur on unconnected devices subject to high energy
electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective
foam should be discharged to the destination socket before devices are removed.
ORDERING GUIDE*P = Plastic Leaded Chip Carrier (PLCC) Package.
OUTLINE DIMENSIONSDimensions shown in inches and (mm).
44-Lead Plastic Leaded Chip Carrier
(P-44A)C1502c–0–8/99
PRINTED IN U.S.A.
:
www.ic-phoenix.com
.
