AD7492AR Fast Delivery |IC PHOENIX CO.,LIMITED

AD7492AR ,1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADCSPECIFICATIONS DD A MIN MAX1 1Parameter A Version B Version Unit Test Conditions/CommentsDYNAMIC PE ..
AD7495BRM ,1 MSPS, 12-Bit ADCsSPECIFICATIONSA MIN MAX1 1Parameter A Version B Version Unit Test Conditions/CommentsDYNAMIC PERFOR ..
AD75004KN ,Quad 12-Bit D/A Convertercharacteristics comparable todouble-buffered latches. The design of the input latches allowsdiscret ..
AD75004KP ,Quad 12-Bit D/A ConverterSPECIFICATIONS (T = +258C, 612.0 V power supplies unless otherwise noted)AParameter Symbol Min Typ ..
AD75004KP ,Quad 12-Bit D/A ConverterFEATURES4 Complete 12-Bit D/A FunctionsVVREFOUT REFINDouble-Buffered Latches+5VSimultaneous Update ..
AD75019JP ,16 x 16 Crosspoint Switch ArraySpecifications subject to change without notice.PIN FUNCTION DESCRIPTIONS PIN CONFIGURATIONPin Name ..
ADG201ATQ ,LC2MOS QUAD SPST SWITCHES
ADG201HSJP ,LC2MOS HIGH SPEED, QUAD SPST SWITCH
ADG202AKNZ , LC2MOS Quad SPST Switches
ADG211AKN ,LC2MOS QUAD SPST SWITCHESCHARACTERISTICS Iomm1 Test Circuit4 tovl Test Circuit 5 tOFF1 Test Circuit 5 OFF Isolation Vs ..
ADG211AKNZ ,LC2MOS ±15 V Quad SPST Switchapplications, all switches exhibit break-before-make switching action when driven simultaneously. ..
ADG211AKP ,LC2MOS QUAD SPST SWITCHESapplications, all switches exhibit break-before-make switching action when driven simultaneously. ..

AD7492AR
1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC
REV.0
1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
FUNCTIONAL BLOCK DIAGRAM
VIN
DB0
DB11
PS/FS
CONVST
BUSY
AVDDREF OUTVDRIVE
AGNDDGND
DVDD
FEATURES
Specified for VDD of 2.7V to 5.25V
Throughput Rate of 1 MSPS—AD7492
Throughput Rate of 1.25 MSPS—AD7492-5
Low Power
4 mW Typ at 1 MSPS with 3 V Supplies
11 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB Typ SNR at 100 kHz Input Frequency
2.5 V Internal Reference
On-Chip CLK Oscillator
Flexible Power/Throughput Rate Management
No Pipeline Delays
High-Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages
GENERAL DESCRIPTION
The AD7492 and AD7492-5 are 12-bit high-speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.25 MSPS. They contain a low-noise, wide bandwidth
track/hold amplifier that can handle bandwidths up to 10 MHz.
The conversion process and data acquisition are controlled using
standard control inputs allowing easy interface to microproces-
sors or DSPs. The input signal is sampled on the falling edge of
CONVST and conversion is also initiated at this point. The
BUSY goes high at the start of conversion and goes low 880 ns
(AD7492) or 680 ns (AD7492-5) later to indicate that the con-
version is complete. There are no pipeline delays associated with
the part. The conversion result is accessed via standard CS and
RD signals over a high-speed parallel interface.
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
The type of sleep mode is hardware selected by the PS/FS pin.
Using these sleep modes allows very low power dissipation num-
bers at lower throughput rates.
The analog input range for the part is 0 to REF IN. The 2.5 V
reference is supplied internally and is available for external refer-
encing. The conversion rate is determined by the internal clock.
PRODUCT HIGHLIGHTSHigh Throughput with Low Power Consumption
The AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.Flexible Power/Throughput Rate Management
The conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to maxi-
mize power efficiency at lower throughput rates.No Pipeline Delay
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CONVST
input and once-off conversion control.Flexible Digital Interface
The VDRIVE feature controls the voltage levels on the I/O
digital pins.Fewer Peripheral Components
The AD7492 optimizes PCB space by using an internal
Reference and internal CLK.
AD7492-5–SPECIFICATIONS1(VDD = 4.75 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
AD7492
AD7492AD7492–SPECIFICATIONS1(VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
REFERENCE OUTPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
NOTES
AD7492
TIMING SPECIFICATIONS1
NOTESSample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Figure 1.The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 µs, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
Figure 1.Load Circuit for Digital Output Timing Specifications
(VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
AVDD to AGND/DGND . . . . . . . . . . . . . . . . .–0.3 V to +7 V
DVDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDRIVE to AGND/DGND . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VDRIVE to DVDD . . . . . . . . . . . . . . . .–0.3 V to DVDD + 0.3 V
AGND TO DGND . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Analog Input Voltage to AGND . . .–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A and B Versions) . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC, TSSOP Package Dissipation . . . . . . . . . . . . . .450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . 75°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W (TSSOP)
θJC Thermal Impedance . . . . . . . . . . . . . . . 25°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
AD7492ARU
AD7492BR
AD7492BRU
AD7492AR-5
AD7492ARU-5
AD7492BR-5
AD7492BRU-5
EVAL-AD7492CB
NOTESR = SOIC; RU = TSSOP.This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATION
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7492 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD7492
PIN FUNCTION DESCRIPTION
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
The last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7492).
The gain error is the deviation of the actual difference between
the first and last code transitions from the ideal difference between
the first and last code transitions with offset errors removed.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±0.5 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB and for a 10-bit con-
verter is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7492 it is defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7492 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Aperture Delay
In a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture Jitter
Aperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise which modulates the phase of
the hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error will increase as the input dV/dt
increases.
AD7492
–Typical Performance Characteristics
INPUT FREQUENCY – kHz
SNR+D – dB
5001000150020002500
TPC 1.Typical SNR+D vs. Input Tone
INPUT FREQUENCY – kHz
THD
dB
500
TPC 2.Typical THD vs. Input Tone
SUPPLY – Volts
SNR
dB
70.60
TPC 3.Typical SNR vs. Supply
FREQUENCY – Hz
200000300000400000500000600000
TPC 4.Typical SNR @ 500 kHz Input Tone
FREQUENCY – Hz
–0.5
TPC 5.Typical Bandwidth
VCC RIPPLE FREQUENCY – kHz
PSSR
dB
5161020263136414651576167727782889297381318232834394449545964697480848994
TPC 6.Typical Power Supply Rejection Ratio (PSRR)

Partno	Mfg	Dc	Qty	Available	Descript
AD7492AR	AD	N/a	150	avai	1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC