AD7490BRU ,16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOPSPECIFICATIONS otherwise noted.)2Parameter B Version Unit Test Conditions/CommentsDYNAMIC PERFORMAN ..
AD7490BRU-REEL7 , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
AD7490BRUZ , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
AD7490BRUZ , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
AD7490BRUZ-REEL7 , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
AD7492AR ,1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADCSPECIFICATIONS DD A MIN MAX1 1Parameter A Version B Version Unit Test Conditions/CommentsDYNAMIC PE ..
ADG201ATQ ,LC2MOS QUAD SPST SWITCHES
ADG201HSJP ,LC2MOS HIGH SPEED, QUAD SPST SWITCH
ADG202AKNZ , LC2MOS Quad SPST Switches
ADG211AKN ,LC2MOS QUAD SPST SWITCHESCHARACTERISTICS
Iomm1 Test Circuit4
tovl Test Circuit 5
tOFF1 Test Circuit 5
OFF Isolation Vs ..
ADG211AKNZ ,LC2MOS ±15 V Quad SPST Switchapplications, all switches exhibit break-before-make
switching action when driven simultaneously. ..
ADG211AKP ,LC2MOS QUAD SPST SWITCHESapplications, all switches exhibit break-before-make
switching action when driven simultaneously. ..
AD7490BRU
16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
REV.A
16-Channel, 1 MSPS, 12-Bit ADC
with Sequencer in 28-Lead TSSOP
FUNCTIONAL BLOCK DIAGRAM
VIN0
VIN15
GND
SCLK
DOUT
DIN
VDRIVE
VDD
REFIN
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for VDD of 2.7V to 5.25V
Low Power at Max Throughput Rates:
5.4 mW Max at 870 kSPS with 3V Supplies
12.5mW Max at 1 MSPS with 5V Supplies
16 (Single-Ended) Inputs with Sequencer
Wide Input Bandwidth:
69.5dB SNR at 50kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface SPI™/QSPI™/
MICROWIRE™/DSP Compatible
Full Shutdown Mode: 0.5 �A Max
28-Lead TSSOP and 32-Lead LFCSP Packages
GENERAL DESCRIPTIONThe AD7490 is a 12-bit high speed, low power, 16-channel,
successive-approximation ADC. The part operates from a single
2.7V to 5.25V power supply and features throughput rates up
to 1MSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 1MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock signal, allowing the device to
easily interface with microprocessors or DSPs. The input signal
is sampled on the falling edge of CS and conversion is also
initiated at this point. There are no pipeline delays associated
with the part.
The AD7490 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. For maximum
throughput rates, the AD7490 consumes just 1.8 mA with 3 V
supplies, and 2.5 mA with 5 V supplies.
By setting the relevant bits in the Control Register, the analog
input range for the part can be selected to be a 0 to REFIN input or
a 0 to 2 � REFIN with either straight binary or twos complement
output coding. The AD7490 features 16 single-ended analog
inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially.
The conversion time is determined by the SCLK frequency as
this is also used as the master clock to control the conversion.
The AD7490 is available in a 28-lead thin shrink small outline
(TSSOP) package, and a 32-lead chip scale package.
SPI and QSPI are trademarks of Motorola Inc.
MICROWIRE is a trademark of National Semiconductor Corporation
PRODUCT HIGHLIGHTSHigh Throughput with Low Power Consumption
The AD7490 offers up to 1 MSPS throughput rates. At
maximum throughput with 3 V supplies, the AD7490
dissipates just 5.4 mW of power.Sixteen Single-Ended Inputs with Channel Sequencer
A Sequence of channels can be selected, through which the
AD7490 will cycle and convert.Single-Supply Operation with VDRIVE Function
The AD7490 operates from a single 2.7 V to 5.25 V supply.
The VDRIVE function allows the serial interface to connect
directly to either 3 V or 5 V processor systems independent
of VDD.Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. The part also features various shutdown
modes to maximize power efficiency at lower throughput
rates. Power consumption is 0.5µA max when in full shutdown.No Pipeline Delay
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once off conversion control.
AD7490–SPECIFICATIONS
(VDD = VDRIVE = 2.7V to 5.25V, REFIN = 2.5V, fSCLK1 = 20MHz, TA = TMIN to TMAX, unless
otherwise noted.)DYNAMIC PERFORMANCE
AD7490CONVERSION RATE
NOTES
1Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see Timing Specifications.
2Temperature Ranges (B Version): –40°C to +85°C.
3See Terminology section.
4Sample tested at 25°C to ensure compliance.
5See Power Versus Throughput Rate section.
Specifications subject to change without notice.
AD7490
TIMING SPECIFICATIONS1tCONVERT
t10
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr= tf= 5ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
(See Figure1.) The 3V operating range spans from 2.7V to 3.6V. The 5V operating range spans from 4.75V to 5.25V.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be
taken when interfacing to account for data access time t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK
frequency with which the user’s system can operate. (See Serial Interface section.)
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4V or 0.7VDRIVEV.
4t3b represents a worst-case figure for having ADD3 available on the DOUT line, i.e., if the AD7490 went back into three-state at the end of a conversion and some
other device took control of the bus between conversions, the user would have to wait a maximum time of t3b before having ADD3 valid on DOUT line. If the DOUT
line is weakly driven to ADD3 between conversions, then the user would typically have to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing
ADD3 valid on DOUT.
5t8 is derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
(VDD = 2.7 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
VDRIVE to GND . . . . . . . . . . . . . . . . . . –0.3V to VDD + 0.3V
Analog Input Voltage to GND . . . . . . .–0.3V to VDD + 0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7V
Digital Output Voltage to GND . . . . . –0.3V to VDD + 0.3V
REFIN to GND . . . . . . . . . . . . . . . . . . –0.3V to VDD + 0.3V
Input Current to Any Pin Except Supplies2 . . . . . . . . ±10mA
Operating Temperature Ranges
Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
Figure 1.Load Circuit for Digital Output Timing Specifications
LFCSP, TSSOP Package, Power Dissipation . . . . . . 450mW
θJA Thermal Impedance . . . . . . . . . . . 108.2°C/W (LFCSP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . .97.9°C/W (TSSOP)
θJC Thermal Impedance . . . . . . . . . . . 32.71°C/W (LFCSP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100mA will not cause SCR latch up.
ORDERING GUIDENOTESLinearity error refers to integral linearity error.This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/
demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in
the CB designators. To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g.,
EVAL-AD7490CB, the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See relevant evaluation board technical note for
more information.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7490 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
