AD7484BST Fast Delivery |IC PHOENIX CO.,LIMITED

AD7484BST ,3MSPS, 14-Bit SAR ADCSPECIFICATIONSSAMPLEParameter Specification Units Test Conditions/CommentsDYNAMIC PE ..
AD7490BRU ,16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOPSPECIFICATIONS otherwise noted.)2Parameter B Version Unit Test Conditions/CommentsDYNAMIC PERFORMAN ..
AD7490BRU-REEL7 , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
AD7490BRUZ , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
AD7490BRUZ , 16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
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ADG201ATQ ,LC2MOS QUAD SPST SWITCHES
ADG201HSJP ,LC2MOS HIGH SPEED, QUAD SPST SWITCH
ADG202AKNZ , LC2MOS Quad SPST Switches
ADG211AKN ,LC2MOS QUAD SPST SWITCHESCHARACTERISTICS Iomm1 Test Circuit4 tovl Test Circuit 5 tOFF1 Test Circuit 5 OFF Isolation Vs ..
ADG211AKNZ ,LC2MOS ±15 V Quad SPST Switchapplications, all switches exhibit break-before-make switching action when driven simultaneously. ..
ADG211AKP ,LC2MOS QUAD SPST SWITCHESapplications, all switches exhibit break-before-make switching action when driven simultaneously. ..

AD7484BST
3MSPS, 14-Bit SAR ADC
REV. PrC 7/13/01
PRELIMINARY TECHNICAL DATA
3MSPS,
14-Bit SAR ADC
FUNCTIONAL BLOCK DIAGRAMFEATURES
Fast Throughput Rate: 3Msps
Wide Input Bandwidth: 50MHz
No Pipeline Delays with SAR ADC
Excellent DC Accuracy Performance
Two Parallel Interface Modes
Low Power:
90mW (Full-Power) and 5mW (NAP Mode)
Standby Mode: 1µA max
Single +5V Supply Operation
Internal +2.5V Reference
Full-Scale Overrange Mode (using 15th bit)
System Offset Removal via User Access Offset Register
Nominal 0 to +2.5V Input with Shifted Range Capability
Pin Compatible Upgrade of 12-Bit AD7482
GENERAL DESCRIPTION
The AD7484 is a 14-bit, high speed, low power, succes-
sive-approximation ADC. The part features a parallel
interface with throughput rates up to 3Msps. The part
contains a low-noise, wide bandwidth track/hold amplifier
which can handle input frequencies in excess of 50MHz.
The conversion process is a proprietary algorithmic suc-
cessive-approximation technique which results in no
pipeline delays. The input signal is sampled and a conver-
sion is initiated on the falling edge of the ��
signal. The conversion process is controlled via an inter-
nally trimmed oscillator. Interfacing is via standard
parallel signal lines making the part directly compatible
with microcontrollers and DSPs.
The AD7484 provides excellent ac and dc performance
specifications. Factory trimming ensures high dc accuracy
resulting in very low INL, offset and gain errors.
The part uses advanced design techniques to achieve very
low power dissipation at high throughput rates. Power
consumption in normal mode of operation is 90mW.
There are two power-saving modes: a NAP mode, which
keeps the reference circuitry alive for a quick power up
while consuming 5mW and a STANDBY mode which
reduces power consumption to a mere 5µW.
The AD7484 features an on-board +2.5V reference but
the part can also accomodate an externally-provided
+2.5V reference source. The nominal analog input range
is 0 to +2.5V but an offset shift capability allows this
nominal range to be offset by +/-200mV. This allows the
user considerable flexibility in setting the bottom end
reference point of the signal range, a useful feature when
using single-supply op-amps.
The AD7484 also provides the user with an 8% overrange
capability via a 15th bit. Thus, if the analog input range
strays outside the nominal by up to 8%, the user can still
accurately resolve the signal by using the 15th bit.
The AD7484 is powered from a +4.75V to +5.25V sup-
ply. The part also provides a VDRIVE pin which allows the
user to set the voltage levels for the digital interface lines.
The range for this VDRIVE pin is from +2.7V to +5.25V.
The part is housed in a 48-pin LQFP package and is
specified over a -40°C to +85°C temperature range.
NAP
MODE2
AVDDAGNDCBIASDVDDDGND
VREF3VREF1
VREF2
VIN��
WRITE
MODE1
��
CLIP
STBY
��
VDRIVE
��
D14
D13
D12
D11
D10
PRELIMINARY TECHNICAL DATA
AD7484–SPECIFICATIONS
(TA = 25��C, VDD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V,
fSAMPLE = 3MSPS)
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT/OUTPUT
LOGIC OUTPUTS
CONVERSION RATE
PRELIMINARY TECHNICAL DATA
AD7484
NOTESTemperature ranges as follows: –40°C to +85°C.See TerminologySample tested @ +25°C to ensure compliance
Specifications subject to change without notice.
TIMING CHARACTERISTICS 1,2
ParameterSymbolMinTypMaxUnits
(VDD = 5 V ±5%, AGND = DGND = 0 V, VREF = Internal;
All specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V unless otherwise noted)
Data Read
Acquisition TimetACQTBDns
Conversion TimetCONVTBDns
Quiet Time before Conversion starttQUIETTBDns
Quiet Time during ConversiontQUIET 2TBDns
�� Pulse Widtht1TBDns
�� falling edge to �� falling edget2TBDTBDns
�� falling edge to �� falling edget3TBDns
Bus Access Timet4TBDns
�� falling edge to new Data validt5TBDns
�� rising edge to new Data validt6TBDns
Bus Relinquish Timet7TBDns
�� rising edge to �� rising edget8TBDns
Data Write
WRITE Pulse Widtht9TBDns
Data Setup timet10TBDns
Data Hold timet11TBDns
�� falling edge to WRITE rising edget12TBDns
WRITE falling edge to �� rising edget13TBDns
PRELIMINARY TECHNICAL DATA
AD7484
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +7 V
VDRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +7 V
Analog Input Voltage to GND . .-0.3 V to AVDD + 0.3 V
Digital Input Voltage to GND . .-0.3 V to DVDD + 0.3 V
REF IN to GND . . . . . . . . . . . . .-0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies . . . . . . .±10mA
Operating Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .+150°C
48-Pin LQFP Package, Power Dissipation . . . . . . . .TBD
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . . .50°C/W
�JC Thermal Impedance . . . . . . . . . . . . . . . . . . . 10°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . .+215°C
Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . .+220°CSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TBD
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PIN CONFIGURATION
ORDERING GUIDE
TemperaturePackage
ModelRangeDescriptionOption
AD7484BST-40°C to +85°CLow-profile Quad Flat PackST-48
EVAL-AD7484CB1Evaluation Board
EVAL-CONTROL BRD22Controller Board
NOTESThis can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
AVDD
AGNDAGND
STBY
NAP
WRITE
��D1D2
AGNDAGNDAVDDCLIPMODE1MODE2��D14D13D12D11
AVDD
CBIAS
AGND
AGND
AVDD
AGND
VIN
VREF2
VREF1
VREF3
AGND
AGND
D10
VDRIVE
DGND
DGND
DVDD
��
AD7484
TOP VIEW
(Not to Scale)
PRELIMINARY TECHNICAL DATA
PIN FUNCTION DESCRIPTION
Pin
MnemonicDescription
AVDDPositive power supply for analog circuitry.
CBIASDecoupling pin for internal bias voltage. A 100nF capacitor should be placed between this pin and
AGND.
AGNDPower supply ground for analog circuitry.
VINAnalog input. Single-ended analog input channel.
VREF1Reference Output. VREF1 connects to the output of the internal 2.5V reference. A 1µF capacitor must
be placed between this pin and AGND.
VREF2Reference Input. A 1µF capacitor must be placed between this pin and AGND. When using an external
voltage reference source, the reference voltage should be applied to this pin.
VREF3Reference decoupling pin. When using the internal reference, a 100nF must be connected from this pin
to AGND. When using an external reference source, this pin should be connected directly to AGND.
STBYStandby logic input. When this pin is logic high, the device will be placed in Standby mode. See Power
Saving Section for further details.
NAPNap logic input. When this pin is logic high, the device will be placed in a very low power mode. See
Power Saving Section for further details.
DVDDPositive power supply for digital circuitry.
DGNDGround reference for digital circuitry.
VDRIVELogic Power Supply Input. The voltage supplied at this pin will determine at what voltage
the interface logic of the AD7484 will operate.
��Convert Start Logic Input. A conversion is initiated on the falling edge of �� signal. The input
track/hold amplifier goes from track mode to hold mode and the conversion process commences.
��Reset Logic Input. A logic 0 on this pin resets the internal state machine and terminates a conversion
that may be in progress. Holding this pin low keeps the part in a reset state.
MODE2Operating Mode Logic Input. See Table 3 for details.
MODE1Operating Mode Logic Input. See Table 3 for details.
CLIPLogic input. A logic high on this pin enables output clipping. In this mode, any input voltage that is
greater than positive full scale or less than negative full scale will be clipped to all 1’s or all 0’s
respectively. Further details are given in the Offset / Overrange setion.Chip Select Logic Input. This pin is used in conjunction with �� to access the conversion result. The
data bus is brought out of tri-state and the current contents of the output register driven onto the data
lines following the falling edge of both �� and ��. �� is also used in conjunction with WRITE to
perform a write to the Offset Register. �� can be hardwired permanently low.Read Logic Input. Used in conjunction with �� to access the conversion result.
WRITEWrite Logic Input. Used in conjunction with �� to write data to the Offset Register. When the desired
offset word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling
edge of this pulse which latches in the word into the Offset Register.
��Busy Logic Output. This pin indicates the status of the conversion process. The �� signal goes low
after the falling edge of �� and stays low for the duration of the conversion. In Parallel Mode 2,
the �� signal returns high when the conversion result has been clocked into the output register. In
Parallel Mode 1, the �� signal returns high as soon as the conversion has been completed but the
conversion result does not get clocked into the output register until the falling edge of the next
�� pulse.
D0 - D13Data I/O Bits (D13 is MSB). These are tri-state pins that are controlled by ��, �� and WRITE.
The operating voltage level for these pins is determined by the VDRIVE input.
D14Data Output Bit for overranging. If the over range feature is not used, this pin should be pulled to
DGND via a 100k� resistor.
PRELIMINARY TECHNICAL DATA
AD7484
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a
point 1/2 LSB below the first code transition, and full
scale, a point 1/2 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e AGND + 0.5
LSB
Gain Error
This is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal (i.e., VREF – 1.5
LSB) after the offset error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the
output of the track/hold amplifier to reach its final value,
within ±1/2 LSB, after the end of conversion (the point
at which the track/hold returns to track mode).
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distor-
tion) at the output of the A/D converter. The signal is
the rms amplitude of the fundamental.Noise is the sum
of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on
the number of quantization levels in the digitization
process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is
given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 14-bit converter, this is 86.04dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7484 it
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc.Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7484 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.

Partno	Mfg	Dc	Qty	Available	Descript
AD7484BST	AD	N/a	19	avai	3MSPS, 14-Bit SAR ADC