AD7476ART-AD7478ART Fast Delivery |IC PHOENIX CO.,LIMITED

AD7476ART ,1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23SPECIFICATIONSDD SCLK SAMPLES and B Versions: V = 2.35 V to 5.25 V, f = 12 MHz, f = 600 kSPS unless ..
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AD7476ART-AD7478ART
1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
REV.A
1 MSPS, 12-/10-/8-Bit ADCs
in 6-Lead SOT-23
FUNCTIONAL BLOCK DIAGRAM
SCLK
SDATA
VIN
VDD
GND
FEATURES
Fast Throughput Rate: 1 MSPS
Speciﬁed for VDD of 2.35V to 5.25V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
15 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
70 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 �A Max
6-Lead SOT-23 Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
GENERAL DESCRIPTION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, high-speed, low-power, successive-approximation
ADCs. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low-noise, wide bandwidth track/hold ampliﬁer that can
handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS and the conversion is also initiated at this
point. There are no pipelined delays associated with the part.
The AD7476/AD7477/AD7478 use advanced design techniques
to achieve very low-power dissipation at high throughput rates.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus the
analog input range for the part is 0 to VDD. The conversion rate
is determined by the SCLK.
PRODUCT HIGHLIGHTSFirst 12-/10-/8-bit ADCs in an SOT-23 package.High Throughput with Low Power Consumption.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock speed
increase. This allows the average power consumption to be
reduced while not converting. The part also features a shut-
down mode to maximize power efﬁciency at lower throughput
rates. Power consumption is 1 µA max when in shutdown.Reference derived from the power supply.No Pipeline Delay.
The parts feature a standard successive-approximation ADC
with accurate control of the sampling instant via a CS input
and once-off conversion control.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
AD7476/AD7477/AD7478
AD7476–SPECIFICATIONS1
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
(A Version: VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS unless otherwise noted;
S and B Versions: VDD = 2.35 V to 5.25 V, fSCLK = 12 MHz, fSAMPLE = 600 kSPS unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.)
AD7476/AD7477/AD7478
ANALOG INPUT
LOGIC OUTPUTS
NOTESTemperature ranges as follows: A Version: –40°C to +85°C, S Version: –55°C to +125°C.
AD7477–SPECIFICATIONS1(VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
AD7476/AD7477/AD7478
AD7478–SPECIFICATIONS1
NOTES
1Temperature ranges as follows: A Version: –40°C to +85°C.
(VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7476/AD7477/AD7478 features proprietary ESD protection circuitry, permanent damage
TIMING SPECIFICATIONS1, 2
fSCLK
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.A Version timing specifications apply to the AD7477 S Version; B Version timing specifications apply to the AD7476 S Version.3 V specifications apply from VDD = 2.7 V to 3.6 V for A Version; 3 V specifications apply from VDD = 2.35 V to 3.6 V for B Version; 5 V specifications apply from
VDD = 4.75 V to 5.25 V.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 1 and deﬁned as the time required for the output to cross 0.8 V or 2.0 V.t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.See Power-up Time section.
Speciﬁcations subject to change without notice.
(VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . .–0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C
Military (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 230°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 92°C/W
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
Figure 1.Load Circuit for Digital Output Timing
Speciﬁcations
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this speciﬁcation is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
AD7476/AD7477/AD7478
ORDERING GUIDE
NOTESLinearity Error here refers to integral linearity error.RT = SOT-23.This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7476/
AD7477, the endpoints of the transfer function are zero scale, a
point 1/2 LSB below the ﬁrst code transition, and full scale, a
point 1/2 LSB above the last code transition. For the AD7478,
the endpoints of the transfer function are zero scale, a pointLSB below the first code transition, and full scale, a pointLSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the ﬁrst code transition (00 . . . 000)
to (00 . . . 001) from the ideal (i.e., AGND + 0.5 LSB). For
the AD7478, this is the deviation of the first code transition
(00 . . . 000) to (00 . . . 001) from the ideal (i.e., AGND +
1 LSB).
Gain Error
For the AD7476/AD7477, this is the deviation of the last code
transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e.,
VREF – 1.5 LSB) after the offset error has been adjusted out.
For the AD7478, this is the deviation of the last code transi-
tion (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF
– 1 LSB) after the offset error has been adjusted.
Track/Hold Acquisition Time
The track/hold ampliﬁer returns into track mode after the end
of conversion. Track/Hold acquisition time is the time required
for the output of the track/hold ampliﬁer to reach its ﬁnal value,
within ±0.5 LSB, after the end of conversion. See Serial Inter-
face Timing section for more detail.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms amplitude
of the fundamental.Noise is the sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent on the number of quantization levels in
the digitization process; the more levels, the smaller the quanti-
zation noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB and for a 10-bit con-
verter it is 62 dB, for an 8-bit converter it is 50dB.
Total Unadjusted Error
This is a comprehensive specification which includes gain error,
linearity error, and offset error.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7476/AD7477/
AD7478 it is deﬁned as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is deﬁned as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this speciﬁcation is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7476/AD7477/AD7478 are tested using the CCIF standard
where two input frequencies are used, fa = 498.7 kHz and
fb = 508.7kHz. In this case, the second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
speciﬁed separately. The calculation of the intermodulation
distortion is as per the THD speciﬁcation where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
AD7476/AD7477/AD7478
PERFORMANCE CURVES
Figure 2 shows a typical FFT plot for the AD7476 at 1 MHz
sample rate and 100 kHz input frequency.
FREQUENCY – kHz
SNR – dB100150200250300350400450500
–115
Figure 2.AD7476 Dynamic Performance at 1 MSPS
Figure 3 shows a typical FFT plot for the AD7476 at 600 kHz
sample rate and 100 kHz input frequency.
FREQUENCY – kHz
SNR
dB100150200250300
–15
Figure 3.AD7476 Dynamic Performance at 600 kSPS
Figure 4 shows a typical FFT plot for the AD7477 at 1 MHz
sample rate and 100 kHz input frequency.
SNR
dB
–10
Figure 5 shows a typical FFT plot for the AD7478 at 1MHz
sample rate and 100kHz input frequency.
FREQUENCY – kHz
SNR
dB
–90
Figure 5.AD7478 Dynamic Performance at 1MSPS
Figure 6 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 993 kSPS with an SCLK frequency of 20 MHz.
INPUT FREQUENCY – Hz
10k
SINAD
dB
100k1M
Figure 6.AD7476 SINAD vs. Input Frequency at 993 kSPS
Figure 7 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 605 kSPS with a SCLK frequency of 12 MHz.

Partno	Mfg	Dc	Qty	Available	Descript
AD7476ART	AD	N/a	191	avai	1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7478ART	AD	N/a	9	avai	1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23