AD7476ABRM ,2.35 V to 5.25 V/ 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SC70FEATURES FUNCTIONAL BLOCK DIAGRAMFast Throughput Rate: 1 MSPSVDDSpecified for V of 2.35 V to 5.25 V ..
AD7476ABRM ,2.35 V to 5.25 V/ 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SC70GENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit 1. ..
AD7476ART ,1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23SPECIFICATIONSDD SCLK SAMPLES and B Versions: V = 2.35 V to 5.25 V, f = 12 MHz, f = 600 kSPS unless ..
AD7476ART-REEL , 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7476ARTZ-REEL7 , 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7476BRTZ-REEL , 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
ADG1408YRUZ , Multi-Cal-System Evaluation Module
ADG1408YRUZ , Multi-Cal-System Evaluation Module
ADG1408YRUZ-REEL7 , 4.7 OHM maximum on resistance
ADG1409YRUZ-REEL7 , 4.7 OHM maximum on resistance
ADG1434YCPZ-REEL7 , 4 OHM RON, Triple/Quad SPDT -15 V/12 V/-5 V iCMOS Switches
ADG1434YRUZ , 4 OHM RON, Triple/Quad SPDT -15 V/12 V/-5 V iCMOS Switches
AD7476ABRM-AD7478AARM
2.35 V to 5.25 V/ 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SC70
REV.C
2.35 V to 5.25 V, 1 MSPS,
12-/10-/8-Bit ADCs in 6-Lead SC70
FEATURES
Fast Throughput Rate: 1 MSPS
Specified for VDD of 2.35V to 5.25V
Low Power:
3.6 mW Typ at 1 MSPS with 3 V Supplies
12.5 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth:
71 dB SNR at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Standby Mode: 1 �A Max
6-Lead SC70 Package
8-Lead MSOP Package
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High Speed Modems
Optical Sensors
FUNCTIONAL BLOCK DIAGRAM
GND
VDD
VIN
SCLK
SDATA
GENERAL DESCRIPTIONThe AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit
high speed, low power, successive-approximation ADCs, respec-
tively. The parts operate from a single 2.35 V to 5.25 V power
supply and feature throughput rates up to 1 MSPS. The parts
contain a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 13 MHz.
The conversion process and data acquisition are controlled using
CS and the serial clock, allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS, and the conversion is also initiated at this point.
There are no pipeline delays associated with the parts.
The AD7476A/AD7477A/AD7478A use advanced design tech-
niques to achieve low power dissipation at high throughput rates.
The reference for the part is taken internally from VDD, which
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 to VDD. The conversion rate is
determined by the SCLK.
PRODUCT HIGHLIGHTSFirst 8-/10-/12-bit ADCs in an SC70 package.High throughput with low power consumption.Flexible power/serial clock speed management. The conversion
rate is determined by the serial clock, allowing the conver-
sion time to be reduced through the serial clock speed increase.
This allows the average power consumption to be reduced
when a power-down mode is used while not converting. The
parts also feature a power-down mode to maximize power
efficiency at lower throughput rates. Current consumption isµA max and 50 nA typically when in power-down mode.Reference derived from the power supply.No pipeline delay. The parts feature a standard successive-
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
*.Patent No. 6,681,332.
AD7476A/AD7477A/AD7478A
(VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise noted;
TA = TMIN to TMAX, unless otherwise noted.)AD7476A–SPECIFICATIONS1DYNAMIC PERFORMANCE
LOGIC INPUTS
AD7476A/AD7477A/AD7478A
AD7477A–SPECIFICATIONS1(VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise noted;
TA = TMIN to TMAX, unless otherwise noted.)NOTESTemperature ranges as follows: A, B Grades: –40°C to +85°C, Y Grade: –40°C to +125°C.Operational from VDD = 2.0 V, with input low voltage (VINL) 0.35 V max.See Terminology section.B and Y Grades, maximum specifications apply as typical figures when VDD = 4.75 V to 5.25 V.SC70 values guaranteed by characterization.Guaranteed by characterization.See Power vs. Throughput Rate section.
Specifications subject to change without notice.
AD7476A/AD7477A/AD7478A
AD7478A–SPECIFICATIONS1(VDD = 2.35 V to 5.25 V, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, unless otherwise noted;
TA = TMIN to TMAX, unless otherwise noted.)NOTES
1Temperature range from –40°C to +85°C.
2Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V min.
3See Terminology section.
4SC70 values guaranteed by characterization.
5Guaranteed by characterization.
6See Power vs. Throughput Rate section.
Specifications subject to change without notice.
AD7476A/AD7477A/AD7478ALOGIC INPUTS
NOTESTemperature range from –40°C to +85°C.Operational from VDD = 2.0 V, with input high voltage (VINH) 1.8 V min.See Terminology section.SC70 values guaranteed by characterization.Guaranteed by characterization.See Power vs. Throughput Rate section.
Specifications subject to change without notice.
AD7476A/AD7477A/AD7478A
TIMING SPECIFICATIONS1
(VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.)NOTESGuaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.Mark/space ratio for the SCLK input is 40/60 to 60/40.Minimum fSCLK at which specifications are guaranteed.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when VDD = 2.35 V and 0.8 V or 2.0 V for VDD > 2.35 V.Measured with 50 pF load capacitor.t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.t7 values also apply to t8 minimum values.See Power-Up Time section.
Specifications subject to change without notice.
Figure 1.Load Circuit for Digital Output Timing Specifications
Timing Example 1Having fSCLK = 20 MHz and a throughput of 1 MSPS gives a
cycle time of t2 + 12.5 (1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min,
this leaves tACQ to be 365ns. This 365 ns satisfies the requirement
of 250 ns for tACQ. From Figure 3, tACQ is comprised of 2.5 (1/fSCLK)
+ t8 + tQUIET, where t8 = 36 ns max. This allows a value of 204ns
for tQUIET, satisfying the minimum requirement of 50ns.
Figure 2.AD7476A Serial Interface Timing Diagram
Figure 3.Serial Interface Timing Example
Timing Example 2Having fSCLK = 5 MHz and a throughput of 315 kSPS gives a
cycle time of t2 + 12.5 (1/fSCLK) + tACQ = 3.174 µs. With t2 =ns min, this leaves tACQ to be 664 ns. This 664 ns satisfies
the requirement of 250 ns for tACQ. From Figure 3, tACQ is
comprised of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This
allows a value of 128ns for tQUIET, satisfying the minimum
requirement of 50ns. As in this example and with other slower
clock values, the signal may already be acquired before the
conversion is complete, but it is still necessary to leave 50ns
minimum tQUIET between conversions. In Example 2, the
signal should be fully acquired at approximately Point C in
Figure 3.
AD7476A/AD7477A/AD7478A
ABSOLUTE MAXIMUM RATINGS1(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin except Supplies2 . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A and B Grades) . . . . . . . . . –40°C to +85°C
Industrial (Y Grade) . . . . . . . . . . . . . . . .–40°C to +125°C
Storage Temperature Range . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
MSOP Package
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . 205.9°C/W
�JC Thermal Impedance . . . . . . . . . . . . . . . . . . 43.74°C/W
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment, and can discharge without detection. Although
the AD7476A/AD7477A/AD7478A feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SC70 Package
�JA Thermal Impedance . . . . . . . . . . . . . . . . . . 340.2°C/W
�JC Thermal Impedance . . . . . . . . . . . . . . . . . . 228.9°C/W
Lead Temperature, Soldering
Reflow (10 sec to 30 sec) . . . . . . . . . . . . . . . .235 (0/+5)°C
Pb-free Temperature Soldering
Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255 (0/+5)°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDENOTESLinearity error here refers to integral nonlinearity.KS = SC70; RM = MSOP.Z = Pb-free part.This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit, allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order
a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g., EVAL-AD7476ACB, the EVAL-CONTROLBRD2, and a
12 V ac transformer. See relevant evaluation board application note for more information.
AD7476A/AD7477A/AD7478A
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTIONSSDATA
8-Lead MSOP
6-Lead SC70
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7476A/
AD7477A/AD7478A, the endpoints of the transfer function are
zero scale, a point 1LSB below the first code transition, and full
scale, a point 1LSB above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1LSB
change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain ErrorThis is the deviation of the last code transition (111 . . . 110)
to (111 . . . 111) from the ideal, i.e., VREF – 1 LSB after the
offset error has been adjusted out.
Track-and-Hold Acquisition TimeThe track-and-hold amplifier returns to track mode at the end
of conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach its
final value, within ±0.5 LSB, after the end of conversion. See
the Serial Interface section for more details.
Signal-to-(Noise + Distortion) Ratio (SINAD)This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, it is 74dB for a 12-bit converter, 62 dB for a 10-bit con-
verter, and 50 dB for an 8-bit converter.
Total Unadjusted Error (TUE)This is a comprehensive specification that includes the gain,
linearity, and offset errors.
Total Harmonic Distortion (THD)Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. It is defined as
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum. But for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation Distortion (IMD)With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb, where m and
n= 0, 1, 2, 3, and so on.Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second-order terms include (fa + fb) and (fa – fb), while the
third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).
The AD7476A/AD7477A/AD7478A are tested using the CCIF
standard where two input frequencies are used (see fa and fb on
the specification pages). In this case, the second-order terms are
usually distanced in frequency from the original sine waves, while
the third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms are
specified separately. The calculation of the intermodulation dis-
tortion is per the THD specification, where it is the ratio of the
rms sum of the individual distortion products to the rmsamplitude
of the sum of the fundamentals expressed in dBs.
AD7476A/AD7477A/AD7478ATPC 1.AD7476A Dynamic Performance at 1 MSPS
TPC 2.AD7477A Dynamic Performance at 1 MSPS
TPC 3.AD7478A Dynamic Performance at 1 MSPS
TPC 4.AD7476A SINAD vs. Input Frequency at 1 MSPS
TPC 1, TPC 2, and TPC 3 each show a typical FFT plot for the
AD7476A, AD7477A, and AD7478A, respectively, at a 1 MSPS
sample rate and 100 kHz input frequency.
TPC 4 shows the signal-to-(noise + distortion) ratio performance
versus the input frequency for various supply voltages while sampling
at 1MSPS with an SCLK frequency of 20 MHz for the AD7476A.
TPC 5 and TPC 6 show INL and DNL performance for the
AD7476A.
TPC 7 shows a graph of the total harmonic distortion versus the
analog input frequency for different source impedances when
using a supply voltage of 3.6V and sampling at a rate of 1MSPS
(see Analog Input section).
TPC 8 shows a graph of the total harmonic distortion versus the
analog input signal frequency for various supply voltages while
sampling at 1 MSPS with an SCLK frequency of 20 MHz.
–Typical Performance Characteristics
