AD7475ARM-AD7475BR-AD7495BRM Fast Delivery |IC PHOENIX CO.,LIMITED

AD7475ARM ,1 MSPS, 12-Bit ADCsGENERAL DESCRIPTIONVDRIVEThe AD7475/AD7495 are 12-bit high-speed, low-power,AD7495successive-approx ..
AD7475BR ,1 MSPS, 12-Bit ADCsfeatures a standard successive-sion time is determined by the SCLK frequency.approximation ADC with ..
AD7476ABRM ,2.35 V to 5.25 V/ 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SC70FEATURES FUNCTIONAL BLOCK DIAGRAMFast Throughput Rate: 1 MSPSVDDSpecified for V of 2.35 V to 5.25 V ..
AD7476ABRM ,2.35 V to 5.25 V/ 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SC70GENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7476A/AD7477A/AD7478A are 12-bit, 10-bit, and 8-bit 1. ..
AD7476ART ,1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23SPECIFICATIONSDD SCLK SAMPLES and B Versions: V = 2.35 V to 5.25 V, f = 12 MHz, f = 600 kSPS unless ..
AD7476ART-REEL , 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
ADG1308BRUZ , 4- and 8-Channel -15 V/12 V Multiplexers
ADG1308BRZ , 4- and 8-Channel -15 V/12 V Multiplexers
ADG1408YRUZ , Multi-Cal-System Evaluation Module
ADG1408YRUZ , Multi-Cal-System Evaluation Module
ADG1408YRUZ-REEL7 , 4.7 OHM maximum on resistance
ADG1409YRUZ-REEL7 , 4.7 OHM maximum on resistance

AD7475ARM-AD7475BR-AD7495BRM
1 MSPS, 12-Bit ADCs
REV.AMSPS,
12-Bit ADCs
FUNCTIONAL BLOCK DIAGRAMS
VIN
GND
VDD
SCLKSDATA
VDRIVE
REF IN
VIN
GND
VDD
SCLKSDATA
VDRIVE
REF OUT
PRODUCT HIGHLIGHTSHigh throughput with low power consumption. The
AD7475 offers 1MSPS throughput rates with 4.5mW
power consumption.Single-supply operation with VDRIVE function. The AD7475/
AD7495 operate from a single 2.7V to 5.25V supply. The
VDRIVE function allows the serial interface to connect directly
to either 3V or 5V processor systems independent of VDD.Flexible power/serial clock speed management. The con-
version rate is determined by the serial clock, allowing the
conversion time to be reduced through the serial clock speed
increase. The part also features shutdown modes to maximize
power efficiency at lower throughput rates. This allows the
average power consumption to be reduced while not convert-
ing. Power consumption is 1 µA when in full shutdown.No pipeline delay. The part features a standard successive-
approximation ADC with accurate control of the sampling
instant via a CS input and once off conversion control.
FEATURES
Fast Throughput Rate: 1MSPS
Specified for VDD of 2.7V to 5.25V
Low Power:
4.5mW Max at 1MSPS with 3V Supplies
10.5mW Max at 1MSPS with 5V Supplies
Wide Input Bandwidth:dB SNR at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High-Speed Serial Interface SPI™/QSPI™/
MICROWIRE™/DSP-Compatible
On-Board Reference 2.5V (AD7495 Only)
Standby Mode: 1�A Max
8-Lead �SOIC and SOIC Packages
APPLICATIONS
Battery-Powered Systems
Personal Digital Assistants
Medical Instruments
Mobile Communications
Instrumentation and Control Systems
Data Acquisition Systems
High-Speed Modems
Optical Sensors
GENERAL DESCRIPTION
The AD7475/AD7495 are 12-bit high-speed, low-power,
successive-approximation ADCs. The parts operate from a single
2.7V to 5.25V power supply and feature throughput rates up toMSPS. The parts contain a low-noise, wide bandwidth track/hold
amplifier that can handle input frequencies in excess of 1MHz.
The conversion process and data acquisition are controlled using
CS and the serial clock allowing the devices to interface with
microprocessors or DSPs. The input signal is sampled on the
falling edge of CS and conversion is also initiated at this point.
There are no pipelined delays associated with the part.
The AD7475/AD7495 use advanced design techniques to achieve
very low power dissipation at high throughput rates. With 3V
supplies and 1MSPS throughput rate, the AD7475 consumes just
1.5mA, while the AD7495 consumes 2mA. With 5V supplies
and 1MSPS, the current consumption is 2.1mA for the AD7475
and 2.6mA for the AD7495.
The analog input range for the part is 0 V to REF IN. The 2.5V
reference for the AD7475 is applied externally to the REF IN pin
while the AD7495 has an on-board 2.5V reference. The conver-
sion time is determined by the SCLK frequency.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
AD7475/AD7495–SPECIFICATIONS1
AD7475–SPECIFICATIONS1
DYNAMIC PERFORMANCE
LOGIC OUTPUTS
(VDD = 2.7V to 5.25V, VDRIVE = 2.7V to 5.25V, REF IN = 2.5V, fSCLK = 20MHz unless otherwise
noted; TA = TMIN to TMAX, unless otherwise noted.)
AD7475/AD7495AD7475–SPECIFICATIONS (continued)
POWER REQUIREMENTS
NOTESTemperature ranges as follows: A, B Versions: –40�C to +85�C.Sample tested @ 25�C to ensure compliance.See Power Versus Throughput Rate section.
Specifications subject to change without notice.
(VDD = 2.7V to 5.25V, VDRIVE = 2.7V to 5.25V, fSCLK = 20MHz unless otherwise noted; TA = TMIN to
TMAX, unless otherwise noted.)AD7495–SPECIFICATIONS1
AD7475/AD7495–SPECIFICATIONS1
AD7495–SPECIFICATIONS (continued)
CONVERSION RATE
POWER REQUIREMENTS
NOTESTemperature ranges as follows: A, B Versions: –40�C to +85�C.Sample tested @ 25�C to ensure compliance.See Power Versus Throughput Rate section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(VDD = 2.7V to 5.25V, VDRIVE = 2.7V to 5.25V, REF IN = 2.5V (AD7475); TA = TMIN to TMAX, unless
otherwise noted.)
NOTESSample tested at 25�C to ensure compliance. All input signals are specified with tr = tf = 5ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8V or 2.0V.t8 and t9 are derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the times, t8 and t9, quoted in the timing characteristics are
Figure 1.Serial Interface Timing Diagram
Timing Example 1
Having fSCLK = 20MHz and a throughput of 1MSPS gives a cycle
time of t2 + 12.5(1/fSCLK) + tACQ = 1µs. With t2 = 10ns min, this
leaves tACQ to be 365ns. This 365ns satisfies the requirement of
300ns for tACQ. From Figure 2, tACQ comprises of 2.5(1/fSCLK) + t8
+ tQUIET, where t8 = 45 ns. This allows a value of 195ns for tQUIET,
satisfying the minimum requirement of 100ns.
Timing Example 2
Having fSCLK = 5 MHz and a throughput of 315KSPS, gives a
cycle time of t2 + 12.5(1/fSCLK) + tACQ = 3.174�s.
With t2 = 10 ns min, this leaves tacq to be 664ns. This 664 ns
satisfies the requirement of 300ns for tACQ. From Figure 2, tACQ
is comprised of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 45ns. This allows
a value of 119ns for tQUIET satisfying the minimum requirement
of 100ns. As in this example and with other slower clock values,
the signal may already be acquired before the conversion is
complete, but it is still necessary to leave 100ns minimum
tQUIET between conversions. In Example 2 the signal should be
fully acquired at approximately Point C in Figure 2.
Figure 2.Serial Interface Timing Example
Figure 3.Load Circuit for Digital Output Timing Specifications
AD7475/AD7495
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7475/AD7495 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1
(TA = 25�C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
VDRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
Analog Input Voltage to GND . . . . . . . . –0.3V to VDD + 0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3V to +7V
VDRIVE to DVDD . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to GND . . . . . . –0.3V to VDD + 0.3V
REF IN to GND . . . . . . . . . . . . . . . . . . –0.3V to VDD + 0.3V
Input Current to Any Pin Except Supplies2 . . . . . . . �10mA
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . . –40�C to +85�C
Storage Temperature Range . . . . . . . . . . . –65�C to +150�C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150�C
SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450mW
�JA Thermal Impedance . . . . . . . . . . . . . . 157�C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9�C/W (µSOIC)
�JC Thermal Impedance . . . . . . . . . . . . . . . 56�C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74�C/W (µSOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215�C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220�C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.Transient currents of up to 100mA will not cause SCR latch-up.
PIN CONFIGURATIONS
AD7475 SOIC/�SOIC
AD7495 SOIC/�SOIC
ORDERING GUIDE
AD7495AR
NOTESLinearity Error here refers to Integral Linearity Error.SO = SOIC; RM = µSOIC.This can be used as a standalone evaluation board or in conjunction with the EVAL-BOARD CONTROLLER for evaluation/demonstration purposes.This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in
the CB designators.
PIN FUNCTION DESCRIPTIONS
6VDRIVE
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints of the
transfer function are zero scale, a point 1/2 LSB below the first
code transition, and full scale, a point 1/2 LSB above the last
code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 0.5LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1.5LSB) after the offset
error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode on the 13th
SCLK rising edge (see Serial Interface section). The Track/Hold
Acquisition Time is the minimum time required for the track-
and-hold amplifier to remain in track mode for its output to
reach and settle to within 0.5LSB of the applied input signal,
given a step change to the input signal.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7475/AD7495, it is
defined as:
where V1 is the rms amplitude of the fundamental and V2, V3, V4,
V5 and V6 are the rms amplitudes of the second through the sixth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to fS/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the har-
monics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa � nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are those
for which neither m nor n is equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7475/AD7495 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as per
AD7475/AD7495
AD7475/AD7495 TYPICAL PERFORMANCE CURVES
TPC 1 shows a typical FFT plot for the AD7475 at 1MHz
sample rate and 100kHz input frequency.
FREQUENCY – kHz
SINAD – dB100150200250300
–15
TPC 1.AD7475 Dynamic Performance
TPC 2 shows a typical FFT plot for the AD7495 at 1MHz sample
rate and 100kHz input frequency.
FREQUENCY – kHz
SINAD
dB100150200250300
–15
TPC 2.AD7495 Dynamic Performance
TPC 3 shows the signal-to-(noise + distortion) ratio performance
versus input frequency for various supply voltages while sampling
at 1MSPS with an SCLK of 20MHz.
SINAD
dB
CIRCUIT INFORMATION
The AD7475/AD7495 are fast, micropower, 12-bit, single-supply,
A/D converters. The parts can be operated from a 2.7V to 5.25 V
supply. When operated from either a 5 V supply or a 3 V sup-
ply, the AD7475/AD7495 are capable of throughput rates ofMSPS when provided with a 20MHz clock.
The AD7475/AD7495 provide the user with an on-chip track/
hold, A/D converter, and a serial interface housed in either an
8-lead SOIC or µSOIC package, which offers the user considerable
space-saving advantages over alternative solutions. The AD7495
also has an on-chip 2.5V reference. The serial clock input accesses
data from the part but also provides the clock source for the
successive-approximation A/D converter. The analog input range
is 0 V to REF IN for the AD7475 and 0 V to REF OUT for
the AD7495.
The AD7475/AD7495 also feature power-down options to allow
power saving between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7475/AD7495 are 12-bit successive approximation
analog-to-digital converters based around a capacitive DAC.
The AD7475/AD7495 can convert analog input signals in the
range 0V to 2.5 V. Figures 4 and 5 show simplified schematics
of the ADC. The ADC comprises of Control Logic, SAR and a
Capacitive DAC, which are used to add and subtract fixed
amounts of charge from the sampling capacitor to bring the
comparator back into a balanced condition. Figure 4 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on VIN.
Figure 4.ADC Acquisition Phase
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to position B causing the compara-
tor to become unbalanced. The Control Logic and the Capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the ADC
output code. Figure 6 shows the ADC transfer function.

Partno	Mfg	Dc	Qty	Available	Descript
AD7475ARM	AD	N/a	15	avai	1 MSPS, 12-Bit ADCs
AD7475BR	AD	N/a	2	avai	1 MSPS, 12-Bit ADCs
AD7495BRM	AD	N/a	1	avai	1 MSPS, 12-Bit ADCs