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ADG1308BRUZ , 4- and 8-Channel -15 V/12 V Multiplexers
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ADG1408YRUZ , Multi-Cal-System Evaluation Module
ADG1408YRUZ , Multi-Cal-System Evaluation Module
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ADG1409YRUZ-REEL7 , 4.7 OHM maximum on resistance
AD7472BR-AD7472BRU
1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
REV. A
1.75 MSPS, 4 mW
10-Bit/12-Bit Parallel ADCs
FUNCTIONAL BLOCK DIAGRAM
VIN
CONVST
AGNDDGND
AVDDDVDDREF INVDRIVE
DB9 (DB11)
DB0
CLK IN
BUSY
AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS.
AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS.
FEATURES
Specified for VDD of 2.7V to 5.25V
1.75 MSPS for AD7470 (10-Bit)
1.5 MSPS for AD7472 (12-Bit)
Low Power
AD7470:3.34 mW Typ at 1.5 MSPS with 3 V Supplies
7.97 mW Typ at 1.75 MSPS with 5 V Supplies
AD7472:3.54 mW Typ at 1.2 MSPS with 3 V Supplies
8.7 mW Typ at 1.5 MSPS with 5 V Supplies
Wide Input Bandwidth
70 dB Typ SNR at 500 kHz Input Frequency
Flexible Power/Throughput Rate Management
No Pipeline Delays
High Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages
GENERAL DESCRIPTIONThe AD7470/AD7472 are 10-bit/12-bit high speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for
the 10-bit AD7470. The parts contain a low noise, wide band-
width track/hold amplifier that can handle input frequencies in
excess of 1 MHz.
The conversion process and data acquisition are controlled
using standard control inputs allowing easy interfacing to
microprocessors or DSPs. The input signal is sampled on the
falling edge of CONVST and conversion is also initiated at
this point. The BUSY goes high at the start of conversion and
goes low 531.66ns after falling edge of CONVST (AD7472 with
a clock frequency of 26MHz) to indicate that the conversion is
complete. There are no pipelined delays associated with the part.
The conversion result is accessed via standard CS and RD sig-
nals over a high speed parallel interface.
The AD7470/AD7472 uses advanced design techniques to
achieve very low power dissipation at high throughput rates. With
3 V supplies and 1.5 MSPS throughput rate, the AD7470 typi-
cally consumes, on average, just 1.1 mA. With 5 V supplies and
1.75 MSPS, the average current consumption is typically
1.6 mA. The part also offers flexible power/throughput rate
management. Operating the AD7470 with 3 V supplies and
500 kSPS throughput reduces the current consumption to 713 µA.
At 5 V supplies and 500 kSPS, the part consumes 944 µA.
It is also possible to operate the parts in an auto sleep mode,
where the part wakes up to do a conversion and automatically
enters sleep mode at the end of conversion. Using this method
allows very low power dissipation numbers at lower throughput
rates. In this mode, the AD7472 can be operated with 3 V sup-
plies at 100 kSPS, and consume an average current of just 124 µA.
At 5 V supplies and 100 kSPS, the average current consumption
is 171 µA.
The analog input range for the part is 0 to REF IN. The +2.5 V
reference is applied externally to the REF IN pin. The conver-
sion rate is determined by the externally-applied clock.
PRODUCT HIGHLIGHTSHigh Throughput with Low Power Consumption. The
AD7470 offers 1.75 MSPS throughput and the AD7472
offers 1.5 MSPS throughput rates with 4 mW power
consumption.Flexible Power/Throughput Rate Management. The conver-
sion rate is determined by an externally-applied clock allow-
ing the power to be reduced as the conversion rate is reduced.
The part also features an auto sleep mode to maximize power
efficiency at lower throughput rates.No Pipeline Delay. The part features a standard successive-
approximation ADC with accurate control of the sampling
instant via a CONVST input and once off conversion
control.
AD7470/AD7472
AD7470–SPECIFICATIONS1(VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, fCLK IN = 30 MHz @ 5 V and 24 MHz @ 3 V;
TA = TMIN to TMAX3, unless otherwise noted.)DC ACCURACY
ANALOG INPUT
REFERENCE INPUT
LOGIC INPUTS
LOGIC OUTPUTS
CONVERSION RATE
POWER REQUIREMENTS
NOTES
1Temperature ranges as follows: A Version: -40°C to +85°C.The AD7470 functionally works at 2.35 V. Typical specifications @ +25°C for SNR (100 kHz) = 59 dB; THD (100 kHz) = –84 dB; INL ±0.8 LSB.
3The AD7470 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 20 MHz @ 5 V and 16MHz @ 3V. Typical Sleep Mode current @ +125°C is 700 nA.
AD7470/AD7472
AD7472–SPECIFICATIONS1(VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, fCLK IN = 26 MHz @ 5 V and 20 MHz @ 3 V;
TA = TMIN to TMAX3, unless otherwise noted.)NOTESTemperature ranges as follows: A and B Versions: –40°C to +85°C.The AD7472 functionally works at 2.35 V. Typical specifications @ +25°C for SNR (100 kHz) = 68 dB; THD (100 kHz) = –84 dB; INL ±0.8 LSB.
AD7470/AD7472NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Figure 1.Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10ns min from falling edge of CONVST.t2 is 35 ns max @ +125°C.Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1(VDD = +2.7 V to +5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)Figure 1.Load Circuit for Digital Output Timing Specifications
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7470/AD7472 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
AVDD to AGND/DGND . . . . . . . . . . . . . . . . .–0.3 V to +7 V
DVDD to AGND/DGND . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VDRIVE to AGND/DGND . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VDRIVE to DVDD . . . . . . . . . . . . . . .–0.3 V to DVDD + 0.3 V
AGND TO DGND . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Analog Input Voltage to AGND . . .–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . .–0.3 V to DVDD + 0.3 V
REF IN to AGND . . . . . . . . . . . . . .–0.3 V to AVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . .±10 mA
Operating Temperature Range
Commercial (A and B Version) . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SOIC, TSSOP Package Dissipation . . . . . . . . . . . . .+450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . .75°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115°C/W (TSSOP)
θJC Thermal Impedance . . . . . . . . . . . . . . .25°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDENOTESR = SOIC; RU = TSSOP.This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
PIN CONFIGURATIONS
AD7470/AD7472
PIN FUNCTION DESCRIPTION
TERMINOLOGY
Integral NonlinearityThis is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain ErrorThe last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7470/
AD7472). The gain error is the deviation of the actual difference
between the first and last code transitions from the ideal differ-
ence between the first and last code transitions with offset errors
removed.
Track/Hold Acquisition TimeThe track/hold amplifier returns into track mode after the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within ±1 LSB, after the end of conversion.
Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental.Noise is the sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB and for a 10-bit con-
verter is 62 dB.
Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7470/AD7472 it is
defined as:
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious NoisePeak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc.Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
The AD7470/AD7472 are tested using the CCIF standard
where two input frequencies near the top end of the input band-
width are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Aperture DelayIn a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture JitterAperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise which modulates the phase of
the hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error will increase as the input dV/dt
increases.
AD7470/AD7472
CIRCUIT DESCRIPTION
CONVERTER OPERATIONThe AD7470/AD7472 is a 10-bit/12-bit successive approxima-
tion analog-to-digital converter based around a capacitive DAC.
The AD7470/AD7472 can convert analog input signals in the
range 0 V to VREF. Figure 2 shows a very simplified schematic of
the ADC. The Control Logic, SAR and the Capacitive DAC
are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition.
COMPARATOR
OUTPUT DATA
10-/12-BIT PARALLEL
VIN
VREF
CONTROL
INPUTSFigure 2.Simplified Block Diagram of AD7470/AD7472
Figure 3 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN.
Figure 3.ADC Acquisition Phase
Figure 4 shows the ADC during conversion. When conversion
starts SW2 will open and SW1 will move to position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the compara-
tor is rebalanced, the conversion result is available in the SAR
register.
Figure 4.ADC Conversion Phase
TYPICAL CONNECTION DIAGRAMFigure 5 shows a typical connection diagram for the AD7470/
AD7472. Conversion is initiated by a falling edge on CONVST.
Once CONVST goes low the BUSY signal goes high, and at the
end of conversion the falling edge of BUSY is used to activate
an Interrupt Service Routine. The CS and RD lines are then
activated in parallel to read the 10- or 12-data bits. The recom-
mended REF IN voltage is 2.5 V providing an analog input
range of 0 V to 2.5 V, making the AD7470/AD7472 a unipolar
A/D. It is recommended to perform a dummy conversion after
power-up as the first conversion result could be incorrect. This
also ensures that the part is in the correct mode of operation.
The CONVST pin should not be floating when power is applied
as a rising edge on CONVST might not wake up the part.
In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic
output voltage values being either 0 V or DVDD. The voltage
applied to VDRIVE controls the voltage value of the output logic
signals. For example, if DVDD is supplied by a 5 V supply and
VDRIVE by a 3 V supply, the logic output voltage levels would be
either 0 V or 3 V. This feature allows the AD7470/AD7472 to
interface to 3 V parts while still enabling the A/D to process
signals at 5 V supply.
Figure 5.Typical Connection Diagram
