AD7466BRM-REEL ,1.8 V Micro-Power 12-Bit ADC in 6-Lead SOT-23GENERAL DESCRIPTION PRODUCT HIGHLIGHTS 1The AD7466/AD7467/AD7468 are 12-, 10-, and 8-bit, high 1. S ..
AD7466BRMZ ,1.8 V Micro-Power 12-Bit ADC in 6-Lead SOT-23SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. T ..
AD7466BRT-REEL7 , 1.6 V, Micropower 12-/10-/8-Bit ADCs
AD746AQ ,Dual Precision, 500 ns Settling, BiFET Op Ampspecifications are guaranteed, although only those shown in boldface are tested on all production u ..
AD746BQ ,Dual Precision, 500 ns Settling, BiFET Op AmpSpecifications are guaranteed maximum at either input after 5 minutes of operation at T = +25°C. Fo ..
AD746JN ,Dual Precision, 500 ns Settling, BiFET Op Ampapplications.bias current between its two amplifiers.The AD746 is internally compensated for stable ..
ADG1204YRUZ , Low Capacitance, Low Charge Injection, ±15 V/12 V, 4:1 iCMOS Multiplexer
ADG1207YRUZ , Low Capacitance, 16- and 8-Channel -15 V/12 V iCMOS Multiplexers
ADG1208YCPZ-REEL7 , Low Capacitance, 4-/8-Channel -15 V/12 V iCMOS Multiplexers
ADG1208YRUZ , Low Capacitance, 4-/8-Channel -15 V/12 V iCMOS Multiplexers
ADG1211YRUZ ,2 pF Off Cap, 1 pC Qinj ± 15/12 V Quad SPST SwitchesSPECIFICATIONS SINGLE SUPPLY V = 15 V ± 10%, V = −15 V, GND = 0 V, unless otherwise noted. DD SSTab ..
ADG1213YCPZ-500RL7 , Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS Quad SPST Switches
AD7466BRM-REEL-AD7466BRMZ
1.8 V Micro-Power 12-Bit ADC in 6-Lead SOT-23
1.6 V, Micropower
12-, 10-, and 8-Bit ADCs in 6-Lead SOT-23
Rev. A
FEATURES
Specified for VDD of 1.6 V to 3.6 V
Low power:
0.62 mW typ at 100 kSPS with 3 V supplies
0.48 mW typ at 50 kSPS with 3.6 V supplies
0.12 mW typ at 100 kSPS with 1.6 V supplies
Fast throughput rate: 200 kSPS
Wide input bandwidth:
71 dB SNR at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface:
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Automatic power-down
Power-down mode: 8 nA typ
6-lead SOT-23 package
8-lead MSOP package
APPLICATIONS
Battery-powered systems
Medical instruments
Remote data acquisition
Isolated data acquisition
GENERAL DESCRIPTION The AD7466/AD7467/AD74681 are 12-, 10-, and 8-bit, high
speed, low power, successive approximation ADCs, respectively.
The parts operate from a single 1.6 V to 3.6 V power supply and
feature throughput rates up to 200 kSPS with low power
dissipation. The parts contain a low noise, wide bandwidth
track-and-hold amplifier, which can handle input frequencies in
excess of 3 MHz.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to VDD. The conversion
rate is determined by the SCLK.
. Patent No. 6,681,332.
FUNCTIONAL BLOCK DIAGRAM
GND
VDD
SCLK
SDATA02643-001
Figure 1.
PRODUCT HIGHLIGHTS 1. Specified for supply voltages of 1.6 V to 3.6 V.
2. 12-, 10-, and 8-bit ADCs in SOT-23 packages.
3. High throughput rate with low power consumption.
Power consumption in normal mode of operation at
100 kSPS and 3 V is 0.9 mW maximum.
4. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through
increases in the serial clock speed. Automatic power-down
after conversion allows the average power consumption to
be reduced when in power-down. Current consumption is
0.1 µA maximum and 8 nA typically when in power-down.
5. Reference derived from the power supply.
6. No pipeline delay.
The part features a standard successive approximation
ADC with accurate control of conversions via a CS input.
TABLE OF CONTENTS AD7466 Specifications.....................................................................3
AD7467 Specifications.....................................................................5
AD7468 Specifications.....................................................................7
Timing Specifications.......................................................................9
Timing Examples........................................................................10
Absolute Maximum Ratings..........................................................11
ESD Caution................................................................................11
Pin Configurations and Function Descriptions.........................12
Terminology................................................................................13
Typical Performance Characteristics...........................................14
Dynamic Performance Curves.................................................14
DC Accuracy Curves.................................................................14
Power Requirements Curves.....................................................14
Circuit Information........................................................................17
Converter Operation..................................................................17
ADC Transfer Function.............................................................17
Typical Connection Diagram...................................................18
Analog Input...............................................................................18
Digital Inputs..............................................................................19
Normal Mode..............................................................................19
Power Consumption..................................................................20
Serial Interface................................................................................22
Microprocessor Interfacing.......................................................23
Application Hints...........................................................................25
Grounding and Layout..............................................................25
Evaluating the Performance of the AD7466 and AD7467....25
Outline Dimensions.......................................................................26
Ordering Guide..........................................................................27
REVISION HISTORY
11/04—Rev. 0 to Rev. A Updated Format..................................................................Universal
Changes to General Description....................................................1
Added Patent Number.....................................................................1
Updated Outline Dimensions.......................................................26
Changes to Ordering Guide..........................................................27
5/03—Revision 0: Initial Version
AD7466 SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted.
The temperature range for the B version is −40°C to +85°C.
Table 1.
AD7467 SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted.
The temperature range for the B version is −40°C to +85°C.
Table 2.
AD7468 SPECIFICATIONS VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted. TA = TMIN to TMAX, unless otherwise noted.
The temperature range for the B version is −40°C to +85°C.
Table 3.
TIMING SPECIFICATIONS For all devices, VDD = 1.6 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input
signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.4 V.
Table 4.
200µAIOL
200µAIOH
1.4VTO OUTPUTPINCL
50pF02643-002
Figure 2. Load Circuit for Digital Output Timing Specifications
TIMING EXAMPLES Figure 3 and Figure 4 show some of the timing parameters from
the Timing Specifications section (Table 4).
Timing Example 1 As shown in Figure 4, having fSCLK = 3.4 MHz and a throughput
of 100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 µs.
Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns +
4.41 µs = 4.46 µs, and t8 = 60 ns max, then tQUIET = 5.48 µs,
which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t2 + 2(1/fSCLK)
= 55 ns + 588 ns = 643 ns, satisfying the maximum requirement
of 640 ns for the power-up time.
Timing Example 2 The AD7466 can also operate with slower clock frequencies.
As shown in Figure 4, assuming VDD = 1.8 V, fSCLK = 2 MHz,
and a throughput of 50 kSPS gives a cycle time of tCONVERT + t8 +
tQUIET = 20 µs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 µs =
7.55 µs, and t8 = 60 ns max, this leaves tQUIET to be 12.39 µs,
which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t2 + 2(1/fSCLK) =
55 ns + 1 µs = 1.05 µs, satisfying the maximum requirement of
640 ns for the power-up time. In this example and with other
slower clock values, the part is fully powered up and the signal
already acquired before the third SCLK falling edge; however,
the track-and-hold does not go into hold mode until that point.
In this example, the part can be powered up and the signal can
be fully acquired at approximately Point B in Figure 4.
SCLK
4 LEADING ZEROSSTATE
SDATAFigure 3. AD7466 Serial Interface Timing Diagram Example
SCLK
POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.02643-004
Figure 4. AD7466 Serial Interface Timing Diagram Example
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD
GND
VIN
SDATA
SCLK02643-005
GND
VINNC
SCLK
VDD02643-006
Figure 5. SOT-23 Pin Configuration
Figure 6. MSOP Pin Configuration
Table 6. Pin Function Descriptions TERMINOLOGY
Integral Nonlinearity (INL) The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. For the AD7466/
AD7467/AD7468, the endpoints of the transfer function are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Differential Nonlinearity (DNL) The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error The deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal (that is, AGND + 1 LSB).
Gain Error The deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (that is, VREF − 1 LSB) after the
offset error has been adjusted out.
Track-and-Hold Acquisition Time The time required for the part to acquire a full-scale step
input value within ±1 LSB, or a 30 kHz ac input value within
±0.5 LSB. The AD7466/AD7467/AD7468 enter track mode on
the CS falling edge, and return to hold mode on the third SCLK
falling edge. The parts remain in hold mode until the following
CS falling edge. See Figure 4 and the Serial Interface section for
more details.
Signal-to-Noise Ratio (SNR) The measured ratio of signal to noise at the output of the ADC.
The signal is the rms value of the sine wave input. Noise is the
rms quantization error within the Nyquist bandwidth (fS/2).
The rms value of the sine wave is half of its peak-to-peak value
divided by √2, and the rms value for the quantization noise is
q/√12. The ratio dependents on the number of quantization
levels in the digitization process; the more levels, the smaller the
quantization noise.
For an ideal N-bit converter, the SNR is defined as
SNR = 6.02 N + 1.76 db
Thus, for a 12-bit converter, this is 74 dB; for a 10-bit converter,
it is 62 dB; and for an 8-bit converter, it is 50 dB.
Practically, though, various error sources in the ADCs cause the
measured SNR to be less than the theoretical value. These errors
occur due to integral and differential nonlinearities, internal ac
noise sources, and so on.
Signal-to-Noise and Distortion Ratio (SINAD) The measured ratio of signal-to-noise and distortion at the
output of the ADC. The signal is the rms value of the sine wave,
and noise is the rms sum of all nonfundamental signals up to
half the sampling frequency (fS/2), including harmonics, but
excluding dc.
Total Unadjusted Error (TUE) A comprehensive specification that includes gain error, linearity
error, and offset error.
Total Harmonic Distortion (THD) The ratio of the rms sum of harmonics to the fundamental. For
the AD7466/AD7467/AD7468, it is defined as THD
log20dB=
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR) The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Typically, the value of this specifi-
cation is determined by the largest harmonic in the spectrum,
but for ADCs where the harmonics are buried in the noise floor,
it is a noise peak.
Intermodulation Distortion (IMD) With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa − fb),
while the third-order terms include (2fa + fb), (2fa – fb),
(fa + 2fb), and (fa − 2fb).
The AD7466/AD7467/AD7468 are tested using the CCIF
standard where two input frequencies are used. In this case,
the second-order terms are usually distanced in frequency from
the original sine waves, while the third-order terms are usually
at a frequency close to the input frequencies. As a result, the
second- and third-order terms are specified separately. The
calculation of the intermodulation distortion is as per the
THD specification, where it is the ratio of the rms sum of the
individual distortion products to the rms amplitude of the sum
of the fundamentals, expressed in dBs.
TYPICAL PERFORMANCE CHARACTERISTICS
DYNAMIC PERFORMANCE CURVES Figure 7, Figure 8, and Figure 9 show typical FFT plots for the
AD7466, AD7467, and AD7468, respectively, at a 100 kSPS
sample rate and a 30 kHz input tone.
Figure 10 shows the signal-to-noise and distortion ratio perfor-
mance vs. input frequency for various supply voltages while
sampling at 100 kSPS with a SCLK frequency of 3.4 MHz for the
AD7466.
Figure 11 shows the signal-to-noise ratio (SNR) performance
vs. input frequency for various supply voltages while sampling
at 100 kSPS with a SCLK frequency of 3.4 MHz for the AD7466.
Figure 12 shows the total harmonic distortion vs. analog input
signal frequency for various supply voltages while sampling at
100 kSPS with a SCLK frequency of 3.4 MHz for the AD7466.
Figure 13 shows the total harmonic distortion vs. analog input
frequency for different source impedances with a supply voltage
of 2.7 V, a SCLK frequency of 3.4 MHz, and sampling at a rate
of 100 kSPS for the AD7466 (see the Analog Input section).
DC ACCURACY CURVES Figure 14 and Figure 15 show typical INL and DNL perfor-
mance for the AD7466.
POWER REQUIREMENTS CURVES Figure 16 shows the supply current vs. supply voltage for the
AD7466 at −40°C, +25°C, and +85°C, with SCLK frequency of
3.4 MHz and a sampling rate of 100 kSPS.
Figure 17 shows the maximum current vs. supply voltage for the
AD7466 with different SCLK frequencies.
Figure 18 shows the shutdown current vs. supply voltage.
Figure 19 shows the power consumption vs. throughput rate for
the AD7466 with a SCLK of 3.4 MHz and different supply
voltages. See the Power Consumption section for more details.
SNR (
FREQUENCY (kHz)
Figure 7. AD7466 Dynamic Performance at 100 kSPS
NR (dB)
FREQUENCY (kHz)Figure 8. AD7467 Dynamic Performance at 100 kSPS
