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AD7450AR
Differential Input, 1MSPS, 12-Bit ADC in レSO-8 and S0-8
REV.PrJ 27/02/02
PRELIMINARY TECHNICAL DATA
Differential Input, 1MSPS,
12-Bit ADC in μSO-8 and S0-8
FEATURES
Fast Throughput Rate: 1MSPS
Specified for VDD of 3 V and 5 V
Low Power at max Throughput Rate:
3 mW typ at 833kSPS with 3 V Supplies
8 mW typ at 1MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 300kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPITM/QSPITM/
MicroWireTM/ DSP Compatible
Powerdown Mode: 1μA max
8 Pin μSOIC and SOIC Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTIONThe AD7450 is a 12-bit, high speed, low power, succes-
sive-approximation (SAR) analog-to-digital converter
featuring a fully differential analog input. It operates from
a single 3 V or 5 V power supply and features throughput
rates up to 833kSPS or 1MSPS respectively.
This part contains a low-noise, wide bandwidth, differen-
tial track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage for the
AD7450 is applied externally to the VREF pin and can be
varied from 100 mV to 2.5 V depending on the power
supply and to suit the application. The value of the refer-
ence voltage determines the common mode voltage range
of the part. With this truly differential input structure and
variable reference input, the user can select a variety of
input ranges and bias points.
The conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to inter-
face with Microprocessors or DSPs. The input signals are
sampled on the falling edge of CS and the conversion is
also initiated at this point.
FUNCTIONAL BLOCK DIAGRAMThe SAR architecture of this part ensures that there are
no pipeline delays.
The AD7450 uses advanced design techniques to achieve
very low power dissipation at high throughput rates.
PRODUCT HIGHLIGHTS1.Operation with either 3 V or 5 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7450 offers 3mW typ power
consumption for 833kSPS throughput.
3.Fully Differential Analog Input.
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. This
part also features a shutdown mode to maximize power
efficiency at lower throughput rates.
5.Variable Voltage Reference Input.
6.No Pipeline Delay.
7.Accurate control of the sampling instant via a CS input
and once off conversion control.
8. ENOB > 8 bits typ with 100mV Reference.
MicroWire is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
VIN+IN-REF
GND
SCLK
SDATA
DD
PRELIMINARY TECHNICAL DATA
AD7450 - SPECIFICATIONS1( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
PRELIMINARY TECHNICAL DATA
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.See Figure 1 and the “Serial Interface” section.Common Mode Voltage.Mark/Space ratio for the SCLK input is 40/60 to 60/40.Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and time for
an output to cross 0.4 V or 2.0 V for VDD = 3 V.
AD7450 - TIMING SPECIFICATIONS 1,2
( VDD = 2.7V to 3.3V, fSCLK = 15MHz, fS = 833kHz, VREF = 1.25 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MHz, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
AD7450
NOTESTemperature ranges as follows: A, B Versions: –40°C to +85°C.See ‘Terminology’ section.Common Mode Voltage. The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
specified in Figure 8.Because the input span of VIN+ and VIN- are both VREF, and they are 180° out of phase, the differential voltage is 2 x VREF.The reference is functional from 100mV and for 5V supplies it can range up to TBDV (see ‘Reference Section’).The reference is functional from 100mV and for 3V supplies it can range up to 2.2V (see ‘Reference Section’).Sample tested @ +25°C to ensure compliance.See POWER VERSUS THROUGHPUT RATE section.TCONVERT + TQUIET (See ‘Serial Interface Section’)Measured with a midscale DC input.
Specifications subject to change without notice.
PRELIMINARY TECHNICAL DATA
AD7450
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . .-0.3 V to +7 V
VIN+ to GND . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VIN- to GND . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . -0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . .-0.3 V to VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . . .-0.3 V to VDD +0.3 V
Input Current to Any Pin Except Supplies2 . . . .±10mA
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . .-40oC to +85oC
Storage Temperature Range . . . . . . . . .-65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .+150oC
SOIC, μSOIC Package, Power Dissipation . . . .450mW
uJA Thermal Impedance . . . . . . . . . .157°C/W (SOIC)
205.9°C/W (μSOIC)
uJC Thermal Impedance . . . . . . . . . . . 56°C/W (SOIC)
43.74°C/W (μSOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . .+215oC
Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . .+220oCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TBD
AD7450AR
AD7450ARM
AD7450BR
AD7450BRM
EVAL-AD7450CB
ORDERING GUIDE
NOTESLinearity error here refers to Integral Linearity Error.This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.EVALUATION BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices
evaluation boards ending in the CB designators.S0 = SOIC; RM = μSOIC
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch up.
Figure 1.Serial Interface Timing Diagram
Figure 2.Load Circuit for Digital Output Timing Specifications
PRELIMINARY TECHNICAL DATA
PIN CONFIGURATION SOIC and μSOIC
PIN FUNCTION DESCRIPTION
PRELIMINARY TECHNICAL DATA
AD7450
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion)
at the output of the ADC. The signal is the rms amplitude
of the fundamental.Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. The theoretical
signal to (noise + distortion) ratio for an ideal N-bit con-
verter with a sine wave input is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76)dB
Thus for a 12-bit converter, this is 74dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7450, it
is defined as:
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second to
the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc.Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7450 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves while
the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third
order terms are specified separately. The calculation of the
intermodulation distortion is as per the THD specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample to sample variation in the effective
point in time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input fre-
quency at which the amplitude of the reconstructed
fundamental is reduced by 0.1dB or 3dB for a full scale
input.
Common Mode Rejection Ratio (CMRR)
The Common Mode Rejection Ratio is defined as the
ratio of the power in the ADC output at full-scale fre-
quency, f, to the power of a 200mV p-p sine wave applied
to the Common Mode Voltage of VIN+ and VIN- of fre-
quency fs:
This is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Zero Code Error
This is the deviation of the midscale code transition (111...111
to 000...000) from the ideal VIN+-VIN - (i.e., 0LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+-VIN- (i.e., +VREF - 1LSB), after
the Zero Code Error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+-VIN - (i.e., -VREF + 1LSB), after
the Zero Code Error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode on the
13th SCLK rising edge (see the “Serial Interface Sec-
tion”). The track/hold acquisition time is the minimum
time required for the track and hold amplifier to remain in
track mode for its output to reach and settle to within 0.5
LSB of the applied input signal.
Power Supply Rejection (PSR)
The power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200mV p-p sine wave applied to the ADC
VDD supply of frequency fs.
PRELIMINARY TECHNICAL DATA
PERFORMANCE CURVES
TPC 1 and TPC 2 show the typical FFT plots for the
AD7450 with VDD of 5V and 3V, 1MHz and 833kHz sam-
pling frequency respectively and an input frequency of
300kHz.
R (dB
TPC 1.AD7450 Dynamic Performance at 1MSPS
with VDD =5V
NR (
TPC 2.AD7450 Dynamic Performance at 833ksps with
VDD = 3V
TPC 3 shows the signal-to-(noise+distortion) ratio
performance versus the analog input frequency for
various supply voltages while sampling at 1MSPS
(VDD = 5V±5%) and 833kSPS (VDD = 3V±10%).
TITLE000
TPC 3. SINAD vs Analog Input Frequency
for Various Supply Voltages TBD
TPC 4 shows the power supply rejection ratio versus
supply ripple frequency for the AD7450. Here, a
200mV p-p sine wave is coupled onto the VDD supply.
A 10nF decoupling capacitor was used on the supply
and a 1μF decoupling capacitor was used on VREF.
TITLE000
TPC 4. Power Supply Rejection (see Terminology Sec-
PRELIMINARY TECHNICAL DATA
AD7450
TPC 5 and TPC 6 show typical DNL plots for the
AD7450 with VDD of 5V and 3V, 1MHz and 833kHz
sampling frequency respectively and an input frequency of
300kHz.
CODE
TPC 5 Typical Differential Nonlinearity (DNL) VDD = 5V
CODE
TPC 6 Typical Differential Nonlinearity (DNL) VDD = 3V
TPC 7 and TPC 8 show typical INL plots for the
AD7450 with VDD of 5V and 3V, 1MHz and 833kHz
sampling frequency respectively and an input frequency of
300kHz.
CODE
TPC 7 Typical Integral Nonlinearity (INL) VDD = 5V
CODE
TPC 8 Typical Integral Nonlinearity (INL) VDD = 3V
PRELIMINARY TECHNICAL DATA
TPC 9 and TPC 10 show the change in DNL versus VREF
for VDD of 5V and 3.3V respectively.
-1
VREF
TPC 9.Change in DNL vs Reference Voltage VDD = 5V
VREF
TPC 10. Change in DNL vs Reference Voltage VDD = 3.3V*
TPC 11 and TPC 12 show the change in INL versus VREF
for VDD of 5V and 3.3V respectively.
VREF
TPC 11. Change in INL vs Reference Voltage VDD = 5V
VREF
TPC 12. Change in INL vs Reference Voltage VDD = 3.3V*
*See ‘Reference Section
PRELIMINARY TECHNICAL DATA
AD7450
TPC 13 shows the change in Zero Code Error versus the
Reference Voltage for VDD = 5V and 3.3V.
VREF
2.5
TPC 13. Change in Zero Code Error vs Reference Voltage
VDD = 5V and 3.3 V*
TPC 14 shows a histogram plot for 10000 conversions of
a dc input using the AD7450 with VDD = 5V. Both ana-
log inputs were set to VREF, which is the center of the
code transition.
CODE
TPC 14. Histogram of 10000 conversions of a DC Input with
TPC 15 shows a histogram plot for 10000 conversions of
a dc input for VDD of 3V. As in TPC 14, both inputs are
set to VREF. Both plots indicate good noise performance as
the majority of codes appear in one output bin.
CODE
TPC 15. Histogram of 10000 conversions of a DC Input with
VDD = 3V
TPC 16 shows the Effective Number of Bits (ENOB)
versus the Reference Voltage for VDD 5V and 3.3V. Note
that the AD7450 has an ENOB of greater than 8-bits typi-
cally when VREF = 100mV.
VREF
ffecti
ve Nu
er o
f Bi
PRELIMINARY TECHNICAL DATA
TPC 17 shows the Common Mode Rejection Ratio versus
supply ripple frequency for the AD7450 for both VDD =
5V and 3 V. Here a 200mV p-p sine wave is coupled onto
the Common Mode Voltage of VIN+ and VIN-.100100010000
Frequency (kHz)
TPC 17. CMRR versus Frequency for VDD = 5V and 3 V
CIRCUIT INFORMATION
The AD7450 is a fast, low power, single supply, 12-bit
successive approximation analog-to-digital converter
(ADC). It can operate with a 5 V and 3V power supply
and is capable of throughput rates up to 1MSPS and
833kSPS when supplied with a 18MHz or 15MHz clock
respectively. This part requires an external reference to be
applied to the VREF pin, with the value of the reference
chosen depending on the power supply and to suit the
application.
When operated with a 5 V supply, the maximum reference
that can be applied to the part is 2.5 V and when operated
with a 3 V supply, the maximum reference that can be
applied to the part is 2.2 V. (See ‘Reference Section’).
The AD7450 has an on-chip differential track and hold
amplifier, a successive approximation (SAR) ADC and a
serial interface, housed in either an 8-lead SOIC or
μSOIC package. The serial clock input accesses data
from the part and also provides the clock source for the
successive-approximation ADC. The AD7450 features a
power-down option for reduced power consumption be-
tween conversions. The power-down feature is
implemented across the standard serial interface as de-
scribed in the ‘Modes of Operation’ section.
CONVERTER OPERATION
The AD7450 is a successive approximation ADC based
figure 3 (acquisition phase), SW3 is closed and SW1 and
SW2 are in position A, the comparator is held in a bal-
anced condition and the sampling capacitor arrays acquire
the differential signal on the input.
Figure 3. ADC Acquisition Phase
When the ADC starts a conversion (figure 4), SW3 will
open and SW1 and SW2 will move to position B, causing
the comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The Control
Logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling
capacitor arrays to bring the comparator back into a bal-
anced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the
ADC’s output code. The output impedances of the
sources driving the VIN+ and the VIN- pins must be
matched otherwise the two inputs will have different set-
tling times, resulting in errors.
Figure 4. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7450 is two’s complement.
The designed code transitions occur at successive LSB
PRELIMINARY TECHNICAL DATA
AD7450
Figure 5. AD7450 Ideal Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
Figure 6 shows a typical connection diagram for the
AD7450 for both 5 V and 3 V supplies. In this setup the
GND pin is connected to the analog ground plane of the
system. The VREF pin is connected to either a 2.5 V or a
1.25 V decoupled reference source depending on the
power supply, to set up the analog input range. The com-
mon mode voltage has to be set up externally and is the
value that the two inputs are centered on. For more details
on driving the differential inputs and setting up the com-
mon mode, see the ‘Driving Differential Inputs’ section.
The conversion result for the ADC is output in a 16-bit
word consisting of four leading zeros followed by the
MSB of the 12-bit result. For applications where power
consumption is of concern, the power-down mode should
be used between conversions or bursts of several conver-
sions to improve power performance. See ‘Modes of
Operation’ section.
THE ANALOG INPUT
The analog input of the AD7450 is fully differential. Dif-
ferential signals have a number of benefits over single
ended signals including noise immunity based on the
device’s common mode rejection, improvements in distor-
tion performance, doubling of the device’s available
dynamic range and flexibility in input ranges and bias
points.
Figure 7 defines the fully differential analog input of the
AD7450.
Figure 7. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN- pins (i.e.
VIN+ - VIN-). VIN+ and VIN- are simultaneously driven by
two signals each of amplitude VREF that are 180° out of
phase. The amplitude of the differential signal is therefore
-VREF to +VREF peak-to-peak (i.e. 2 x VREF). This is re-
gardless of the common mode (CM). The common mode
is the average of the two signals, i.e. (VIN+ + VIN-)/2 and
is therefore the voltage that the two inputs are centered on.
This results in the span of each input being CM ± VREF/2.
This voltage has to be set up externally and its range var-
ies with VREF. As the value of VREF increases, the
common mode range decreases. When driving the inputs
with an amplfier, the actual common mode range will be
determined by the amplifier’s output voltage swing.
Figure 8 shows how the common mode range varies with
VREF for a 5 V power supply and figure 9 shows an ex-
ample of the common mode range when using the
AD8138 differential amplifer to drive the analog inputs.
The common mode must be in this range to guarantee the
specifications. With a 3V power supply, the Common
Mode range is TBD.
For ease of use, the common mode can be set up to be
equal to VREF, resulting in the differential signal being
±VREF centered on VREF. When a conversion takes place,
the common mode is rejected resulting in a virtually noise
free signal of amplitude -VREF to +VREF corresponding to
he digital codes of 0 to 4095.
