AD74111YRU ,2.5 V, 24-Bit Sigma-Delta Mono CODECSPECIFICATIONS f = 48 kHz, T = T to T , unless otherwise noted.)S A MIN MAXParameter Conditions Min ..
AD74111YRU-REEL ,2.5 V, 24-Bit Sigma-Delta Mono CODECAPPLICATIONSto +105°C.Digital Video Camcorders (DVC)®Portable Audio Devices (Walkman , PDAs, and so ..
AD7414ARM-0 , ±0.5C Accurate, 10-Bit Digital Temperature Sensors in SOT-23
AD7414ARM-1 , ±0.5C Accurate, 10-Bit Digital Temperature Sensors in SOT-23
AD7414ART-0500RL7 , ±0.5C Accurate, 10-Bit Digital Temperature Sensors in SOT-23
AD7414ART-0REEL , ±0.5C Accurate, 10-Bit Digital Temperature Sensors in SOT-23
ADF4113BCP ,RF PLL Frequency SynthesizersCHARACTERISTICS (5 V)RF Input Frequency Use a square wave for lower frequencies.ADF4110 25/550 25/5 ..
ADF4113BRU ,RF PLL Frequency SynthesizersSPECIFICATIONS(AV = DV = 3 V 10%, 5 V 10%; AV ≤ V ≤ 6.0 V; AGND = DGND = CPGND = 0 V; R = 4.7 k ..
ADF4113BRUZ-REEL7 , RF PLL Frequency Synthesizers
ADF4116BRU ,RF PLL Frequency SynthesizersSPECIFICATIONS(AV = DV = 3 V 10%, 5 V 10%; AV ≤ V ≤ 6.0 V; AGND = DGND = CPGND = 0 V; T = T to ..
ADF4117BRU ,RF PLL Frequency SynthesizersCHARACTERISTICSRF Input Frequency See Figure 22 for Input CircuitADF4116 45/550 45/550 MHz min/maxA ..
ADF4118BRU ,RF PLL Frequency SynthesizersFEATURESThe ADF4116 family of frequency synthesizers can be usedADF4116: 550 MHzto implement local ..
AD74111YRU-AD74111YRU-REEL
2.5 V, 24-Bit Sigma-Delta Mono CODEC
REV.0
Low Cost, Low Power
Mono Audio Codec
FEATURES
2.5 V Mono Audio Codec with 3.3 V Tolerant
Digital Interface
Supports 8 kHz to 48 kHz Sample Rates
Supports 16-/20-/24-Bit Word Lengths
Multibit �-� Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DAC – Least Sensitive to Jitter
Performance (20 Hz to 20 kHz)
85 dB ADC Dynamic Range
93 dB DAC Dynamic Range
Programmable ADC Gain
On-Chip Volume Control for DAC Channel
Software Controllable Clickless Mute
Supports 256�
fS, 512�
fS, and 768�
fS Master Mode
Clocks
Master Clock Prescaler for Use with DSP Master Clocks
On-Chip Reference
16-Lead TSSOP Package
APPLICATIONS
Digital Video Camcorders (DVC)
Portable Audio Devices (Walkman®, PDAs, and so on)
Audio Processing
Voice Processing
Telematic Systems
General-Purpose Analog I/O
FUNCTIONAL BLOCK DIAGRAM
VIN
CAPP
CAPN
DVDD2AVDDDVDD1VOUT
AGNDREFCAP
DIN
DOUT
DFS
DCLK
DGND
MCLKRESET
GENERAL DESCRIPTIONThe AD74111 is a front-end processor for general-purpose audio
and voice applications. It features a multibit �-� A/D conversion
channel and a multibit �-� D/A conversion channel. The ADC
channel provides >67 dB THD+N and the DAC channel pro-
vides >88 dB THD+N, both over an audio signal bandwidth.
The AD74111 is particularly suitable for a variety of applications
where mono input and output channels are required, including
audio sections of digital video camcorders, portable personal
audio devices, and telematic applications. Its high quality
performance also makes it suitable for speech and telephony
applications such as speech recognition and synthesis, and modern
feature phones.
An on-chip reference voltage is included but can be powered
down and bypassed by an external reference source if required.
The AD74111 offers sampling rates that, depending on MCLK
selection and MCLK divider ratio, range from 8 kHz in the
voiceband range to 48 kHz in the audio range.
The AD74111 is available in a 16-lead TSSOP package option
and is specified for the automotive temperature range of –40°C
to +105°C.
AD74111–SPECIFICATIONS
(AVDD = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 2.5 V ± 5%, fMCLK = 12.288 MHz,
fS = 48 kHz, TA = TMIN to TMAX, unless otherwise noted.)Total Harmonic Distortion + Noise
Programmable Input Gain
Gain Step Size
Offset Error
Full-Scale Input Voltage
Input Resistance
Input Capacitance
Common-Mode Input Volts
Crosstalk
AD74111
Table I.Current Summary (AVDD = 2.5 V, DVDD1 = 2.5 V, DVDD2 = 2.5 V)1, 2, 3NOTESAll values are typical, unless otherwise noted.Max values are quoted with DVDD1 = 3.6 V.Sample rates quoted are for 16 kHz and (48 kHz).
LOGIC OUTPUT
*Guaranteed by design.
Specifications subject to change without notice.
AD74111
TIMING CHARACTERISTICS
(AVDD = 2.5 V ± 5%, DVDD2 = 2.5 V ± 5%, DVDD1 = 3.3 V ± 10%, fMCLK = 12.288 MHz, fS = 48 kHz,
TA = TMIN to TMAX, unless otherwise noted.)NOTESDetermines Master/Slave mode operation.Applies in Slave mode only.Applies in Master mode only.Applies in Multiframe-Sync mode only.
Figure 1.MCLK and RESET Timing
Figure 2.Serial Port Timing
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD74111 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C, unless otherwise noted.)
AVDD, DVDD2 to AGND, DGND . . . . . . .–0.3 V to +3.0 V
DVDD1 to AGND, DGND . . . . . . . . . . . . .–0.3 V to +4.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . .–0.3 V to DVDD1 + 0.3 V
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
16-Lead TSSOP, θJA Thermal Impedance . . . . . . . .150.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
TEMPERATURE RANGE
ORDERING GUIDE
AD74111
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TPC 1.ADC Composite Filter Response
TPC 2.ADC Composite Filter Response
Low Group Delay Enabled
TPC 3.ADC Composite Filter Response
(Pass-Band Section)
TPC 4.DAC Composite Filter Response
TPC 5.DAC Composite Filter Response
Low Group Delay Enabled
TPC 6.DAC Composite Filter Response
(Pass-Band Section)
AD74111
FUNCTIONAL DESCRIPTION
General DescriptionThe AD74111 is a 2.5 V mono codec. It comprises an ADC and
DAC channel with single-ended input and output. The ADC
has a programmable gain stage and the DAC has programmable
volume control. Each of these sections is described in further
detail below. The AD74111 is controlled by means of a flexible
serial port (SPORT) that can be programmed to accommodate
many industry standard DSPs and microcontrollers. The AD74111
can be set to operate as a master or slave device. The AD74111
can be set to operate with sample rates of 8kHz to 48kHz,
depending on the values of MCLK and the MCLK prescalers.
On-chip digital filtering is provided as part of the DAC and
ADC channels with a low group delay option to reduce the delays
through the filters when operating at lower sample rates. Figure4
shows a block diagram of the DAC and ADC channel in the
AD74111. Figures 5a and 5b show block diagrams of the filter
arrangements of the ADC and DAC filters.
ADC SectionThe AD74111 contains a multibit sigma-delta ADC. The ADC
has a single input pin with additional pins for decoupling/filter
capacitors. The ADC channel has an independent input amplifier
gain stage that can be programmed in steps of 3 dB, from 0dB
to 12dB. The input amplifier gain settings are set by program-
ming the appropriate bits in Control Register E. The ADC can
also be muted under software control. The AD74111 input
channel employs a multibit sigma-delta conversion technique that
provides a high resolution output with system filtering imple-
mented on-chip. Sigma-delta converters employ a technique
known as oversampling, where the sampling rate is many times
the highest frequency of interest. In the case of the AD74111,
the oversampling ratio is 64 and a decimation filter is used to
reduce the output to standard sample rates. The maximum sample
rate is 48kHz.
TPC 7.ADC THD+N vs. Sample Rate
TPC 8.DAC THD+N vs. Sample Rate
Figure 5a.ADC Filter Section
Figure 5b.DAC Filter Section
ADC, CAPP, and CAPN PinsThe ADC channel requires two external capacitors to act as
charge reservoirs for the switched capacitor inputs of the sigma-
delta modulator. These capacitors isolate the outputs of the PGA
stage from glitches generated by the sigma-delta modulator. The
capacitor also forms a low-pass filter with the output impedance
of the PGA (approximately 124 Ω), which helps to isolate noise
from the modulator engine. The capacitors should be of good
quality, such as NPO or polypropylene film, with values from
100pF to 1 nF and should be connected to AGND.
Peak ReadbackThe AD74111 can store the highest ADC value to facilitate level
adjustment of the input signal. Programming the Peak Enable
bit in Control Register E with a 1 will enable ADC Peak Level
Reading. The peak value is stored as a 6-bit number from 0dB
to –63 dB in 1dB steps. Reading Control Register F will give the
highest ADC value since the bit was set. The ADC peak register
is automatically cleared after reading.
Decimator SectionThe digital decimation filter has a pass-band ripple of 0.2mdB
and a stop-band attenuation of 120 dB. The filter is an FIR type
with a linear phase response. The group delay at 48 kHz is
910µs. Output sample rates up to 48kHz are supported.
Input Signal SwingThe ADC input has an input range of 0.5 V rms/1.414 V p-p
about a bias point equal to VREFCAP. Figure 6 shows a typical
input filter circuit for use with the AD74111.
Figure 6.Typical Input Circuit
DAC SectionThe AD74111 DAC channel has a single-ended, analog output.
The DAC has independent software controllable Mute and Volume
Control functions. Control Register G controls the attenuation
factor for the DAC. This register is 10 bits wide, giving 1024
steps of attenuation. The AD74111 output channel employs a
Output Signal SwingThe DAC has an output range of 0.5 V rms/1.414 V p-p about
a bias point equal to VREFCAP (see Figure 7).
Figure 7.Typical Output Circuit
Low Group DelayIt is possible to bypass much of the digital filtering by enabling
the Low Group Delay function in Control Register C. By reduc-
ing the amount of filtering the AD74111 applies to input and
output samples, the time delay between the sampling interval
and when the sample is available is greatly reduced. This can be
of benefit in applications such as telematics, where minimal
time delays are important. When the Low Group Delay function
is enabled, the sample rate becomes IMCLK/128.
ReferenceThe AD74111 features an on-chip reference whose nominal
value is 1.125 V. A 100 nF ceramic and 10 µF tantalum capacitor
applied at the REFCAP pin are necessary to stabilize the reference.
(See Figure 8.)
Figure 8.Reference Decoupling
If required, an external reference can be used as the reference
source of the ADC and DAC sections. This may be desirable in
situations where multiple devices are required to use the same
value of reference or because of a better temperature coefficient
specification. The internal reference can be disabled via Control
Register A and the external reference applied at the REFCAP
pin (see Figure 9). External references should be of a suitable
value such that the voltage swing of the inputs or outputs is not
AD74111Figure 9.External Reference
Master Clocking SchemeThe update rate of the AD74111’s ADC and DAC channels
requires an internal master clock (IMCLK) that is 256 times the
sample update rate (IMCLK = 256 � fS). To provide some flex-
ibility in selecting sample rates, the device has a series of three
master clock prescalers that are programmable and allow the
user to choose a range of convenient sample rates from a single
external master clock. The master clock signal to the AD74111 is
applied at the MCLK pin. The MCLK signal is passed through
a series of three programmable MCLK prescaler (divider) circuits
that can be selected to reduce the resulting Internal MCLK
(IMCLK) frequency if required. The first and second MCLK
prescalers provide divider ratios of �1 (pass through), �2, �3;
while the third prescaler provides divider ratios of �1 (pass
through), �2, �4.
Figure 10.MCLK Divider
The divider ratios allow a more convenient sample rate selection
from a common MCLK, which may be required in many voice
related applications. Control Register B should be programmed
to achieve the desired divider ratios.
Selecting Sample RatesThe sample rate at which the converter runs is always 256 times
the IMCLK rate. IMCLK is the Internal Master Clock and is the
output from the Master Clock Prescaler. The default sample rate
is 48 kHz (based on an external MCLK of 12.288 MHz). In this
mode, the ADC modulator is clocked at 3.072 MHz and the DAC
modulator is clocked at 6.144 MHz. Sample rates that are lower
than MCLK/256 can be achieved by using the MCLK prescaler.
Example 1: fSAMP = 48 kHz and 8 kHz RequiredMCLK = 48 kHz � 256 = 12.288 MHz to provide 48 kHz fSAMP.
For fSAMP = 8 kHz, it is necessary to use the �3 setting in
Prescaler1, the �2 setting in Prescaler 2, and pass throughPrescaler 3. This results in an IMCLK = 8 kHz � 256 =
2.048MHz (= 12.288 MHz/6).
Example 2: fSAMP = 44.1 kHz and 11.025 kHz RequiredMCLK = 44.1 kHz � 256 = 11.2896 MHz to provide 44.1 kHz fSAMP.
For fSAMP = 11.025 kHz, it is necessary to use the �1 setting in
Prescaler 1 and the �4 setting in Prescaler 2, and pass through
in Prescaler 3. This results in an IMCLK = 11.025 kHz � 256
= 2.8224 MHz (= 11.2896 MHz/4).
Resetting the AD74111The AD74111 can be reset by bringing the RESET pin low.
Following a reset, the internal circuitry of the AD74111 ensures
that the internal registers are reset to their default settings and
the on-chip RAM is purged of previous data samples. The DIN
pin is sampled to determine if the AD74111 is required to
operate in Master or Slave mode. The reset process takes 3072
MCLK periods, and the user should not attempt to program the
AD74111 during this time.
Power Supplies and GroundsThe AD74111 features three separate supplies: AVDD, DVDD1,
and DVDD2.
AVDD is the supply to the analog section of the device and must
be of sufficient quality to preserve the AD74111’s performance
characteristics. It is nominally a 2.5 V supply.
DVDD1 is the supply for the digital interface section of the device.
It is fed from the digital supply voltage of the DSP or controller
to which the device is interfaced and allows the AD74111
to interface with devices operating at supplies of between
2.5V – 5% to 3.3 V + 10%.
DVDD2 is the supply for the digital core of the AD74111. It is
nominally a 2.5 V supply.
Accessing the Internal RegistersThe AD74111 has seven registers that can be programmed to
control the functions of the AD74111. Each register is 10 bits
wide and is written to or read from using a 16-bit write or read
operation, with the exception of Control Register F, which is
read-only. Table V shows the format of the data transfer operation.
The Control Word is made up of a Read/Write bit, the register
address, and the data to be written to the device. Note that in a
read operation the data field is ignored by the device. Access to
the control registers is via the serial port through one of the
operating modes described below.
Serial PortThe AD74111 contains a flexible serial interface port that is
used to program and read the control registers and to send and
receive DAC and ADC audio data. The serial port is compatible
with many popular DSPs and can be programmed to operate in
a variety of modes, depending on which one best suits the DSP
being used. The serial port can be set to operate as a Master or
Slave device, as discussed below. Figure 11 shows a timing
diagram of the serial port.
