AD7398BR ,Quad, Serial-Input 12-Bit/10-Bit DACsSpecifications subject to change without notice.–2– REV. 0AD7398/AD7399(@ V = 5 V, V = 0 V; or V = ..
AD7398BR ,Quad, Serial-Input 12-Bit/10-Bit DACsCHARACTERISTICSShutdown Supply Current I No Load 30/60 30/60 µ A typ/maxDD_SDPositive Supply Curren ..
AD7398BRU-REEL7 ,Quad, Serial-Input 12-Bit/10-Bit DACsSPECIFICATIONS(@ V = 5 V, V = 0 V; or V = +5 V, V = –5 V, V = +2.5 V, –40C < TDD SS DD SS REF AAD7 ..
AD7399 ,Quad, Serial-Input 10-Bit DACSpecifications subject to change without notice.–2– REV. 0AD7398/AD7399(@ V = 5 V, V = 0 V; or V = ..
AD7400 ,Isolated Sigma-Delta ModulatorGENERAL DESCRIPTION Onboard Digital Isolator Onboard Reference The AD7400/AD7401 are 2nd order sig ..
AD7400AYNSZ , Isolated Sigma-Delta Modulator
ADF4106BRUZ-R7 , PLL Frequency Synthesizer
ADF4106BRUZ-RL , PLL Frequency Synthesizer
ADF4107BCP ,PLL Frequency SynthesizerGENERAL DESCRIPTION 7.0 GHz bandwidth The ADF4107 frequency synthesizer can be used to implement 2. ..
ADF4107BRUZ , PLL Frequency Synthesizer
ADF4110BCP ,RF PLL Frequency SynthesizersCHARACTERISTICS7ADF4113 Phase Noise Floor –171 –171 dBc/Hz typ @ 25 kHz PFD Frequency–164 –164 dBc/ ..
ADF4110BRU ,RF PLL Frequency SynthesizersCHARACTERISTICSREFIN Input Frequency 0/100 0/100 MHz min/max4Reference Input Sensitivity –5/0 –5/0 ..
AD7398BR-AD7398BRU-REEL7
Quad, Serial-Input 12-Bit/10-Bit DACs
REV.0
Quad, Serial-Input
12-Bit/10-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
CLK
GND
VDD
SDI
VOUTA
VOUTB
VOUTC
VOUTD
VREFAVREFB
VREFCVREFDLDACRSVSS
FEATURES
AD7398—12-Bit Resolution
AD7399—10-Bit Resolution
Programmable Power Shutdown
Single (3 V to 5 V) or Dual (�5 V) Supply Operation
3-Wire Serial SPI-Compatible Interface
Internal Power ON Reset
Double Buffered Registers for Simultaneous
Multichannel DAC Update
Four Separate Rail-to-Rail Reference Inputs
Thin Profile TSSOP-16 Package Available
Low Tempco 1.5 ppm/�C
APPLICATIONS
Automotive Output Voltage Span
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTIONThe AD7398/AD7399 family of quad, 12-bit/10-bit, voltage-
output digital-to-analog converters is designed to operate from a
single 3 V to 5 V or a dual ±5 V supply. Built with Analog’s robust
CBCMOS process, this monolithic DAC offers the user low
cost, and ease-of-use in single or dual-supply systems.
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS < VREF < VDD that
result in a wide selection of full-scale outputs. For multiplying
applications ac inputs can be as large as ±5 VP.
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller-compatible inputs using serial-
data-in (SDI), clock (CLK), and a chip-select (CS). A common
level-sensitive load-DAC strobe (LDAC) input allows simulta-
neous update of all DAC outputs from previously loaded Input
Registers. Additionally, an internal power ON reset forces the
output voltage to zero at system turn ON. An external asynchro-
nous reset (RS) also forces all registers to the zero code state. A
programmable power-shutdown feature reduces power dissipa-
tion on unused DACs.
Both parts are offered in the same pinout to enable users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications see the
pin compatible AD7304 product.
The AD7398/AD7399 is specified over the extended industrial
(–40°C to +125°C) temperature range. Parts are available in
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP-
16 packages.
Figure 1.AD7398 DNL vs. Code (TA = 25°C)
AD7398/AD7399–SPECIFICATIONS
AD7398 12-BIT VOLTAGE OUTPUT DAC
STATIC PERFORMANCELOGIC INPUTS
NOTESOne LSB = VREF/4096 V for the 12-bit AD7398.The first eight codes (000H, 007H) are excluded from the linearity error measurement in single supply operation.These parameters are guaranteed by design and not subject to production testing.When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Operation section of the data sheet.
(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40�C < TA
< +125�C, unless otherwise noted.)
AD7398/AD7399
AD7399 10-BIT VOLTAGE OUTPUT DAC
STATIC PERFORMANCELOGIC INPUTS
NOTESOne LSB = VREF/1024 V for the 10-bit AD7399.The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.These parameters are guaranteed by design and not subject to production testing.When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Operation section of the data sheet.
(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40�C < TA
< +125�C, unless otherwise noted.)
AD7398/AD7399
ABSOLUTE MAXIMUM RATINGS*VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Thermal Resistance θJA
16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . 158°C/W
16-Lead Thin Shrink Surface Mount (RU-16) . . . 180°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . (TJ Max–TA)/θJA
ORDERING GUIDEThe AD7398 contains 3254 transistors. The die size measures 108 mil × 144 millimeters.
Figure 2.AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
Figure 3.Continuous Clock Timing Diagram
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
R-16 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RU-16 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . 224°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7398/AD7399 features proprietary ESD protection circuitry, permanent damage may occur
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
AD7398/AD7399
Table I.Control Logic Truth TableNOTES↑+ Positive logic transition; ↓– Negative logic transition; X Don’t Care; SR shift register.At power ON, both the Input Register and the DAC Register are loaded with all zeros..During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken
out of Shutdown mode.LDAC input is a level-sensitive input that controls the four DAC registers.
Table II.AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First FormatNOTE
Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table III.AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First FormatNOTE
Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table IV.AD7398/AD7399 Address Decode Control
TERMINOLOGY
Relative Accuracy, INLFor the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
Differential Nonlinearity, DNLDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maxi-
mum ensures monotonicity. TPC 3 illustrates a typical DNL
versus code plot.
Zero-Scale Error, VZSEZero-scale error is a measure of the output voltage error from
zero voltage when zero code is loaded to the DAC register.
Full-Scale Error, VFSEFull-scale error is a measure of the output voltage error from full-
scale voltage when full-scale code is loaded to the DAC register.
Full-Scale Temperature Coefficient, TCVFSThis is a measure of the change in full-scale error with a change
in temperature. It is expressed in ppm/°C or mV/°C.
DAC Glitch Impulse, QDigital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (midscale transition). A plot of the
glitch impulse is shown in TPC 10.
Digital Feedthrough, QDFDigital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. CS is held
high, while the CLK and SDI signals are toggled. It is speci-
fied in nV-s and is measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa. A typi-
cal plot of digital feedthrough is shown in TPC 11.
Power Supply Sensitivity, PSSThis specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
sensitivity is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
by ±10%.
Reference Feedthrough, VOUT/VREFThis is a measure of the feedthrough from the VREF input to
the DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in dB or mV p-p.
AD7398/AD7399
–Typical Performance Characteristics
CODE – Decimal
INL
LSB
1024153620482560307235844096TPC 1.AD7398 INL vs. Code (TA = 25°C)
CODE – Decimal
INL
LSB
CODE – Decimal
INL
LSB
CODE – Decimal
INL
LSB
CODE – Decimal
INL
LSB
2563845126407688961024TPC 2.AD7399 INL vs. Code (TA = 25°C)
CODE – Decimal
DNL
LSB
1024153620482560307235844096TPC 3.AD7398 DNL vs. Code (TA = 25°C)
CODE – Decimal
DNL
LSB
CODE – Decimal
DNL
LSB
CODE – Decimal
DNL
LSB
CODE – Decimal
DNL
LSB
2563845126407688961024TPC 4.AD7399 DNL vs. Code (TA = 25°C)
