AD7392 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7392 ,+3/+5 V, Parallel-Input Micropower 12-Bit DACCHARACTERISTICS (@ V = 2.5 V, 2408C < T < 1858C, unless otherwise noted)REF IN AParameter Symbol Co ..
AD7392AR ,+3 V, Parallel Input Micropower 10- and 12-Bit DACsCHARACTERISTICSREF INAParameter Symbol Conditions 3 V 6 10% 5 V 6 10% UnitsSTATIC PERFORMANCE1Resol ..
AD7393AR ,+3 V, Parallel Input Micropower 10- and 12-Bit DACsCHARACTERISTICSPower Supply Range V DNL < 61 LSB 2.7/5.5 2.7/5.5 V min/maxDD RANGEV = 0 V, No Load, ..
AD7393ARU ,+3 V, Parallel Input Micropower 10- and 12-Bit DACsapplications in a thin 1.1 mm heightsupply V or any value in between. The voltage outputs areDDTSSO ..
AD7394 ,+3/+5V Dual, Serial-Input 12-Bit DACapplications the AD7395AR is specified for operation over thepositive supply V or any value in betw ..
AD7394AR ,+3 V, Dual, Serial Input 12-/10-Bit DACsapplications the AD7395AR is specified for operation over thepositive supply V or any value in betw ..
ADF4002BRUZ , Phase Detector/Frequency Synthesizer
ADF4002BRUZ-RL7 , Phase Detector/Frequency Synthesizer
ADF4002BRUZ-RL7 , Phase Detector/Frequency Synthesizer
ADF4007BCP ,High Frequency Divider/PLL Frequency SynthesizerCHARACTERISTICS 2REFIN Input Sensitivity 0.8/VDD V p-p min/max Biased at AVDD/2REF Input Freque ..
ADF4106 ,PLL Frequency SynthesizerCHARACTERISTICSREFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, Use DC-CoupledSquare ..
ADF4106BCP ,PLL Frequency Synthesizerspecifications are given as typical values. 3Use a square wave for lower frequencies, below the mi ..

AD7392
+3/+5 V, Parallel-Input Micropower 12-Bit DAC
REV.A
+3 V, Parallel Input
Micropower 10- and 12-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Micropower: 100 mA
0.1 mA Typical Power Shutdown
Single-Supply +2.7 V to +5.5 V Operation
Compact 1.1 mm Height TSSOP-20 Package
AD7392/12-Bit Resolution
AD7393/10-Bit Resolution
0.9 LSB Differential Nonlinearity Error
APPLICATIONS
Automotive 0.5 V to 4.5 V Output Span Voltage
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7392/AD7393 family of 10- and 12-bit voltage-output
digital-to-analog converters is designed to operate from a single
+3 V supply. Built using a CBCMOS process, these monolithic
DACs offer the user low cost and ease of use in single-supplyV systems. Operation is guaranteed over the supply voltage
range of +2.7 V to +5.5 V, making this device ideal for battery
operated applications.
The full-scale voltage output is determined by the external
reference input voltage applied. The rail-to-rail REFIN to
DACOUT allows for a full-scale voltage set equal to the positive
supply VDD or any value in between. The voltage outputs are
capable of sourcing 5 mA.
A 12-bit wide data latch loads with a 45 ns write time allowing
interface to the fastest processors without wait states.
Additionally, an asynchronous RS input sets the output to zero
scale at power on or upon user demand.
Both parts are offered in the same pinout to allow users to select
the amount of resolution appropriate for their applications
without circuit card changes.
The AD7392/AD7393 are specified for operation over the ex-
tended industrial (–40°C to +85°C) temperature range. The
AD7393AR is specified for the –40°C to +125°C automotive
temperature range. AD7392/AD7393s are available in plastic
DIP, and 20-lead SOIC packages. The AD7393ARU is avail-
able for ultracompact applications in a thin 1.1 mm height
TSSOP-20 package.
For serial data input, 8-lead packaged versions, see the AD7390
and AD7391 products.
CODE – Decimal
0.4
DNL – LSB
102415362048256030723584
Figure 1.AD7392 Differential Nonlinearity Error vs. Code
Figure 2.AD7393 Differential Nonlinearity Error vs. Code
AD7392/AD7393–SPECIFICATIONS
AD7392 ELECTRICAL CHARACTERISTICS
STATIC PERFORMANCE
LOGIC INPUTS
SUPPLY CHARACTERISTICS
NOTESOne LSB = VREF/4096 V for the 12-bit AD7392.The first two codes (000H, 001H) are excluded from the linearity error measurement.These parameters are guaranteed by design and not subject to production testing.Typicals represent average readings measured at +25°C.All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
(@ VREF IN = 2.5 V, 2408C < TA < 1858C, unless otherwise noted)
AD7392/AD7393
AD7393 ELECTRICAL CHARACTERISTICS
STATIC PERFORMANCE
REFERENCE INPUT
ANALOG OUTPUT
INTERFACE TIMING
AC CHARACTERISTICS
NOTESOne LSB = VREF/1024 V for the 10-bit AD7393.The first two codes (000H, 001H) are excluded from the linearity error measurement.These parameters are guaranteed by design and not subject to production testing.Typicals represent average readings measured at +25°C.All input control signals are specified with tR = tF = 2 ns (10% to 90% of 13 V) and timed from a voltage level of 1.6 V.The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
(@ VREF IN = 2.5 V, 2408C < TA < 1858C, unless otherwise noted)
AD7392/AD7393
PIN CONFIGURATIONS
VREF
VOUT
AGND
DGND
D11
D10
VDD
SHDN
VREF
VOUT
AGND
DGND
VDD
SHDN
NC = NO CONNECT
PIN DESCRIPTION
ORDERING GUIDE
NOTES
XIND = –40°C to +85°C; AUTO = –40°C to +125°C.
The AD7392 contains 709 transistors. The die size measures 78 mil · 85 mil =
6630 sq. mil.
ABSOLUTE MAXIMUM RATINGS*
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . .–0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . .50 mA
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +2 V
Package Power Dissipation . . . . . . . . . . . . .(TJ max – TA)/qJA
Thermal Resistance qJA
20-Lead Plastic DIP Package (N-20) . . . . . . . . . . .57°C/W
20-Lead SOIC Package (R-20) . . . . . . . . . . . . . . . .60°C/W
20-Lead Thin-Shrink Surface Mount (RU-20) . . .155°C/W
Maximum Junction Temperature (TJ max) . . . . . . . . . .150°C
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
AD7393AR . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature
N-20 (Soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . .+300°C
R-20 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . . . . . .+215°C
RU-20 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
DB11–DB0
VOUT
Figure 3.Timing Diagram
DBX
INTERNAL
DAC
SWITCHES
Figure 4.Digital Control Logic
CODE – Decimal
INL – LSB
Figure 5.AD7392 Integral Nonlinear-
ity Error vs. Code
TOTAL UNADJUSTED ERROR – LSB
FREQUENCY
–3.33.310162330364350
Figure 8.AD7393 Total Unadjusted
Error Histogram
VIN – Volts
SUPPLY CURRENT –
100
Figure 11.Supply Current vs. Logic
Input Voltage
CODE – Decimal
INL – LSB
Figure 6.AD7393 Integral Nonlinear-
ity Error vs. Code
Figure 9.AD7393 Full-Scale Output
Tempco Histogram
SUPPLY VOLTAGE – V73456
THRESHOLD VOLTAGE – V
3.5
Figure 12.Logic Threshold vs.
Supply Voltage
Figure 7.AD7392 Total Unadjusted
Error Histogram
Figure 10.Voltage Noise Density vs.
Frequency
Figure 13.Supply Current vs.
Temperature
AD7392/AD7393
CLOCK FREQUENCY – Hz
SUPPLY CURRENT –
80010k10M100k1M
200
Figure 14.Supply Current vs. Clock
Frequency
TIME – 2ms/DIV
Figure 17.Midscale Transition
Performance
FREQUENCY – Hz
GAIN – dB
23010100100k1k10k
Figure 20.Reference Multiplying
Bandwidth
FREQUENCY – Hz
PSRR – dB1010010k1k
Figure 15.Power Supply Rejection
vs. Frequency
TIME – 5ms/DIV
Figure 18.Digital Feedthrough
REFERENCE VOLTAGE – V1324
INTEGRAL NONLINEARITY – LSB
1.4
Figure 21.INL Error vs. Reference
Voltage
Figure 16.IOUT at Zero Scale vs. VOUT
Figure 19.Large Signal Settling Time
Figure 22.Long-Term Drift
Accelerated by Burn-in

Partno	Mfg	Dc	Qty	Available	Descript
AD7392	AD	N/a	13368	avai	+3/+5 V, Parallel-Input Micropower 12-Bit DAC