AD7376AR10-AD7376AR50-AD7376ARU1M-AD7376ARU50 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7376AR50 ,+-15 V Operation Digital PotentiometerCHARACTERISTICS (Applies to All Parts [Notes 5, 11])Input Clock Pulsewidth t , t Clock Level High o ..
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AD7376AR10-AD7376AR50-AD7376ARU1M-AD7376ARU50
+-15 V Operation Digital Potentiometer
REV.0
*Patent Number: 5495245
615 V Operation
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
128 Position
Potentiometer Replacement
10 kV, 50 kV, 100 kV, 1 MV
Power Shutdown: Less than 1 mA
3-Wire SPI Compatible Serial Data Input
+5 V to +30 V Single Supply Operation
65 V to 615 V Dual Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD7376 provides a single channel, 128-position digitally-
controlled variable resistor (VR) device. This device performs the
same electronic adjustment function as a potentiometer or vari-
able resistor. These products were optimized for instrument and
test equipment applications where a combination of high voltage
with a choice between bandwidth or power dissipation are avail-
able as a result of the wide selection of end-to-end terminal resis-
tance values. The AD7376 contains a fixed resistor with a wiper
contact that taps the fixed resistor value at a point determined by
a digital code loaded into the SPI-compatible serial-input regis-
ter. The resistance between the wiper and either endpoint of the
fixed resistor varies linearly with respect to the digital code trans-
ferred into the VR latch. The variable resistor offers a completely
programmable value of resistance between the A terminal and the
wiper or the B terminal and the wiper. The fixed A to B terminal
resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal tem-
perature coefficient of –300 ppm/°C.
The VR has its own VR latch which holds its programmed resis-
tance value. The VR latch is updated from an internal serial-to-
parallel shift register which is loaded from a standard 3-wire
serial-input digital interface. Seven data bits make up the data
word clocked into the serial data input register (SDI). Only the
last seven bits of the data word loaded are transferred into the
7-bit VR latch when the CS strobe is returned to logic high. A
serial data output pin (SDO) at the opposite end of the serial
register allows simple daisy-chaining in multiple VR applications
without additional external decoding logic.
The reset (RS) pin forces the wiper to the midscale position by
loading 40H into the VR latch. The SHDN pin forces the resistor
to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When shutdown is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown as long as power to VDD is not re-
moved. The digital interface is still active in shutdown so that
code changes can be made that will produce a new wiper posi-
tion when the device is taken out of shutdown.
The AD7376 is available in both surface mount (SOL-16) and
the 14-lead plastic DIP package. For ultracompact solutions
selected models are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For operation at lower
supply voltages (+3 V to +5 V), see the AD8400/AD8402/
AD8403 products.
Figure 1.Detail Timing Diagram
The last seven data bits clocked into the serial input register will
be transferred to the VR 7-bit latch when CS returns to logic
high. Extra data bits are ignored.
AD7376–SPECIFICATIONS
(VDD/VSS = 615 V 6 10% or 6 5 V 6 10%, VA = +VDD, VB = VSS/0 V, –408C < TA < +858C
unless otherwise noted.)ELECTRICAL CHARACTERISTICS
DIGITAL INPUTS AND OUTPUTS
POWER SUPPLIES
DYNAMIC CHARACTERISTICS
AD7376
ORDERING GUIDE
NOTES
11Typicals represent average readings at +25°C, VDD = +15 V, and VSS = –15 V.
12Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27.Test Circuit.
13INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26.Test Circuit.
14Resistor terminals A, B, W have no limitations on polarity with respect to each other.
15Guaranteed by design and not subject to production test.
16Measured at the A terminal. A terminal is open circuit in shutdown mode.
17IOL = 200 μA for the 50 kΩ version operating at VDD = +5 V.
18PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
19Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band-
width. The highest R value results in the minimum overall power consumption.
10All dynamic characteristics use VDD = +15 V and VSS = –15 V.
11See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +5 V or +15 V.
12Propagation delay depends on value of VDD, RL and CL see Applications section.
Specifications subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +30 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V, –16.5 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +44 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . .±20 mA
Digital Input Voltages to GND . . . . . . . . . .0 V, VDD + 0.3 V
Digital Output Voltage to GND . . . . . . . . . . . . . .0 V, +30 V
Operating Temperature Range . . . . . . . . . . .–40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Package Power Dissipation . . . . . . . . . . . .(TJ MAX – TA)/θJA
Thermal Resistance θJA
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . .92°C/W
SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . .120°C/W
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240°C/W
PIN CONFIGURATIONS
PDIP & TSSOP-14 SOL-16
NC = NO CONNECT
VDD
SDO
SHDN
SDI
VSS
GND
CLK
NC = NO CONNECT
VDD
SDO
SDI
VSS
GND
CLK
SHDNCS
AD7376
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % R
CODE – Decimal
Figure 2.Wiper To End Terminal
Percent Resistance vs. Code
TEMPERATURE – 8C
NOMINAL END-TO-END RESISTANCE – k50
125
Figure 5. Nominal Resistance vs.
Temperature
SUPPLY VOLTAGE (VDD - VSS) – Volts
INL – LSB
0.4
Figure 8.Potentiometer Divider
Nonlinearity Error vs. Supply
Voltage
–Typical Performance Characteristics
CODE – Decimal
R-INL ERROR – LSB
–0.3
Figure 3.Resistance Step Position
Nonlinearity Error vs. Code
IWA – mA
– V0.2520.50.7511.251.51.75
Figure 6.Resistance Linearity vs.
Conduction Current
CODE – Decimal
T POTENTIOMETER
MODE TEMPCO – ppm/161283248648096112
–30
Figure 9. ΔVWB/ΔT Potentiometer
Mode Tempco
Figure 4. Relative Resistance Step
Change from Ideal vs. Code
SUPPLY VOLTAGE (VDD - VSS) – Volts
R_INL – LSB
0.6
Figure 7.Resistance Nonlinearity
Error vs. Supply Voltage
TEMPERATURE – 8C
WIPER CONTACT RESISTANCE –
200
Figure 10.Wiper Contact
Resistancevs. Temperature
CODE – Decimal
INL NONLINEARITY ERROR – LSB
–0.15
Figure 11.Potentiometer Divider
Nonlinearity Error vs. Code
FREQUENCY – Hz
GAIN – dB
10k100k1M
Figure 14.10 kΩ Gain vs. Frequency
vs. Code
FREQUENCY – Hz
GAIN – dB10k1M100k
–48
Figure 17.50 kΩ Gain vs. Frequency
vs. Code
CODE – Decimal
DNL – LSB
–0.15
Figure 12. Potentiometer Divider
Differential Nonlinearity Error
vs. Code
FREQUENCY – Hz
GAIN – dB
–4210k
100k
Figure 15.1 MΩ Gain vs. Frequency
vs. Code
2mS/DIV
Figure 18.Large Signal Settling Time
CODE – Decimal
RHEOSTAT MODE TEMPCO – ppm/
–100161283248648096112
Figure 13. ΔRWB/ΔT Rheostat Mode
Tempco
5mS/DIV
Figure 16.Midscale Transition Glitch
Figure 19.Total Harmonic Distortion
Plus Noise vs. Frequency
AD7376
FREQUENCY – Hz
GAIN – dB
–42100k10k
Figure 20.100 kΩ Gain vs. Frequency
vs. Code
FREQUENCY – Hz
GAIN – dB
–0.6100k1M10k
1001k
Figure 23.Gain Flatness vs Fre-
quency vs. Nominal Resistance RAB
TEMPERATURE – 8C
SUPPLY CURRENT – mA
Figure 26.Supply Current (IDD, ISS)
vs. Temperature
FREQUENCY – Hz
GAIN – dB
–42100k1M10k
–54
Figure 21.–3 dB Bandwidth vs.
Nominal Resistance
FREQUENCY – Hz
PSRR – dB1001k10k100k
Figure 24.Power Supply Rejection
vs. Frequency
TEMPERATURE – 8C
SHUTDOWN CURRENT –
Figure 27.IA_SD Shutdown Current vs.
Temperature
Figure 22.Clock Feedthrough
VB – Volts
RON– 250
40015
Figure 25.Incremental Wiper
Contact Resistance vs.
Common-Mode Voltage
CLOCK FREQUENCY – Hz
SUPPLY CURRENT – mA10k100k1M10M
0.5
Figure 28.IDD Supply Current vs.
Input Clock Frequency

Partno	Mfg	Dc	Qty	Available	Descript
AD7376AR10	AD	N/a	544	avai	+-15 V Operation Digital Potentiometer
AD7376AR50	AD	N/a	1	avai	+-15 V Operation Digital Potentiometer
AD7376ARU1M	ADI	N/a	10	avai	+-15 V Operation Digital Potentiometer
AD7376ARU50	AD	N/a	4	avai	+-15 V Operation Digital Potentiometer