AD73460BB-80 ,Six-Input Channel Analog Front EndOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte Memory DMA (BDMA, Full ..
AD734AN ,10 MHz, 4-Quadrant Multiplier/DividerFEATURESHigh Accuracy14-Lead DIP0.1% Typical Error(Q Package and N Package)High Speed10 MHz Full-Po ..
AD734AQ ,10 MHz, 4-Quadrant Multiplier/DividerSPECIFICATIONSA S S LTRANSFER FUNCTION
AD73460BB-80
Six-Input Channel Analog Front End
REV.0
Six-Input Channel
Analog Front End
FEATURES
AFE PERFORMANCE
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
72 dB SNR
64 kS/s Maximum Sample Rate
–80 dB Crosstalk
Low Group Delay (25�s Typ per ADC Channel)
Programmable Input Gain
Single Supply Operation
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD73460 is a six-input channel analog front-end processor
for general-purpose applications including industrial power meter-
ing or multichannel analog inputs. It features six 16-bit A/D
conversion channels, each of which provides 72dB signal-to-noise
ratio over a dc-to-2 kHz signal bandwidth. Each channel also
features a programmable input gain amplifier (PGA) with gain
settings in eight stages from 0 dB to 38 dB.
The AD73460 is particularly suitable for industrial power metering
as each channel samples synchronously, ensuring that there is
no (phase) delay between the conversions. The AD73460 also
features low group delay conversions on all channels.
An on-chip reference voltage of 1.25 V is included. The sampling
rate of the device is programmable with separate settings
offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of input channels by cas-
cading an extra AFE external to the AD73460.
The AD73460’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The AD73460-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and 16K
(16-bit) of data RAM. The AD73460-40 integrates 40K bytes
of on-chip memory configured as 8K words (24-bit) of program
RAM and 8K (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The AD73460 is available in a 119-ball
PBGA package.
AD73460
TopicPageFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PBGA BALL CONFIGURATION . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 10
ANALOG FRONT END . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FUNCTIONAL DESCRIPTION–AFE . . . . . . . . . . . . . . . 11
Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signal Conditioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 11
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 12
Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AFE Serial Port (SPORT2) . . . . . . . . . . . . . . . . . . . . . . . 13
SPORT2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 14
Decimation Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 14
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Resetting the AFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FUNCTIONAL DESCRIPTION—DSP . . . . . . . . . . . . . . 20
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DSP SECTION PIN DESCRIPTIONS . . . . . . . . . . . . . . . 21
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TopicPageLOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 23
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 25
PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Program Memory (Full Memory Mode) . . . . . . . . . . . . . 26
Program Memory (Host Mode) . . . . . . . . . . . . . . . . . . . . 26
DATA MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Memory (Full Memory Mode) . . . . . . . . . . . . . . . . 26
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . . 26
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . . 26
Boot Memory Select (BMS) Disable . . . . . . . . . . . . . . . . 27
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Byte Memory DMA (BDMA, Full Memory Mode) . . . . . 27
Internal Memory DMA Port (IDMA Port;
Host Memory Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . . 28
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bus Request and Bus Grant (Full Memory Mode) . . . . . . 28
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
INSTRUCTION SET DESCRIPTION . . . . . . . . . . . . . . . 29
DESIGNING AN EZ-ICE-COMPATIBLE
SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Target Board Connector for EZ-ICE Probe . . . . . . . . . . . 30
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 30
PM, DM, BM, IOM, and CM . . . . . . . . . . . . . . . . . . . . . 30
Target System Interface Signals . . . . . . . . . . . . . . . . . . . . 30
ANALOG FRONT END (AFE) INTERFACING . . . . . . . 30
DSP SPORT TO AFE INTERFACING . . . . . . . . . . . . . . 30
CASCADE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interfacing to the AFE’s Analog Inputs . . . . . . . . . . . . . . 31
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32
TABLE OF CONTENTS
AD73460
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz,
fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)SPECIFICATIONS
AD73460–SPECIFICATIONSNOTESOperating temperature range is as follows:–20°C to +85°C. Therefore, TMIN = –20°C and TMAX = +85°C.Test conditions:Input PGA set for 0dB gain (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38dB preamplifier
bypassed and input gain of 0 dB.Test Conditions:no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table I.AFE Section Current Summary (AVDD = DVDD = 3.3V)The above values are in mA. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0V,
fMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73460
SPECIFICATIONSNOTESBidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.Input only pins: RESET, BR, DR0, DR1, PWD.Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.Although specified for TTL outputs, all AD73460 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.0 V on BR.Idle refers to AD73460 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
and Type 6, and 20% are idle instructions.Applies to PBGA package type.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0V, fMCLK = 16.384 MHz, fSAMP = 64 kHz;
TA = TMIN to TMAX, unless otherwise noted.)
AD73460
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . .. –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –20°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
PBGA, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W
Reflow Soldering
Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . 225°C
Time at Maximum Temperature . . . . . . . . . . . . . . . 15 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
TIMING CHARACTERISTICS–AFE SECTION1NOTESFor details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
Specifications subject to change without notice.
(AVDD = 3 V to 3.6 V; DVDD = 3 V to 3.6 V; AGND = DGND = 0 V;
TA = TMlN to TMAX, unless otherwise noted.)
PBGA BALL CONFIGURATIONS
PBGA BALL CONFIGURATION
AD73460
PIN FUNCTION DESCRIPTIONS1AVDD
AGND
DGND
DVDD
ARESET
SCLK2
PIN FUNCTION DESCRIPTIONS1 (continued)NOTESRefer to the ADSP-2185L data sheet for a detailed description of the DSP pins.Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
AD73460
ARCHITECTURE OVERVIEWThe AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Every instructions can be executed in a single processor
cycle. The AD73460 assembly language uses an algebraic syntax
for ease of coding and readability. A comprehensive set of devel-
opment tools supports program development.
Figure 1.Functional Block Diagram
Figure 1 is an overall block diagram of the AD73460. The pro-
cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi-
tives are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations with 40 bits of
accumulation. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
sub routine calls and returns in a single cycle. With internal
loop counters and loop stacks, the AD73460 executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The AD73460 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
ANALOG FRONT ENDThe analog front end (AFE) of the AD73460 is configured as a
separate block that is normally connected to either SPORT0 or
SPORT1 of the DSP section. As it is not hardwired to either
SPORT users have total flexibility in how they wish to allocate
system resources to support the AFE. It is also possible to
further expand the number of analog input channels connected
to the SPORT by cascading an AD73360 device external to
the AD73460.
The AFE is configured as six input channels. It comprises six
independent encoder channels each featuring signal condition-
ing, programmable gain amplifier, sigma-delta A/D convertor
and decimator sections. Each of these sections is described in
further detail below. All channels share a common internal
reference whose nominal value is 1.25 V. Figure 2 shows a block
diagram of the AFE section of the AD73460. It shows six input
channels along with a common reference. Communication to all
channels is handled by the SPORT2 block which interfaces to
either SPORT0 or SPORT1 of the DSP section.
Figure 2.Functional Block Diagram of Analog Front End
Table II.PGA Settings for the Encoder Channel
ADCEach channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and increases
the resolution.
FUNCTIONAL DESCRIPTION—AFE
Encoder ChannelEach encoder channel consists of a signal conditioner, a switched
capacitor PGA, and a sigma-delta analog-to-digital converter
(ADC). An on-board digital filter, which forms part of the
sigma-delta ADC, also performs critical system-level filtering.
Due to the high level of oversampling, the input antialias require-
ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.
Signal ConditionerEach analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
Programmable Gain AmplifierEach encoder section’s analog front end comprises a Switched
Capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table II, may be used
to increase the signal level applied to the ADC from low output
sources such as microphones, and can be used to avoid placing
external amplifiers in the circuit. The input signal level to the
sigma-delta modulator should not exceed the maximum input
voltage permitted.
The PGA gain is set by bits IGS0, IGS1, and IGS2 in control
Registers D, E, and F.
AD73460
Analog Sigma-Delta ModulatorThe AD73460 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73460, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to fS/2 = DMCLK/16
(Figure 3a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 3b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 3c).
Figure 3.Sigma-Delta Noise Reduction
Figure 4 shows the various stages of filtering that are employed
in a typical AD73460 application. In Figure 4a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial over-
sampling rate and the bandwidth of interest. In Figure 4b, the
signal and noise-shaping responses of the sigma-delta modulator
are shown. The signal response provides further rejection of any
high frequency signals while the noise-shaping will push the inher-
ent quantization noise to an out-of-band position. The detail of
Figure 4c shows the response of the digital decimation filter
(Sinc-cubed response) with nulls every multiple of DMCLK/256,
which is the decimation filter update rate. The final detail in
Figure 4d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the user’s requirements and available MIPS. The filtering
in Figures 4a through 4c is implemented in the AD73460.
fB = 4kHzfSINIT = DMCLK/8Analog Antialias Filter Transfer Function
fB = 4kHzfSINIT = DMCLK/8
NOISE TRANSFER FUNCTION
SIGNAL TRANSFER FUNCTIONAnalog Sigma-Delta Modulator Transfer FunctionDigital Decimator Transfer FunctionFinal Filter LPF (HPF) Transfer Function
Figure 4.DC Frequency Responses
Decimation FilterThe digital filter used in the AD73460 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator and secondly, it deci-
mates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits. Its Z
transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a mini-
mal group delay of 25 µs.
ADC CodingThe ADC coding scheme is in two’s complement format (see
Figure 5). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale however, the output word is set at
0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
Figure 5.ADC Transfer Function
Voltage ReferenceThe AD73460 contains an internal bandgap reference that
provides a low noise, temperature-compensated reference to the
ADCs. The reference has a nominal value of 1.25 V and is avail-
able on the REFCAP pin. A buffered version of the reference is
available on the REFOUT pin and can be used to bias external
analog circuitry if required. The reference output (REFOUT) can
be enabled by setting the RU bit (CRC:6) in Control Register
C. It is possible to overdrive the internal reference by connecting
an external reference to the REFCAP pin. This may be required
when a different value of reference or better temperature coeffi-
cient is required. The current sink and source capabilities of the
REFCAP pin must be taken into consideration when overdriv-
ing the reference. When a lower value of external reference is
required it must have sufficient current sink capability to over-
ride the current source capabilities of the REFCAP pin. When a
higher value of external reference is required it can usually be
connected directly to the REFCAP pin as the pin can typically
only sink 0.25 mA before its value changes. Figure 6 shows a
plot of REFCAP Voltage versus Current. Note that the negative
values indicate that the external reference is sinking current to
provide the required reference voltage.
AFE Serial Port (SPORT2)
REFCAP – V
CURRENT
mA
1.101.201.301.401.50Figure 6.REFCAP Voltage vs. Current
additional external AFE can be cascaded to the internal AFE
(up to a limit of seven) to provide additional input channels
if required.
In both transmit and receive modes, data is transferred at the
serial clock (SCLK2) rate with the MSB being transferred first.
Communication between the AFE section and DSP section
must always be initiated by the AFE section (AFE is in master
mode, DSP is in slave mode). This ensures that there is no
collision between input data and output samples.
SPORT2 OverviewSPORT2 is a flexible, full-duplex, synchronous serial port
whose protocol has been designed to allow an additional AFE to
be connected in cascade to the DSP section. It has a very
flexible architecture that can be configured by programming two
of the internal control registers in each AFE block. SPORT2 has
three distinct modes of operation: Control Mode, Data Mode,
and Mixed Control/Data Mode.
NOTE: As each AFE has its own SPORT section, the register
settings in each must be programmed. The registers that control
SPORT and sample rate operation (CRA and CRB) must be
programmed with the same values to ensure correct operation.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the AFE. In Data Mode (CRA:0 = 1), any information
that is sent to the AFE is ignored, while the encoder section
(ADC) data is read from the device. In this mode, only ADC
data is read from the device. Mixed mode (CRA:0 = 1 and
CRA:1 = 1) allows the user to send control information and
receive either control information or ADC data. This is achieved
by using the MSB of the 16-bit frame as a flag bit. Mixed mode
reduces the resolution to 15 bits with the MSB being used to
indicate whether the information in the 16-bit frame is control
information or ADC data.
SPORT2 features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must
AD73460words to the AFE. In certain configurations, data can be written
to the device to coincide with the output sample being shifted
out of the serial register—see section on interfacing devices. The
serial clock rate (CRB:2–3) defines how many 16-bit words
can be written to a device before the next output sample event
will happen.
The SPORT2 block diagram, shown in Figure 7, details the
blocks associated with AFE including the eight control registers
(A–H), external AMCLK to internal DMCLK divider and serial
clock divider. The divider rates are controlled by the setting of
Control Register B. The AFE features a master clock divider
that allows users the flexibility of dividing externally available
high frequency DSP clocks to generate a lower frequency master
clock internally in the AFE, which may be more suitable for
either serial transfer or sampling rate requirements. The master
clock divider has five divider options (÷1 default condition, ÷2,
÷3, ÷4, ÷5) that are set by loading the master clock divider field
in Register B with the appropriate code (see Table VIII). Once
the internal device master clock (DMCLK) has been set using
the master clock divider, the sample rate and serial clock set-
tings are derived from DMCLK.
Figure 7.SPORT Block Diagram
SPORT2 can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the mas-
ter clock divider. Care should be taken when selecting Master
Clock, Serial Clock, and Sample Rate divider settings to ensure
that there is sufficient time to read all the data from the AFE
before the next sample interval.
SPORT Register MapsThere are eight control registers for the AFE, each eight bits
wide. Table VI shows the control register map for the AFE.
The first two control registers, CRA and CRB, are reserved for
controlling SPORT2. They hold settings for parameters such as
bit rate, internal master clock rate, and device count. If multiple
AFEs are cascaded, registers CRA and CRB on both devices
must be programmed with the same setting to ensure correct
operation. The other six registers, CRC through CRH, are used
Master Clock DividerThe AFE features a programmable master clock divider that
allows the user to reduce an externally available master clock, at
pin AMCLK, by one of the ratios 1, 2, 3, 4, or 5 to produce an
internal master clock signal (DMCLK) that is used to calculate
the sampling and serial clock rates. The master clock divider is
programmable by setting CRB:4–6. Table III shows the division
ratio corresponding to the various bit settings. The default divider
ratio is divide-by-one.
Table III.DMCLK (Internal) Rate Divider Settings
Serial Clock Rate DividerThe AFE features a programmable serial clock divider that allows
users to match the serial clock (SCLK2) rate of the data to that
of the DSP. The maximum SCLK2 rate available is DMCLK
and the other available rates are: DMCLK/2, DMCLK/4 and
DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK2
rate. The serial clock divider is programmable by setting bits
CRB:2–3. Table IV shows the serial clock rate corresponding to
the various bit settings.
Table IV.SCLK Rate Divider Settings
Decimation Rate DividerThe AFE features a programmable decimation rate divider that
allows users flexibility in matching the AFE’s ADC sample rates
to the needs of the DSP software. The maximum sample rate
available is DMCLK/256 and the other available rates are:
DMCLK/512, DMCLK/1024 and DMCLK/2048. The slowest
rate (DMCLK/2048) is the default sample rate. The sample rate
divider is programmable by setting bits CRB:0–1. Table V shows
the sample rate corresponding to the various bit settings.
Table V.Decimation Rate Divider Settings
Table VI.Control Register Map
Table VII.Control Word Description
CONTROL REGISTER A
AD73460
Table IX.Control Register B Description
Table X.Control Register C Description
Table XI.Control Register D Description
CONTROL REGISTER B
CONTROL REGISTER C
CONTROL REGISTER D
