AD73422BB-80 ,Dual Low Power CMOS Analog Front End with DSP MicrocomputerSPECIFICATIONS2Maximum Voltage Output SwingSingle-Ended 1.578 V p-p PGA = 6 dB–2.85 dBm Max Output ..
AD73460BB-80 ,Six-Input Channel Analog Front EndOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte Memory DMA (BDMA, Full ..
AD734AN ,10 MHz, 4-Quadrant Multiplier/DividerFEATURESHigh Accuracy14-Lead DIP0.1% Typical Error(Q Package and N Package)High Speed10 MHz Full-Po ..
AD734AQ ,10 MHz, 4-Quadrant Multiplier/DividerSPECIFICATIONSA S S LTRANSFER FUNCTION
AD73422BB-80
Dual Low Power CMOS Analog Front End with DSP Microcomputer
REV. 0
Dual Low Power CMOS
Analog Front End with DSP Microcomputer
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AFE PERFORMANCE
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25�s Typ per ADC Channel,
50 �s Typ per DAC Channel)
Programmable Input/Output Gain
On-Chip Reference
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
GENERAL DESCRIPTIONThe AD73422 is a single device incorporating a dual analog
front end and a microcomputer optimized for digital signal
processing (DSP) and other high speed numeric processing
applications.
The AD73422’s analog front end (AFE) section features a dual
front-end converter for general purpose applications including
speech and telephony. The AFE section features two 16-bit A/D
conversion channels and two 16-bit D/A conversion channels.
Each channel provides 77dB signal-to-noise ratio over a
voiceband signal bandwidth. It also features an input-to-output
gain network in both the analog and digital domains. This is
featured on both codecs and can be used for impedance match-
ing or scaling when interfacing to Subscriber Line Interface
Circuits (SLICs).
The AD73422 is particularly suitable for a variety of applica-
tions in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. The low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
applications. The A/D and D/A conversion channels feature
programmable input/output gains with ranges 38 dB and 21 dB
respectively. An on-chip reference voltage is included to allow
single supply operation.
The sampling rate of the AFE is programmable with four sepa-
rate settings offering 64, 32, 16 and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of I/O channels by cascad-
ing extra AFEs external to the AD73422.
The AD73422’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities and on-chip program
and data memory.
The AD73422-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73422-40 integrates 40K
bytes of on-chip memory configured as 8K words (24-bit) of
program RAM, and 8K words (16-bit) of data RAM. Power-
down circuitry is also provided to meet the low power needs of
battery operated portable equipment. The AD73422 is available
in a 119-ball PBGA package.
AD73422–SPECIFICATIONS
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0V, fDMCLK = 16.384MHz,
fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73422LOGIC INPUTS
LOGIC OUTPUT
POWER SUPPLIES
NOTESOperating temperature range is as follows:–20°C to +85°C; therefore, TMIN = –20°C and TMAX = +85°C.Test conditions:Input PGA set for 0dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 1011)/DMCLK.Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.At VOUT output.
AD73422–SPECIFICATIONSVIL
VOL
IIH
IOZL
IDD
IDD
NOTESBidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.Input only pins: RESET, BR, DR0, DR1, PWD.Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.Although specified for TTL outputs, all AD73422 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.0 V on BR.Idle refers to AD73422 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.Applies to PBGA package type.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
(AVDD = DVDD = VDD = +3 V to 3.6 V; DGND = AGND = 0V, fDMCLK = 16.384MHz,
fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73422
POWER CONSUMPTIONNOTES
The above values are in mA and are typical values unless otherwise noted.
Specifications subject to change without notice.
TIMING CHARACTERISTICS–AFE SECTION1NOTESFor details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
Specifications subject to change without notice.
AD73422
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73422 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . .. –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –40°C to +125°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
PBGA, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W
Reflow Soldering
Maximum Temperature . . . . . . . . . . . . . . . . . . . . . .+225°C
Time at Maximum Temperature . . . . . . . . . . . . . . . . .15 sec
Maximum Temperature Ramp Rate . . . . . . . . . . . .1.3°C/sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PBGA BALL CONFIGURATION123457
TOP VIEWNOTES:
VDD (INT) – DSP CORE SUPPLY
VDD (EXT) – DSP I/O DRIVER SUPPLY
BOTH VDD (INT) AND VDD (EXT) SHOULD BE POWERED FROM THE SAME SUPPLY.
PBGA BALL CONFIGURATION DESCRIPTIONS
AD73422
PBGA BALL CONFIGURATION DESCRIPTIONS (Continued)NOTES
ARCHITECTURE OVERVIEWThe AD73422 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The AD73422 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set
of development tools supports program development.
Figure 1.Functional Block Diagram
Figure 1 is an overall block diagram of the AD73422. The pro-
cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations; divi-
sion primitives are also supported. The MAC performs single-
cycle multiply, multiply/add and multiply/subtract operations
with 40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization and derive
exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73422 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The AD73422 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The AD73422 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Analog Front EndThe AFE section is configured as a separate block that is nor-
mally connected to either SPORT0 or SPORT1 of the DSP
section. As it is not hardwired to either SPORT, the user has
total flexibility in how they wish to allocate system resources to
support the AFE. It is also possible to further expand the num-
ber of analog I/O channels connected to the SPORT by cascad-
ing other single or dual channel AFEs (AD73311 or AD73322)
external to the AD73422.
The AFE is configured as a cascade of two I/O channels (similar
to that of the discrete AD73322—refer to the AD73322 data sheet
for more details), with each channel having a separate 16-bit
sigma-delta based ADC and DAC. Both channels share a com-
mon reference whose nominal value is 1.2V. Figure 2 shows a
block diagram of the AFE section of the AD73422. It shows two
channels of ADC and DAC conversion, along with a common
reference. Communication to both channels is handled by the
SPORT2 block which interfaces to either SPORT0 or SPORT1 of
the DSP section.
Figure 3 shows the analog connectivity available on each chan-
nel of the AFE (Channel 1 is detailed here). Both channels
feature fully differential inputs and outputs. The input section
allows direct connection to the internal Programmable Gain
Amplifier at the input of the sigma-delta ADC section, or op-
tional inverting amplifiers may be configured to provide some
fixed external gain or to interface to a transducer with relatively
AD73422Figure 2.Functional Block Diagram of Analog Front End Section
samples at DMCLK/8. Its bitstream output is filtered and deci-
mated by a Sinc-cubed decimator to provide a sample rate se-
lectable from 64 kHz, 32 kHz, 16 kHz or 8 kHz (based on an
AMCLK of 16.384 MHz).
Figure 3.Analog Front End Configuration
The DAC channel features a Sinc-cubed interpolator which
increases the sample rate from the selected rate to the digital
sigma-delta modulator rate of DMCLK/8. The digital sigma-
Each channel also features two programmable gain elements,
Analog Gain Tap (AGT) and Digital Gain Tap (DGT), which,
when enabled, add a signed and scaled amount of the input
signal to the DAC’s output signal. This is of particular use in
line impedance balancing when interfacing the AFE to Sub-
scriber Line Interface Circuits (SLICs).
FUNCTIONAL DESCRIPTION - AFE
Encoder ChannelsBoth encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input anti-
alias requirements are reduced such that a simple single-pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Programmable Gain AmplifierEach encoder section’s analog front end comprises a switched
capacitor PGA which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table I, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
Table I.PGA Settings for the Encoder Channel
ADCBoth ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decima-
tion filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta ModulatorThe AD73422’s input channels employ a sigma-delta conver-
sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling where the sampling rate is many times the highest
frequency of interest. In the case of the AD73422, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to FS/2 = DMCLK/16
(Figure 4a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 4b). The combination
of these techniques, followed by the application of a digital
filter, sufficiently reduces the noise in band to ensure good
dynamic performance from the part (Figure 4c).
Figure 5 shows the various stages of filtering that are employed
in a typical AD73422 application. In Figure 5a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling fre-
quency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 5b,
the signal and noise-shaping responses of the sigma-delta modu-
lator are shown. The signal response provides further rejection
of any high frequency signals, while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 5c shows the response of the digital decima-
tion filter (Sinc-cubed response) with nulls every multiple of
DMCLK/256, which corresponds to the decimation filter up-
date rate for a 64 kHz sampling. The nulls of the Sinc3 response
correspond with multiples of the chosen sampling frequency.
The final detail in Figure 5d shows the application of a final
antialias filter in the DSP engine. This has the advantage of
being implemented according to the user’s requirements and
available MIPS. The filtering in Figures 5a through 5c is imple-
mented in the AD73422.
FB = 4kHzFSINIT = DMCLK/8Analog Antialias Filter Transfer Function
FB = 4kHzFSINIT = DMCLK/8
SIGNAL TRANSFER FUNCTIONAnalog Sigma-Delta Modulator Transfer Function
FB = 4kHzFSINTER = DMCLK/256Digital Decimator Transfer Function
AD73422
Decimation FilterThe digital filter used in the AD73422’s AFE section carries out
two important functions. Firstly, it removes the out-of-band
quantization noise, which is shaped by the analog modulator,
and secondly, it decimates the high frequency bitstream to a
lower rate 16-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits or
greater (depending on chosen sampling rate). Its Z transform is
given as: [(1–Z–N)/(1–Z–1)]3 where N is set by the sampling rate
(N = 32 @ 64 kHz sampling...N = 256 @ 8 kHz sampling)
Thus when the sampling rate is 64 kHz a minimal group delay
of 25 µs can be achieved.
Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio between
sigma-delta modulator and decimator output equals 32, we get
five bits per stage of the three stage Sinc3 filter. Due to symme-
try within the sigma-delta modulator, the LSB will always be a
zero, therefore the 16-bit ADC output word will have 2 LSBs
equal to zero, one due to the sigma-delta symmetry and the
other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in
transferring the decimator output as the ADC word. For example
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator output.
This yields eight bits per stage of the 3-stage Sinc3 filter.
ADC CodingThe ADC coding scheme is in twos complement format (see
Figure 6). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a word length of up to 18 bits
(depending on decimation rate chosen), which is the final out-
put of the ADC block. In Data Mode this value is truncated to
16 bits for output on the Serial Data Output (SDO) pin. For
input values equal to or greater than positive full scale, however,
VREF
ANALOG
INPUT
VREF + (VREF � 0.32875)
VREF – (VREF � 0.32875)
ANALOG
INPUT
VREF + (VREF � 0.6575)
VREF – (VREF � 0.6575)
ADC CODE DIFFERENTIAL
VREFthe output word is set at 0x7FFF, which has the LSB set to 1.
In mixed Control/Data Mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.
Decoder ChannelThe decoder channels consist of digital interpolators, digital
sigma-delta modulators, single bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain ampli-
fiers with differential outputs.
DAC CodingThe DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation FilterThe anti-imaging interpolation filter is a sinc-cubed digital filter
that up-samples the 16-bit input words from the input sample
rate to a rate of DMCLK/8, while filtering to attenuate images
produced by the interpolation process. Its’ Z transform is given
as: [(1–Z–N)/(1–Z–1)]3 where N is determined by the sampling
rate (N = 32 @ 64 kHz... N = 256 @ 8 kHz). The DAC re-
ceives 16-bit samples from the host DSP processor at the pro-
grammed sample rate of DMCLK/N. If the host processor fails
to write a new value to the serial port, the existing (previous)
data is read again. The data stream is filtered by the anti-imaging
interpolation filter, but there is an option to bypass the interpo-
lator for the minimum group delay configuration by setting the
IBYP bit (CRE:5) of Control Register E. The interpolation filter
has the same characteristics as the ADC’s antialiasing decima-
tion filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized in
the passband of the converter. The bitstream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGAThe output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB todB in 3 dB steps, as shown in Table II. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
Table II.PGA Settings for the Decoder Channel
Differential Output AmplifiersThe decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal is
dc-biased to the codec’s on-chip voltage reference.
Voltage ReferenceThe AD73422 reference, REFCAP, is a bandgap reference that
provides a low noise, temperature-compensated reference to the
DAC and ADC. A buffered version of the reference is also made
available on the REFOUT pin and can be used to bias other
external analog circuitry. The reference has a nominal value of
1.2V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Figure 7.Analog Input/Output Section
Analog and Digital Gain TapsThe AD73422 features analog and digital feedback paths be-
tween input and output. The amount of feedback is determined
by the gain setting that is programmed in the control registers.
This feature can typically be used for balancing the effective
impedance between input and output when used in Subscriber
Line Interface Circuit (SLIC) interfacing.
Analog Gain TapThe analog gain tap is configured as a programmable differential
amplifier whose input is taken from the ADC’s input signal
path. The output of the analog gain tap is summed with the
output of the DAC. The gain is programmable using Control
Register F (CRF:0-4) to achieve a gain of –1 to +1 in 32 steps,
with muting being achieved through a separate control setting
(Control Register F Bit _). The gain increment per step is 0.0625.
The AGT is enabled by powering up the AGT control bit in the
power control register (CRC:1). When this bit is set (=1) CRF
becomes an AGT control register with CRF:0-4 holding the
AGT coefficient, CRF:5 becomes an AGT enable and CRF:7
becomes an AGT mute control bit. Control bit CRF:5 connects/
disconnects the AGT output to the summer block at the output
of the DAC section while control bit CRF:7 overrides the gain
Table III.Analog Gain Tap Settings**AGE and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Digital Gain TapThe digital gain tap features a programmable gain block whose
input is taken from the bitstream from the ADC’s sigma-delta
modulator. This single bit input (1 or 0) is used to add or sub-
tract a programmable value, which is the digital gain tap setting,
to the output of the DAC section’s interpolator. The program-
mable setting has 16-bit resolution and is programmed using the
settings in Control Registers G and H.
Table IV.Digital Gain Tap Settings**AGE and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
AFE Serial Port (SPORT2)The AFE section communicates with the DSP section via its
bidirectional synchronous serial port (SPORT2), which interfaces
to either SPORT0 or SPORT1 of the DSP section. SPORT2 is
used to transmit and receive digital data and control informa-
tion. The dual AFE is implemented using two separate AFE
blocks that are internally cascaded with serial port access to the
input of AFE Channel 1 and the output of AFE Channel 2.
This allows other single or dual codec devices to be cascaded
together (up to a limit of eight codec units).
In both transmit and receive modes, data is transferred at the
serial clock (SCLK2) rate with the MSB being transferred first.
Communications between the AFE section and the DSP section
AD73422Figure 8.SPORT2 Block Diagram
SPORT2 OverviewSPORT2 is a flexible, full-duplex, synchronous serial port
whose protocol has been designed to allow extra AFE devices
(AD733xx series), up to a maximum of eight I/O channels, to be
connected in cascade to a DSP SPORT (0 or 1). It has a very
flexible architecture that can be configured by programming two
of the internal control registers in each AFE block. SPORT2 has
three distinct modes of operation: Control Mode, Data Mode
and Mixed Control/Data Mode.
NOTE:As each AFE has its own control section, the register
settings in each must be programmed. The registers that control
serial transfer and sample rate operation (CRA and CRB) must
be programmed with the same values, otherwise incorrect opera-
tion may occur.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), information
that is sent to the device is used to update the decoder section
(DAC), while the encoder section (ADC) data is read from the
device. In this mode, only DAC and ADC data is written to or
read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)
allows the user to choose whether the information being sent to
the device contains either control information or DAC data.
This is achieved by using the MSB of the 16-bit frame as a flag
bit. Mixed mode reduces the resolution to 15 bits with the MSB
being used to indicate whether the information in the 16-bit
frame is control information or DAC/ADC data.
SPORT2 features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must
be written to SPORT2 without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once SPORT2 starts to output
interfacing. The serial clock rate (CRB:2–3) defines how many
16-bit words can be written to a device before the next output
sample event will happen.
The SPORT2 block diagram, shown in Figure 8, details the
blocks associated with codecs 1 and 2, including the eight con-
trol registers (A–H), external AMCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73422 features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to gen-
erate a lower frequency master clock internally in the codec
which may be more suitable for either serial transfer or sampling
rate requirements. The master clock divider has five divider
options (÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are set by
loading the master clock divider field in Register B with the appro-
priate code. Once the internal device master clock (DMCLK) has
been set using the master clock divider, the sample rate and
serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK)
rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or
DMCLK/8, where DMCLK is the internal or device master
clock resulting from the external or pin master clock being di-
vided by the master clock divider. When working at the lower
SCLK rate of DMCLK/8, which is intended for interfacing with
slower DSPs, the SPORT will support a maximum of two codecs
in cascade (a single AD73422 or two AD73311s) with the sample
rate of DMCLK/256.
SPORT2 Register MapsThere are two register banks for each AFE channel in the
AD73422: the control register bank and the data register bank.
The control register bank consists of eight read/write registers,
each eight bits wide. Table IX shows the control register map
for the AD73422. The first two control registers, CRA and
CRB, are reserved for controlling serial activity. They hold
settings for parameters such as serial clock rate, internal master
other five registers; CRC through CRH are used to hold control
settings for the ADC, DAC, Reference, Power Control and
Gain Tap sections of the device. It is not necessary that the
contents of CRC through CRH on each codec are similar. Con-
trol registers are written to on the negative edge of SCLK. The
data register bank consists of two 16-bit registers that are the
DAC and ADC registers.
Master Clock DividerThe AD73422’s AFE features a programmable master clock
divider that allows the user to reduce an externally available
master clock, at pin AMCLK, by one of the ratios 1, 2, 3, 4 or
5, to produce an internal master clock signal (DMCLK) that is
used to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table V
shows the division ratio corresponding to the various bit set-
tings. The default divider ratio is divide-by-one.
Table V.DMCLK (Internal) Rate Divider Settings
Serial Clock Rate DividerThe AD73422’s AFE features a programmable serial clock
divider that allows users to match the serial clock (SCLK) rate
of the data to that of the DSP engine or host processor. The
maximum SCLK rate available is DMCLK, and the other avail-
able rates are: DMCLK/2, DMCLK/4 and DMCLK/8. The
slowest rate (DMCLK/8) is the default SCLK rate. The serial
clock divider is programmable by setting bits CRB:2–3. Table
VI shows the serial clock rate corresponding to the various bit
settings.
Table VI.SCLK Rate Divider Settings
Sample Rate DividerThe AD73422 features a programmable sample rate divider that
allows users flexibility in matching the codec’s ADC and DAC
sample rates (decimation/interpolation rates) to the needs of the
DSP software. The maximum sample rate available is DMCLK/
256, which offers the lowest conversion group delay, while the
other available rates are: DMCLK/512, DMCLK/1024 and
DMCLK/2048. The slowest rate (DMCLK/2048) is the default
sample rate. The sample rate divider is programmable by setting
bits CRB:0-1. Table VII shows the sample rate corresponding to
the various bit settings.
Table VII.Sample Rate Divider Settings
DAC Advance RegisterThe loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The de-
fault DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(FS × 32); see Table VIII. The sample
rate FS is dependent on the setting of both the AMCLK divider
and the Sample Rate divider; see Tables VII and IX. In certain
circumstances this DAC update adjustment can reduce the
group delay when the ADC and DAC are used to process data
in series. See AD73322 data sheet (Appendix C) for details of
how the DAC advance feature can be used.
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
Table VIII.DAC Timing Control
Table IX.Control Register Map
AD73422
Table X.Control Word Description
Table XI.Control Register A Description
Table XII.Control Register B Description
Table XIII.Control Register C Description
Table XIV.Control Register D Description
Table XV.Control Register E Description
AD73422
Table XVI.Control Register F Description
Table XVII.Control Register G Description
Table XVIII.Control Register H Description
