AD73360LAR ,Six-Input Channel Analog Front EndSPECIFICATIONS2, 3Maximum Input Range at VIN 1.578 V p-p Measured Differentially–2.85 dBmNominal Re ..
AD73360LAR-REEL ,Six-Input Channel Analog Front EndSPECIFICATIONS2, 3Maximum Input Range at VIN 1.578 V p-p Measured Differentially–2.85 dBmNominal Re ..
AD7339BS ,5 V Integrated High Speed ADC/Quad DAC SystemGENERAL DESCRIPTIONREFERENCEVREFAThe AD7339 is a composite IC that contains both DAC andAVDDADC fun ..
AD7339BS ,5 V Integrated High Speed ADC/Quad DAC SystemSPECIFICATIONS wise noted)Parameter B Version Units Test Conditions/CommentsADC ADCCLK = 2.048 MHzR ..
AD734 ,10 MHz, 4-Quadrant Multiplier/DividerSPECIFICATIONSA S S LTRANSFER FUNCTION
AD73360LAR
Six-Input Channel Analog Front End
REV.0
FEATURES
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
76 dB SNR
64 kS/s Maximum Sample Rate
–95 dB Crosstalk
Low Group Delay (25�s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port Which Allows Multiple Devices to
Be Connected in Cascade
Single (2.7V to 3.6V) Supply OperationmW Max Power Consumption at 2.7V
On-Chip Reference
28-Lead SOIC Package
APPLICATIONS
General-Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD73360L is a six-input channel analog front-end proces-
sor for general-purpose applications, including industrial power
metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels, each of which provides 76dB signal-
to-noise ratio over a dc-to-4kHz signal bandwidth. Each
channel also features a programmable input gain amplifier (PGA)
with gain settings in eight stages from 0 dB to 38 dB.
The AD73360L is particularly suitable for industrial power
metering as each channel samples synchronously, ensuring that
there is no (phase) delay between the conversions. The AD73360L
also features low group delay conversions on all channels.
An on-chip reference voltage is included with a nominal value
of 1.2 V.
The sampling rate of the device is programmable, with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry-standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73360L is available in 28-lead SOIC package.
Six-Input Channel
Analog Front End
AD73360L–SPECIFICATIONS1(AVDD = 2.7V to 3.6V; DVDD = 2.7V to 3.6V; DGND = AGND = 0V, fMCLK = 16.384MHz,
fSCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)ADC SPECIFICATIONS
AD73360LNOTESOperating temperature range is as follows:–40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.Test conditions:Input PGA set for 0dB gain (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38dB preamplifier
bypassed and input gain of 0 dB.Test Conditions:no load on digital inputs, analog inputs ac-coupled to ground.
Specifications subject to change without notice.
Table I.Current Summary (AVDD = DVDD = 3.3V)The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
TIMING CHARACTERISTICS
(AVDD = 2.7V to 3.6V; DVDD = 2.7V to 3.6V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless other-
wise noted.)
AD73360LFigure 1.MCLK Timing
Figure 2.Load Circuit for Timing Specifications
Figure 3.SCLK Timing
Figure 4.Serial Port (SPORT)
VIN – dBm0
S/(N+D) – dB
3.17Figure 5.S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . . . . . . . . –0.3 V to AVDD
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
ORDERING GUIDE
PIN CONFIGURATION
R-28
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73360L features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD73360L
PIN FUNCTION DESCRIPTIONSTERMINOLOGY
Absolute GainAbsolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0dBm0 for each ADC. The absolute gain specification
is used for gain tracking error specification.
CrosstalkCrosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking ErrorGain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by
definition.
Group DelayGroup delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel NoiseIdle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 0Hz–4 kHz).
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply RejectionPower supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample RateThe sample rate is the rate at which each ADC updates its output
register. It is set relative to the DMCLK and the programmable
sample rate setting.
SNR + THDSignal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in a given frequency
range, including harmonics but excluding dc.
ABBREVIATIONSADCAnalog-to-Digital Converter.Bandwidth.
CRxA Control Register where x is a placeholder for
an alphabetic character (A–E). There are eight
read/write control registers on the AD73360L—
designated CRA through CRE.
CRx:nA bit position, where n is a placeholder for a
numeric character (0–7), within a control regis-
ter; where x is a placeholder for an alphabetic
character (A–E). Position 7 represents the MSB
and Position 0 represents the LSB.
DMCLKDevice (Internal) Master Clock. This is the
internal master clock resulting from the external
master clock (MCLK) being divided by the on-
chip master clock divider.
FSLBFrame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of non-FSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.
PGAProgrammable Gain Amplifier.Switched Capacitor.
SNRSignal-to-Noise Ratio.
SPORTSerial Port.
THDTotal Harmonic Distortion.
VBWVoice Bandwidth.
AD73360L
FUNCTIONAL DESCRIPTION
General DescriptionThe AD73360L is a six-input channel, 16-bit, analog front end.
It comprises six independent encoder channels each featuring
signal conditioning, programmable gain amplifier, sigma-delta
A/D converter and decimator sections. Each of these sections is
described in further detail below.
Encoder ChannelEach encoder channel consists of a signal conditioner, a switched
capacitor PGA, and a sigma-delta analog-to-digital converter
(ADC). An on-board digital filter, which forms part of the
sigma-delta ADC, also performs critical system-level filtering.
Due to the high-level of oversampling, the input antialias require-
ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.
Signal ConditionerEach analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
Programmable Gain AmplifierEach encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table II, may
be used to increase the signal level applied to the ADC from
low-output sources such as microphones, and can be used to
avoid placing external amplifiers in the circuit. The input signal
level to the sigma-delta modulator should not exceed the maxi-
mum input voltage permitted.
The PGA gain is set by bits IGS0, IGS1, and IGS2 in control
Registers D, E, and F.
Table II.PGA Settings for the Encoder Channel
ADCEach channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and increases
the resolution.
Analog Sigma-Delta ModulatorThe AD73360L input channels employ a sigma-delta conver-
sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73360L, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to fS/2 = DMCLK/16
(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 6c).
Figure 6.Sigma-Delta Noise Reduction
Figure 7 shows the various stages of filtering that are employed
in a typical AD73360L application. In Figure 7a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes care
of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial oversam-
pling rate and the bandwidth of interest. In Figure 7b, the signal
and noise-shaping responses of the sigma-delta modulator are
shown. The signal response provides further rejection of any
high-frequency signals while the noise-shaping will push the
inherent quantization noise to an out-of-band position. The detail
of Figure 7c shows the response of the digital decimation filter
(sinc-cubed response) with nulls every multiple of DMCLK/
256, which is the decimation filter update rate. The final detail
in Figure 7d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the user’s requirements and available MIPS. The filtering in
Figures 7a through 7c is implemented in the AD73360L.
FB = 4kHzFSINIT = DMCLK/8Analog Antialias Filter Transfer Function
FB = 4kHzFSINIT = DMCLK/8
NOISE TRANSFER FUNCTION
SIGNAL TRANSFER FUNCTIONAnalog Sigma-Delta Modulator Transfer FunctionDigital Decimator Transfer Function
Decimation FilterThe digital filter used in the AD73360L carries out two impor-
tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high-frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits. Its
Z transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a mini-
mal group delay of 25 µs.
Word growth in the decimator is determined by the sampling
rate. At 64kHz sampling, where the oversampling ratio between
the sigma-delta modulator and decimator output equals 32,
there are five bits per stage of the three-stage Sinc3 filter. Due to
symmetry within the sigma-delta modulator, the LSB will always
be a zero; therefore, the 16-bit ADC output word will haveLSBs equal to zero, one due to the sigma-delta symmetry and
the other being a padded zero to make up a 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in trans-
ferring the decimator output as the ADC word. For example
at 8kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator. This yields
eight bits per stage of the three stage Sinc3 filter.
ADC CodingThe ADC coding scheme is in two’s complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale, however, the output word is set
at 0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
AD73360L
Voltage ReferenceThe AD73360L reference, REFCAP, is a bandgap reference
that provides a low noise, temperature-compensated reference
to the ADC. A buffered version of the reference is also made
available on the REFOUT pin and can be used to bias other
external analog circuitry. The reference has a default nominal
value of 1.2 V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Serial Port (SPORT)The AD73360Ls communicate with a host processor via the
bidirectional synchronous serial port (SPORT) which is compat-
ible with most modern DSPs. The SPORT is used to transmit
and receive digital data and control information. Two AD73360Ls
can be cascaded together to provide additional input channels.
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT of each AD73360L block uses
a common serial register for serial input and output, communi-
cations between an AD73360L and a host processor (DSP
engine) must always be initiated by the AD73360Ls themselves.
In this configuration the AD73360Ls are described as being in
Master mode. This ensures that there is no collision between
input data and output samples.
SPORT OverviewThe AD73360L SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to
eight AD73360L devices to be connected in cascade, to a single
DSP via a six-wire interface. It has a very flexible architecture
that can be configured by programming two of the internal
control registers in each device. The AD73360L SPORT has
three distinct modes of operation: Control Mode, Data Mode
and Mixed Control/Data Mode.
Figure 9.SPORT Block Diagram
Note: As each AD73360L has its own SPORT section, the
register settings in all SPORTs must be programmed. The regis-
ters that control SPORT and sample rate operation (CRA and
CRB) must be programmed with the same values, otherwise
incorrect operation may occur.
In Program Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the AD73360L. In Data Mode (CRA:0 = 1), any infor-
mation that is sent to the device is ignored, while the encoder
section (ADC) data is read from the device. In this mode, only
ADC data is read from the device. Mixed mode (CRA:0 = 1 and
CRA:1 = 1) allows the user to send control information and
receive either control information or ADC data. This is achieved
by using the MSB of the 16-bit frame as a flag bit. Mixed mode
reduces the resolution to 15 bits with the MSB being used to
indicate whether the information in the 16-bit frame is control
information or ADC data.
The SPORT features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must be
written to the SPORT without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once the SPORT starts to output
the latest ADC word, it is safe for the DSP to write new control
words to the AD73360L. In certain configurations, data can be
written to the device to coincide with the output sample being
shifted out of the serial register—see section on interfacing
devices. The serial clock rate (CRB:2–3) defines how many 16-bit
words can be written to a device before the next output sample
event will happen.
The SPORT block diagram, shown in Figure 9, details the blocks
associated with AD73360L including the eight control registers
(A–H), external MCLK to internal DMCLK divider and serial
clock divider. The divider rates are controlled by the setting of
Control Register B. The AD73360L features a master clock
divider that allows users the flexibility of dividing externally
available high-frequency DSP or CPU clocks to generate a lower
frequency master clock internally in the AD73360L which may be
more suitable for either serial transfer or sampling rate require-
ments. The master clock divider has five divider options (÷1
default condition, ÷2, ÷3, ÷4, ÷5) that are set by loading the
master clock divider field in Register B with the appropriate
code (see Table XIII). Once the internal device master clock
(DMCLK) has been set using the master clock divider, the sample
rate and serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the master
clock divider. Care should be taken when selecting Master Clock,
Serial Clock, and Sample Rate divider settings to ensure that
there is sufficient time to read all the data from the AD73360L
before the next sample interval.
Table IV.Control Word Description
Table III.Control Register Map
Table V.Control Register A Description
CONTROL REGISTER A
AD73360L
Table VI.Control Register B Description
Table VII.Control Register C Description
Table VIII.Control Register D Description
CONTROL REGISTER B
CONTROL REGISTER D
CONTROL REGISTER C
Table IX.Control Register E Description
Table X.Control Register F Description
Table XI.Control Register G Description
CONTROL REGISTER E
CONTROL REGISTER G
CONTROL REGISTER F
AD73360L
Table XII.Control Register H Description
REGISTER BIT DESCRIPTIONS
Control Register ACRA:0Data/Program Mode. This bit controls the operating mode of the AD73360L. If CRA:1 is 0, a 0 in this bit places the
part in Program Mode. If CRA:1 is 0, a 1 in this bit places the part in Data Mode.
CRA:1Mixed Mode. If this bit is a 0, the operating mode is determined by CRA:0. If this bit is a 1, the part operates in
Mixed Mode.
CRA:2Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.
CRA:3SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation.
CRA:4–6Device Count Bits. These bits tell the AD73360L how many devices are used in a cascade. Both devices in the
cascade should be programmed to the same value ensure correct operation. See Table XVI.
CRA:7Reset. Writing a 1 to this bit will initiate a software reset of the AD73360L.
Control Register BCRB:0–1Decimation Rate. These bits are used to set the decimation of the AD73360L. See Table XV.
CRB:2–3Serial Clock Divider. These bits are used to set the serial clock frequency. See Table XIV.
CRB:4–6Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table XIII.
CRB:7Control Echo Enable. Setting this bit to a 1 will cause the AD73360L to write out any control words it receives.
This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode.
Control Register CCRC:0Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360L to power up, regardless of
the status of the Power Control Bits in CRD-CRF. If fewer than six channels are required, this bit should be set to
0 and the Power Control Bits of the relevant channels should be set to 1.
CRC:1–4Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation.
CRC:5Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the refer-
ence. A 0 in this bit will power down the reference. Note that the reference is automatically powered up if any
channel is enabled.
CRC:6Reference Output. When this bit is set to 1, the REFOUT pin is enabled.
CRC:7Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.
Control Register DCRD:0–2Input Gain Selection. These bits select the input gain for ADC1. See Table II.
CRD:3Power Control for ADC1. A 1 in this bit powers up ADC1.
CRD:4–6Input Gain Selection. These bits select the input gain for ADC2. See Table II.
CRD:7Power Control for ADC2. A 1 in this bit powers up ADC2.
Control Register ECRE:0–2Input Gain Selection. These bits select the input gain for ADC3. See Table II.
CONTROL REGISTER H
Control Register FCRF:0–2Input Gain Selection. These bits select the input gain for ADC5. See Table II.
CRF:3Power Control for ADC5. A 1 in this bit powers up ADC5.
CRF:4–6Input Gain Selection. These bits select the input gain for ADC6. See Table II.
CRF:7Power Control for ADC6. A 1 in this bit powers up ADC6.
Control Register GCRG:0–5Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit
(CRG:6) is 1, a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the Single-
Ended Enable Mode bit (CRG:7) is 1, a 1 in a Channel Select bit location will put that channel into Single-Ended
Mode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-Ended Mode and
will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7.
CRG:6Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel
Select bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation.
CRG:7Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel
Select bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels.
Control Register HCRH:0–5Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1,
a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel Select
bit set to 0, the channel will not be inverted regardless of the state CRH:7.
CRH:6Test Mode Enable. This bit should be set to 0 to ensure normal operation.
CRH:7Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit
(CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels.
SPORT Register MapsThere are eight control registers for the AD73360L, each eight
bits wide. Table III shows the control register map for the
AD73360L. The first two control registers, CRA and CRB, are
reserved for controlling the SPORT. They hold settings for
parameters such as bit rate, internal master clock rate, and device
count. If two AD73360Ls are cascaded, Registers CRA and
CRB on each device must be programmed with the same setting
to ensure correct operation (this is shown in the programming
examples). The other six registers; CRC through CRH are
used to hold control settings for the Reference, Power Control,
ADC channel, and PGA sections of the device. It is not necessary
that the contents of CRC through CRH on each AD73360L
are similar. Control registers are written to on the negative
edge of SCLK.
Master Clock DividerThe AD73360L features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5 to
produce an internal master clock signal (DMCLK) that is used
to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table XIII
shows the division ratio corresponding to the various bit set-
tings. The default divider ratio is divide-by-one.
Table XIII.DMCLK (Internal) Rate Divider Settings
Serial Clock Rate DividerThe AD73360L features a programmable serial clock divider
that allows users to match the serial clock (SCLK) rate of the
data to that of the DSP engine or host processor. The maximum
SCLK rate available is DMCLK and the other available rates
are: DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
is programmable by setting bits CRB:2–3. Table XIV shows the
serial clock rate corresponding to the various bit settings.
Table XIV.SCLK Rate Divider Settings
AD73360L
Decimation Rate DividerThe AD73360L features a programmable decimation rate divider
that allows users flexibility in matching the AD73360L’s ADC
sample rates to the needs of the DSP software. The maximum
sample rate available is DMCLK/256 and the other available
rates are: DMCLK/512, DMCLK/1024, and DMCLK/2048. The
slowest rate (DMCLK/2048) is the default sample rate. The
sample rate divider is programmable by setting bits CRB:0-1.
Table XV shows the sample rate corresponding to the various
bit settings.
Table XV.Decimation Rate Divider Settings
OPERATION
General DescriptionThe AD73360L inputs and outputs data in a Time Division
Multiplexing (TDM) format. When data is being read from the
AD73360L each channel has a fixed time slot in which its data
is transmitted. If a channel is not powered up, no data is trans-
mitted during the allocated time slot and the SDO line will be
three-stated. When the AD73360L is first powered up or reset it
will be set to Program Mode and will output an SDOFS. After a
reset the SDOFS will be asserted once every sample period
(125 µs assuming 16.384 MHz master clock). If the AD73360L
is configured in Frame Sync Loop-Back Mode, one control
word can be transmitted after each SDOFS pulse. Figure 10a
shows the SDO and SDOFS lines after a reset. The serial data
sent by SDO will not contain valid ADC data until the AD73360L
is put into Data Mode or Mixed Mode. Control Registers D
through F allow channels to be powered up individually. This
gives greater flexibility and control over power consumption.
Figure 10b shows the SDOFS and SDO of the AD73360L when
all channels are powered up and Figure 10c shows SDOFS and
SDO with Channels 1, 3, and 5 powered up.
Resetting the AD73360LThe RESET pin resets all the control registers. All registers are
reset to zero, indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the RESET pin, the
device can be reset using the RESET bit (CRA:7) in Control
Register A. Both hardware and software resets require four
DMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0
(default condition) thus enabling Program Mode. The reset
conditions ensure that the device must be programmed to the
correct settings after power-up or reset. Following a reset, the
SDOFS will be asserted approximately 2070 master (MCLK)
cycles after RESET goes high. The data that is output following
the reset and during Program Mode is random and contains no
valid information until either data or mixed mode is set.
Power ManagementThe individual functional blocks of the AD73360L can be enabled
separately by programming the power control register CRC. It
allows certain sections to be powered down if not required, which
adds to the device’s flexibility in that the user need not incur the
penalty of having to provide power for a certain section if it is
not necessary to their design. The power control registers provide
individual control settings for the major functional blocks on
each analog front-end unit and also a global override that allows
all sections to be powered up/down by setting/clearing the bit.
Using this method the user could, for example, individually
enable a certain section, such as the reference (CRC:5), and
disable all others. The global power-up (CRC:0) can be used to
enable all sections but if power-down is required using the global
Figure 10a. Output Timing After Reset (Program Mode)
Figure 10b.Output Timing: All Channels Powered Up (Data/Mixed Mode)
