AD73360AR ,Six-Input Channel Analog Front EndSPECIFICATIONS2, 3Maximum Input Range at VIN 1.644 V p-p 5VEN = 0, Measured Differentially–2.85 dBm ..
AD73360ASU ,Six-Input Channel Analog Front Endapplications including industrial powerFUNCTIONAL BLOCK DIAGRAMVINP1ANALOGSIGNAL0/38dB- DECIMATOR ..
AD73360LAR ,Six-Input Channel Analog Front EndSPECIFICATIONS2, 3Maximum Input Range at VIN 1.578 V p-p Measured Differentially–2.85 dBmNominal Re ..
AD73360LAR-REEL ,Six-Input Channel Analog Front EndSPECIFICATIONS2, 3Maximum Input Range at VIN 1.578 V p-p Measured Differentially–2.85 dBmNominal Re ..
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AD73360AR-AD73360ASU
Six-Input Channel Analog Front End
REV. A
Six-Input Channel
Analog Front End
FEATURES
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
77 dB SNR
64 kS/s Maximum Sample Rate
–83 dB Crosstalk
Low Group Delay (25�s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port which Allows Multiple Devices to
Be Connected in Cascade
Single (+2.7V to +5.5V) Supply OperationmW Max Power Consumption at +2.7V
On-Chip Reference
28-Lead SOIC and 44-Lead TQFP Packages
APPLICATIONS
General Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD73360 is a six-input channel analog front-end processor
for general purpose applications including industrial power
metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels each of which provide 77dB signal-to-
noise ratio over a dc to 4kHz signal bandwidth. Each channel
also features a programmable input gain amplifier (PGA) with
gain settings in eight stages from 0 dB to 38 dB.
The AD73360 is particularly suitable for industrial power me-
tering as each channel samples synchronously, ensuring that there
is no (phase) delay between the conversions. The AD73360 also
features low group delay conversions on all channels.
An on-chip reference voltage is included and is programmable
to accommodate either 3 V or 5 V operation.
The sampling rate of the device is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73360 is available in 28-lead SOIC and 44-lead TQFP
packages.
AD73360–SPECIFICATIONS1(AVDD = 3V � 10%; DVDD = 3V � 10%; DGND = AGND = 0V, fMCLK = 16.384 MHz,
fSCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)ADC SPECIFICATIONS
AD73360NOTESOperating temperature range is as follows:–40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.Test conditions:Input PGA set for 0dB gain (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38dB preamplifier
bypassed and input gain of 0 dB.Test Conditions:no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table I.Current Summary (AVDD = DVDD = 3.3V)The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
AD73360–SPECIFICATIONS1(AVDD = 5V � 10%; DVDD = 5V � 10%; DGND = AGND = 0V, fMCLK = 16.384 MHz,
fSCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)ADC SPECIFICATIONS
AD73360NOTESOperating temperature range is as follows:–40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.Test conditions:Input PGA set for 0dB gain (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38dB preamplifier
bypassed and input gain of 0 dB.Test Conditions:no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table II.Current Summary (AVDD = DVDD = 5.5V)The above values are in mA and are typical values unless otherwise noted.
Table III.Signal Ranges
AD73360
TIMING CHARACTERISTICS
(AVDD = 3 V � 10%; DVDD = 3 V � 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise
noted)
TIMING CHARACTERISTICS
(AVDD = 5 V � 10%; DVDD = 5 V � 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise
noted)
Figure 1.MCLK Timing
Figure 2.Load Circuit for Timing Specifications
Figure 3.SCLK Timing
Figure 4.Serial Port (SPORT)
VIN – dBm0
S/(N+D) – dB
3.17Figure 5a.S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
Figure 5b.S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
AD73360
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . .. –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +150°C
SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
ORDERING GUIDENOTESR = 0.3' Small Outline IC (SOIC); SU = Thin Quad Flatpack IC (TQFP).The AD73360 evaluation board can be interfaced to an ADSP-2181 EZ-KIT Lite
or to a Texas Instruments EVM kit.The upgrade consists of a connector for the expansion port P3 of the EZ-KIT
Lite. This option is intended for existing owners of EZ-KIT Lite.The EZ-KIT Lite has been modified to allow it to interface with the AD73360
evaluation board. This option is intended for users who do not already have an
EZ-KIT Lite.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73360 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
R-28 SU-44
VINN5
VINP5
VINN6
VINP6
REFOUT
REFCAP
AVDD2
AVDD2
AGND2
AGND2
AGND2
NC = NO CONNECT
AGND2
DGND
DGND
DVDD
AVDD1
SDI
AVDD1
SDIFS
AGND1
AGND1VINN1
RESETB
VINN2VINP3VINN4VINP4NCVINP2
SCLK
MCLK
SDO
VINP1
SDOFS
VINN3
PIN FUNCTION DESCRIPTIONMCLK
SDO
SDOFS
SDIFS
SDI
AGND1
AD73360
TERMINOLOGY
Absolute GainAbsolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0dBm0 for each ADC. The absolute gain specification
is used for gain tracking error specification.
CrosstalkCrosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking ErrorGain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB by
definition.
Group DelayGroup Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the de-
gree of nonlinear phase response of the system.
Idle Channel NoiseIdle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 0Hz–4 kHz).
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply RejectionPower supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample RateThe sample rate is the rate at which each ADC updates its out-
put register. It is set relative to the DMCLK and the program-
mable sample rate setting.
SNR + THDSignal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in a given frequency
range, including harmonics but excluding dc.
ABBREVIATIONSADCAnalog-to-Digital Converter.Bandwidth.
CRxA Control Register where x is a placeholder for
an alphabetic character (A–E). There are eight
read/write control registers on the AD73360—
designated CRA through CRE.
CRx:nA bit position, where n is a placeholder for a
numeric character (0–7), within a control regis-
ter; where x is a placeholder for an alphabetic
character (A–E). Position 7 represents the MSB
and Position 0 represents the LSB.
DMCLKDevice (Internal) Master Clock. This is the
internal master clock resulting from the external
master clock (MCLK) being divided by the on-
chip master clock divider.
FSLBFrame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of nonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.
PGAProgrammable Gain Amplifier.Switched Capacitor.
SNRSignal-to-Noise Ratio.
SPORTSerial Port.
THDTotal Harmonic Distortion.
VBWVoice Bandwidth.
FUNCTIONAL DESCRIPTION
General DescriptionThe AD73360 is a six-channel, 16-bit, analog front end. It
comprises six independent encoder channels each featuring
signal conditioning, programmable gain amplifier, sigma-delta
A/D convertor and decimator sections. Each of these sections is
described in further detail below.
Encoder ChannelEach encoder channel consists of a signal conditioner, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input
antialias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Signal ConditionerEach analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
Programmable Gain AmplifierEach encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modula-
tor. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 in control
Registers D, E and F.
Table IV.PGA Settings for the Encoder Channel
ADCEach channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and in-
creases the resolution.
Analog Sigma-Delta ModulatorThe AD73360 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73360, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to fS/2 = DMCLK/16
(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 6c).
Figure 6.Sigma-Delta Noise Reduction
AD73360Figure 7 shows the various stages of filtering that are employed
in a typical AD73360 application. In Figure 7a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling fre-
quency. This also shows the major difference between the initial
oversampling rate and the bandwidth of interest. In Figure 7b,
the signal and noise-shaping responses of the sigma-delta modu-
lator are shown. The signal response provides further rejection
of any high frequency signals while the noise-shaping will push
the inherent quantization noise to an out-of-band position. The
detail of Figure 7c shows the response of the digital decima-
tion filter (Sinc-cubed response) with nulls every multiple of
DMCLK/256, which is the decimation filter update rate. The
final detail in Figure 7d shows the application of a final antialias
filter in the DSP engine. This has the advantage of being imple-
mented according to the user’s requirements and available
MIPS. The filtering in Figures 7a through 7c is implemented in
the AD73360.
FB = 4kHzFSINIT = DMCLK/8Analog Antialias Filter Transfer Function
FB = 4kHzFSINIT = DMCLK/8Analog Sigma-Delta Modulator Transfer FunctionDigital Decimator Transfer Function
Decimation FilterThe digital filter used in the AD73360 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator and secondly, it deci-
mates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/
256, and increases the resolution from a single bit to 15 bits. Its
Z transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a mini-
mal group delay of 25 µs.
ADC CodingThe ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale, however, the output word is set
at 0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
Figure 8.ADC Transfer Function
Voltage ReferenceThe AD73360 reference, REFCAP, is a bandgap reference that
provides a low noise, temperature-compensated reference to the
ADC. A buffered version of the reference is also made available
on the REFOUT pin and can be used to bias other external
analog circuitry. The reference has a default nominal value of
1.25V but can be set to a nominal value of 2.5V by setting the
5VEN bit (CRC:7) of CRC. The 5V mode is generally only
usable when VDD = 5V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Serial Port (SPORT)The AD73360s communicate with a host processor via the
bidirectional synchronous serial port (SPORT) which is compat-
ible with most modern DSPs. The SPORT is used to transmit
and receive digital data and control information. Multiple
AD73360s be cascaded together (up to a limit of eight) to pro-
vide additional input channels.
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT of each AD73360 block uses a
common serial register for serial input and output, communica-
tions between an AD73360 and a host processor (DSP engine)
must always be initiated by the AD73360s themselves. In this
configuration the AD73360s are described as being in Master
mode. This ensures that there is no collision between input data
and output samples.
SPORT OverviewThe AD73360 SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to
eight AD73360 devices to be connected in cascade, to a single
DSP via a six-wire interface. It has a very flexible architecture
that can be configured by programming two of the internal
control registers in each device. The AD73360 SPORT has
three distinct modes of operation: Control Mode, Data Mode
and Mixed Control/Data Mode.
NOTE: As each AD73360 has its own SPORT section, the
register settings in both SPORTs must be programmed. The
registers which control SPORT and sample rate operation (CRA
and CRB) must be programmed with the same values, otherwise
incorrect operation may occur.
In Program Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the AD73360. In Data Mode (CRA:0 = 1), any infor-
mation that is sent to the device is ignored, while the encoder
section (ADC) data is read from the device. In this mode, only
ADC data is read from the device. Mixed mode (CRA:0 = 1
and CRA:1 = 1) allows the user to send control information and
receive either control information or ADC data. This is achieved
by using the MSB of the 16-bit frame as a flag bit. Mixed mode
reduces the resolution to 15 bits with the MSB being used to
indicate whether the information in the 16-bit frame is control
information or ADC data.
The SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and out-
put data must share the same register there are some precau-
tions that must be observed. The primary precaution is that no
information must be written to the SPORT without reference to
an output sample event, which is when the serial register will be
overwritten with the latest ADC sample word. Once the SPORT
starts to output the latest ADC word, it is safe for the DSP to
write new control words to the AD73360. In certain configura-
tions, data can be written to the device to coincide with the
output sample being shifted out of the serial register—see section
on interfacing devices. The serial clock rate (CRB:2–3) defines
how many 16-bit words can be written to a device before the
next output sample event will happen.
The SPORT block diagram, shown in Figure 9, details the blocks
associated with AD73360 including the eight control registers
(A–H), external MCLK to internal DMCLK divider and serial
clock divider. The divider rates are controlled by the setting of
Control Register B. The AD73360 features a master clock
divider that allows users the flexibility of dividing externally
available high frequency DSP or CPU clocks to generate a lower
frequency master clock internally in the AD73360 which may be
more suitable for either serial transfer or sampling rate require-
ments. The master clock divider has five divider options (÷1
default condition, ÷2, ÷3, ÷4, ÷5) that are set by loading the
master clock divider field in Register B with the appropriate
code (see Table VI). Once the internal device master clock
(DMCLK) has been set using the master clock divider, the
sample rate and serial clock settings are derived from DMCLK.
Figure 9.SPORT Block Diagram
The SPORT can work at four different serial clock (SCLK)
rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or
DMCLK/8, where DMCLK is the internal or device master
clock resulting from the external or pin master clock being di-
vided by the master clock divider. Care should be taken when
selecting Master Clock, Serial Clock and Sample Rate divider
settings to ensure that there is sufficient time to read all the data
from the AD73360 before the next sample interval.
AD73360
SPORT Register MapsThere are eight control registers for the AD73360, each eight
bits wide. Table V shows the control register map for the
AD73360. The first two control registers, CRA and CRB, are
reserved for controlling the SPORT. They hold settings for
parameters such as bit rate, internal master clock rate and de-
vice count. If multiple AD73360s are cascaded, registers CRA
and CRB on each device must be programmed with the same
setting to ensure correct operation (this is shown in the pro-
gramming examples). The other six registers; CRC through
CRH are used to hold control settings for the Reference, Power
Control, ADC channel and PGA sections of the device. It is
not necessary that the contents of CRC through CRH on
each AD73360 are similar. Control registers are written to on
the negative edge of SCLK.
Table V.Control Register Map
Table VII.Control Register A Description
Table VIII.Control Register B Description
Table IX.Control Register C Description
CONTROL REGISTER A
CONTROL REGISTER B
CONTROL REGISTER C
AD73360
Table X.Control Register D Description
Table XI.Control Register E Description
Table XII.Control Register F Description
CONTROL REGISTER D
CONTROL REGISTER E
CONTROL REGISTER F
Table XIII.Control Register G Description
Table XIV.Control Register H Description
CONTROL REGISTER G
CONTROL REGISTER H
REGISTER BIT DESCRIPTIONS
Control Register ACRA:0Data/Program Mode. This bit controls the operating mode of the AD73360. If CRA:1 is 0, then a 0 in this bit
places the part in Program Mode. If CRA:1 is 0, then a 1 in this bit places the part in Data Mode.
CRA:1Mixed Mode. If this bit is a 0, then the operating mode is determined by CRA:0. If this bit is a 1, then the
part operates in Mixed Mode.
CRA:2Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.
CRA:3SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation.
CRA:4–6Device Count Bits. These bits tell the AD73360 how many devices are used in a cascade. All devices in the
cascade should be programmed to the same value ensure correct operation. See Table XVIII.
CRA:7Reset. Writing a 1 to this bit will initiate a software reset of the AD73360.
Control Register BCRB:0–1Decimation Rate. These bits are used to set the decimation of the AD73360. See Table VII.
CRB:2–3Serial Clock Divider. These bits are used to set the serial clock frequency. See Table VI.
CRB:4–6Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table V.
CRB:7Control Echo Enable. Setting this bit to a 1 will cause the AD73360 to write out any control words it receives.
This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode.
AD73360
Control Register CCRC:0Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360 to power-up regardless of the
status of the Power Control Bits in CRD-CRF. If less than six channels are required, this bit should be set to 0 and
the Power Control Bits of the relevant channels should be set to 1.
CRC:1–4Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation.
CRC:5Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the refer-
ence. A 0 in this bit will power-down the reference. Note that the reference is automatically powered up if any
channel is enabled.
CRC:6Reference Output. When this bit is set to 1, the REFOUT pin is enabled.
CRC:75 V Enable. When this bit is set to 1, the 5 V operating mode is enabled.
Control Register DCRD:0–2Input Gain Selection. These bits select the input gain for ADC1. See Table IV.
CRD:3Power Control for ADC1. A 1 in this bit powers up ADC1.
CRD:4–6Input Gain Selection. These bits select the input gain for ADC2. See Table IV.
CRD:7Power Control for ADC2. A 1 in this bit powers up ADC2.
Control Register ECRE:0-2Input Gain Selection. These bits select the input gain for ADC3. See Table IV.
CRE:3Power Control for ADC3. A 1 in this bit powers up ADC3.
CRE:4–6Input Gain Selection. These bits select the input gain for ADC4. See Table IV.
CRE:7Power Control for ADC4. A 1 in this bit powers up ADC4.
Control Register FCRF:0–2Input Gain Selection. These bits select the input gain for ADC5. See Table IV.
CRF:3Power Control for ADC5. A 1 in this bit powers up ADC5.
CRF:4–6Input Gain Selection. These bits select the input gain for ADC6. See Table IV.
CRF:7Power Control for ADC6. A 1 in this bit powers up ADC6.
Control Register GCRG:0–5Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit
(CRG:6) is 1, then a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the
Single-Ended Enable Mode bit (CRG:7) is 1, then a 1 in a Channel Select bit location will put that channel into
Single-Ended Mode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-
Ended Mode and will not have its analog modulator reset regardless of the state of CRG:6 and CRG:7.
CRG:6Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose Channel
Select bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation.
CRG:7Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose Channel
Select bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels.
Control Register HCRH:0–5Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1,
then a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel
Select bit set to 0, the channel will not be inverted regardless of the state CRH:7.
CRH:6Test Mode Enable. This bit should be set to 0 to ensure normal operation.
CRH:7Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit
(CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels.
