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AD73322LAR ,Low Cost, Low Power CMOS General-Purpose Dual Analog Front EndFEATURESFUNCTIONAL BLOCK DIAGRAMTwo 16-Bit A/D ConvertersAVDD1 AVDD2Two 16-Bit D/A Converters DVDDP ..
AD73322LAST ,Low Cost, Low Power CMOS General-Purpose Dual Analog Front Endfeatures anseparate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHzinput-to-output gain network ..
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ADE5566ASTZF62 , Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver
AD73322AR-AD73322AST
Low Cost, Low Power CMOS General-Purpose Dual Analog Front End
REV.B
Low Cost, Low Power CMOS
General-Purpose Dual Analog Front End
FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25ms Typ per ADC Channel,
50 ms Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual
Codecs to be Connected in Cascade Giving Eight
I/O Channels
Single (+2.7V to +5.5V) Supply OperationmW Typ Power Consumption at 3.0V
On-Chip Reference
28-Lead SOIC and 44-Lead LQFP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe AD73322 is a dual front-end processor for general-purpose
applications including speech and telephony. It features two
16-bit A/D conversion channels and two 16-bit D/A conversion
channels. Each channel provides 77␣dB signal-to-noise ratio
over a voiceband signal bandwidth. It also features an input-to-
output gain network in both the analog and digital domains.
This is featured on both codecs and can be used for impedance
matching or scaling when interfacing to Subscriber Line Inter-
face Circuits (SLICs).
The AD73322 is particularly suitable for a variety of applica-
tions in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition, and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.
The A/D and D/A conversion channels feature programmable
input/output gains with ranges of 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single-supply
operation. This reference is programmable to accommodate
either 3 V or 5 V operation.
The sampling rate of the codecs is programmable with four
separate settings, offering 64 kHz, 32 kHz, 16 kHz and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73322 is available in 28-lead SOIC and 44-lead LQFP
packages.
REFCAP
SDOFS
AVDD1AVDD2DVDD
REFOUT
VFBP1
VINP1
VINN1
VFBN1
VOUTP1
VOUTN1
VFBP2
VINP2
VINN2
VFBN2
VOUTP2
VOUTN2
AGND1AGND2DGND
SDO
MCLK
RESET
SCLK
SDIFS
SDI
AD73322
AD73322–SPECIFICATIONS1
(AVDD = +3V 6 10%; DVDD = +3V 6 10%; DGND = AGND = 0V, fDMCLK =
16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
AD73322FREQUENCY RESPONSE
AD73322
Table I.Current Summary (AVDD = DVDD = +3.3V)The above values are in mA and are typical values unless otherwise noted.
NOTESOperating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.Test conditions:Input PGA set for 0dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 · 1011)/DMCLK.Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.At VOUT output.Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38dB pream-
plifier bypassed and input gain of 0 dB.Test Conditions:no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
AD73322
SPECIFICATIONS1
(AVDD = +5V 6 10%; DVDD = +5V 6 10%; DGND = AGND = 0 V, fDMCLK = 16.384 MHz, fSAMP = 64 kHz;
TA = TMIN to TMAX, unless otherwise noted)
AD73322
AD73322NOTESOperating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.Test conditions: Input PGA set for 0dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise stated).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 · 1011)/DMCLK.Between VOUTP and VOUTN.At VOUT output.Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB
preamplifier bypassed and input gain of 0 dB.Test conditions: no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table II.Current Summary (AVDD = DVDD = +5.5V)The above values are in mA and are typical values unless otherwise noted.
AD73322
Table III.Signal Ranges
TIMING CHARACTERISTICSSpecifications subject to change without notice.
(AVDD = +3 V 6 10%; DVDD = +3 V 6 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)
TIMING CHARACTERISTICSSerial Port
Specifications subject to change without notice.
(AVDD = +5 V 6 10%; DVDD = +5 V 6 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted)Figure 1.MCLK Timing
Figure 3.SCLK Timing
Figure 2.Load Circuit for Timing Specifications
AD73322
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . .. –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature RangeIndustrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
SOIC, qJA Thermal Impedance . . . . . . . . . . . . . . . 71.4°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
LQFP, qJA Thermal Impedance . . . . . . . . . . . . . . . 53.2°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDENOTESThe AD73322 evaluation board features a selectable number of codecs in
cascade (from 1 to 4). It can be interfaced to an ADSP-2181 EZ-KIT Lite or to
a Texas Instruments EVM kit.The upgrade consists of a connector that is used to connect the EZ-KIT to the
AD73322 evaluation board. This option is intended for owners of the EZ-KIT
Lite.The EZ-KIT Lite has been modified to allow it to interface with the AD73322
evaluation board. This option is intended for users who do not already have an
EZ-KIT Lite.
PIN CONFIGURATIONS
28-Lead Wide Body SOIC
(R-28)
SDO
MCLK
SCLK
RESET
DVDD
DGND
AGND2
VINP1
VFBP1
VINN1
VFBN1
AVDD2
REFCAP
REFOUT
SDOFS
SDIFS
SDI
AGND1
AVDD1
VOUTP2
VFBN2
VINN2
VFBP2
VINP2
VOUTN2
VOUTP1
VOUTN1
44-Lead Plastic Thin Quad Flatpack (LQFP)
(ST-44A)
VOUTN1
VOUTP1
VOUTN2
VOUTP2
REFOUT
REFCAP
AVDD2
AVDD2
AGND2
AGND2
AGND2
NC = NO CONNECT
AGND2
DGND
DGND
DVDD
AVDD1
SDINC
AVDD1
SDIFS
AGND1
AGND1VFBN1
RESET
VFBP1VINN2VFBP2VINP2NCVINP1
SCLK
MCLK
SDO
VINN1
SDOFS
VFBN2
PIN FUNCTION DESCRIPTIONS
AD73322
TERMINOLOGY
Absolute GainAbsolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine
wave at 0 dBm0 for the DAC and with a 1 kHz sine wave atdBm0 for the ADC. The absolute gain specification is used for
gain tracking error specification.
CrosstalkCrosstalk is due to coupling of signals from a given channel to
an adjacent channel. It is defined as the ratio of the amplitude of
the coupled signal to the amplitude of the input signal. Crosstalk
is expressed in dB.
Gain Tracking ErrorGain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group DelayGroup Delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the
degree of nonlinear phase response of the system.
Idle Channel NoiseIdle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (mea-
sured in the frequency range 300Hz–3400 Hz).
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa – nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n is equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply RejectionPower supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample RateThe sample rate is the rate at which the ADC updates its output
register and the DAC updates its output from its input register.
The sample rate can be chosen from a list of four that are fixed
relative to the DMCLK. Sample rate is set by programming bits
DIR0-1 in Control Register B of each channel.
SNR+THDSignal-to-noise ratio plus total harmonic distortion is defined to
be the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONSADCAnalog-to-Digital Converter.
AFEAnalog Front End.
AGTAnalog Gain Tap.
ALBAnalog Loop-Back.Bandwidth.
CRxA Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73322—desig-
nated CRA through CRE.
CRx:nA bit position, where n is a placeholder for a nu-
meric character (0–7), within a control register,
where x is a placeholder for an alphabetic charac-
ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DACDigital-to-Analog Converter.
DGTDigital Gain Tap.
DLBDigital Loop-Back.
DMCLKDevice (Internal) Master Clock. This is the inter-
nal master clock resulting from the external master
clock (MCLK) being divided by the on-chip mas-
ter clock divider.Full Scale.
FSLBFrame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of
first device in the cascade. Data input and out-
put occur simultaneously. In the case of Non-
FSLB, SDOFS and SDO are connected to the
Rx Port of the DSP while SDIFS and SDI are
connected to the Tx Port.
PGAProgrammable Gain Amplifier.Switched Capacitor.
SLBSport Loop-Back
SNRSignal-to-Noise Ratio.
SPORTSerial Port.
THDTotal Harmonic Distortion.
VBWVoice Bandwidth.
VIN – dBm0
S/(N+D) – dB
3.17 Figure 5.S/(N+D) vs. VIN (ADC @ 3V) over Voiceband
Bandwidth (300 Hz–3.4kHz)
VIN – dBm0
S/(N+D) – dB
3.17 Figure 6.S/(N+D) vs. VIN (DAC @ 3V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
VIN – dBm0
S/(N+D) – dB
3.17 Figure 7.S/(N+D) vs. VIN (ADC @ 5 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
VIN – dBm0
S/(N+D) – dB
3.17 Figure 8.S/(N+D) vs. VIN (DAC @ 5 V) over Voiceband
Bandwidth (300 Hz–3.4 kHz)
Typical Performance Characteristics
AD73322
VFBN1
VINN1
VINP1
VFBP1
VOUTP1
VOUTN1
REFCAP
REFOUT
VFBN2
VINN2
VINP2
VFBP2
VOUTP2
VOUTN2
AGND1AGND2DGND
SDOFS
SDO
MCLK
RESET
SCLK
SDIFS
SDI
DVDDAVDD2AVDD1Figure 9.Functional Block Diagram
FUNCTIONAL DESCRIPTION
Encoder ChannelsBoth encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part of
the sigma-delta ADC, also performs critical system-level filter-
ing. Due to the high level of oversampling, the input antialias
requirements are reduced such that a simple single pole RC
stage is sufficient to give adequate attenuation in the band of
interest.
Programmable Gain AmplifierEach encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta modu-
lator. The SC sampling frequency is DMCLK/8. The PGA,
whose programmable gain settings are shown in Table IV, may
be used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in control register D.
Table IV.PGA Settings for the Encoder Channel
ADCBoth ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decimation
filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta ModulatorThe AD73322’s input channels employ a sigma-delta conver-
sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73322, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to FS/2 = DMCLK/16
(Figure 10a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 10b). The combi-
nation of these techniques, followed by the application of a
digital filter, sufficiently reduces the noise in band to ensure
good dynamic performance from the part (Figure 10c).
BAND
INTEREST
FS/2
DMCLK/16
FS/2
DMCLK/16
FS/2
DMCLK/16
BAND
INTEREST
BAND
INTERESTFigure 10.Sigma-Delta Noise Reduction
Figure 11 shows the various stages of filtering that are employed
in a typical AD73322 application. In Figure 11a we see the
transfer function of the external analog antialias filter. Even
far away from the initial sampling frequency (DMCLK/8) that it
takes care of any signals that could be aliased by the sampling
frequency. This also shows the major difference between the
initial oversampling rate and the bandwidth of interest. In Fig-
ure 11b, the signal and noise-shaping responses of the sigma-
delta modulator are shown. The signal response provides further
rejection of any high frequency signals while the noise-shaping
will push the inherent quantization noise to an out-of-band
position. The detail of Figure 11c shows the response of the
digital decimation filter (Sinc-cubed response) with nulls every
multiple of DMCLK/256, which corresponds to the decimation
filter update rate for a 64kHz sampling. The nulls of the Sinc3
response correspond with multiples of the chosen sampling
frequency. The final detail in Figure 11d shows the application
of a final antialias filter in the DSP engine. This has the advan-
tage of being implemented according to the user’s requirements
and available MIPS. The filtering in Figures 11a through 11c is
implemented in the AD73322.
FB = 4kHzFSINIT = DMCLK/8Analog Antialias Filter Transfer Function
FB = 4kHzFSINIT = DMCLK/8
NOISE TRANSFER FUNCTION
SIGNAL TRANSFER FUNCTIONAnalog Sigma-Delta Modulator Transfer FunctionDigital Decimator Transfer FunctionFinal Filter LPF (HPF) Transfer Function
AD73322
Decimation FilterThe digital filter used in the AD73322 carries out two important
functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high frequency bit-stream to a lower rate 16-bit
word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits or greater
(depending on chosen sampling rate). Its Z transform is given
as:
[(1 – Z –N)/(1 – Z –1)]3
where N is set by the sampling rate (N = 32 @ 64 kHz sampling
. . . N = 256 @ 8 kHz sampling). Thus when the sampling rate
is 64kHz, a minimal group delay of 25 ms can be achieved.
Word growth in the decimator is determined by the sampling
rate. At 64kHz sampling, where the oversampling ratio between
sigma-delta modulator and decimator output equals 32, there
are five bits per stage of the three-stage Sinc3 filter. Due to
symmetry within the sigma-delta modulator, the LSB will al-
ways be a zero; therefore, the 16-bit ADC output word will have
2 LSBs equal to zero, one due to the sigma-delta symmetry and
the other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth will be greater
than the 16-bit sample word, therefore truncation occurs in
transferring the decimator output as the ADC word. For example,
at 8 kHz sampling, word growth reaches 24 bits due to the OSR
of 256 between sigma-delta modulator and decimator output.
This yields eight bits per stage of the three-stage Sinc3 filter.
ADC CodingThe ADC coding scheme is in twos complement format (see
Figure 12). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a word length of up to 24 bits
(depending on decimation rate chosen), which is the final out-
put of the ADC block. In Data Mode this value is truncated to
16 bits for output on the Serial Data Output (SDO) pin.
VREF + (VREF 3 0.32875)
VREF
VREF – (VREF 3 0.32875)
ADC CODE DIFFERENTIAL
ANALOG
INPUT
VREF + (VREF 3 0.6575)
VREF – (VREF 3 0.6575)
ANALOG
INPUTIn mixed Control/Data Mode, the resolution is fixed at 15 bits,
with the MSB of the 16-bit transfer being used as a flag bit to
indicate either control or data in the frame.
Decoder ChannelThe decoder channels consist of digital interpolators, digital
sigma-delta modulators, single-bit digital-to-analog converters
(DAC), analog smoothing filters and programmable gain ampli-
fiers with differential outputs.
DAC CodingThe DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation FilterThe anti-imaging interpolation filter is a sinc-cubed digital filter
that up-samples the 16-bit input words from the input sample
rate to a rate of DMCLK/8, while filtering to attenuate images
produced by the interpolation process. Its Z transform is given as:
[(1 – Z –N)/(1 – Z –1)]3
where N is determined by the sampling rate (N = 32 @kHz . . . N = 256 @ 8kHz). The DAC receives 16-bit
samples from the host DSP processor at the programmed
sample rate of DMCLK/N. If the host processor fails to write a
new value to the serial port, the existing (previous) data is read
again. The data stream is filtered by the anti-imaging interpola-
tion filter, but there is an option to bypass the interpolator for
the minimum group delay configuration by setting the IBYP bit
(CRE:5) of Control register E. The interpolation filter has the
same characteristics as the ADC’s antialiasing decimation filter.
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized in
the passband of the converter. The bit-stream output of the
sigma-delta modulator is fed to the single-bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGAThe output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB todB in 3 dB steps, as shown in Table V. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
Table V.PGA Settings for the Decoder Channel
Differential Output AmplifiersThe decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal is
dc-biased to the codec’s on-chip voltage reference.
Voltage ReferenceThe AD73322 reference, REFCAP, is a bandgap reference that
provides a low noise, temperature-compensated reference to the
DAC and ADC. A buffered version of the reference is also made
available on the REFOUT pin and can be used to bias other
external analog circuitry. The reference has a default nominal
value of 1.2V, but can be set to a nominal value of 2.4V by
setting the 5VEN bit (CRC:7) of CRC. The 5V mode is gener-
ally only usable when AVDD = 5V.
Figure 13.Analog Input/Output Section
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Analog and Digital Gain TapsThe AD73322 features analog and digital feedback paths be-
tween input and output. The amount of feedback is determined
by the gain setting which is programmed in the control registers.
This feature can typically be used for balancing the effective
impedance between input and output when used in Subscriber
Line Interface Circuit (SLIC) interfacing.
Analog Gain TapThe analog gain tap is configured as a programmable differential
amplifier whose input is taken from the ADC’s input signal path.
The output of the analog gain tap is summed with the output of
the DAC. The gain is programmable using Control Register F
(CRF:0-4) to achieve a gain of –1 to +1 in 32 steps with muting
being achieved through a separate control setting (Control Regis-
ter F Bit 7). The gain increment per step is 0.0625. The AGT is
enabled by powering-up the AGT control bit in the power con-
trol register (CRC:1). When this bit is set (=1) CRF becomes an
AGT control register with CRF:0-4 holding the AGT coeffi-
cient, CRF:5 becomes an AGT enable and CRF:7 becomes an
AGT mute control bit. Control bit CRF:5 connects/disconnects
the AGT output to the summer block at the output of the DAC
section while control bit CRF:7 overrides the gain tap setting
with a mute, (zero gain) setting. Table VI shows the gain versus
digital setting for the AGT.
AD73322
Table VI.Analog Gain Tap Settings**AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Digital Gain TapThe digital gain tap features a programmable gain block whose
input is taken from the bitstream output of the ADC’s sigma-
delta modulator. This single bit input (1 or 0) is used to add or
subtract a programmable value, which is the digital gain tap setting,
to the output of the DAC section’s interpolator. The program-
mable setting has 16-bit resolution and is programmed using the
settings in Control Registers G and H. (See Table VII).
Table VII.Digital Gain Tap Settings*
DGT15–0 (Hex)0x8000
0x9000
0xA000
0xC000
0xE000
0x0000
0x2000
0x4000
0x6000
0x7FFF
*AGT and DGT weights are given for the case of VFBNx (connected to the
sigma-delta modulator’s positive input) being at a higher potential than VFBPx
(connected to the sigma-delta modulator’s negative input).
Serial Port (SPORT)The codecs communicate with a host processor via the bidirec-
tional synchronous serial port (SPORT), which is compatible
with most modern DSPs. The SPORT is used to transmit and
receive digital data and control information. The dual codec is
implemented using two separate codec blocks that are internally
cascaded with serial port access to the input of Codec1 and the
output of Codec2. This allows other single or dual codec de-
vices to be cascaded together (up to a limit of eight codec units).
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT of each codec block uses a com-
mon serial register for serial input and output, communications
between an AD73322 codec and a host processor (DSP engine)
SPORT OverviewThe AD73322 SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to four
AD73322 devices (or combinations of AD73322 dual codecs
and AD73311 single codecs up to eight codec blocks) to be con-
nected, in cascade, to a single DSP via a six-wire interface. It has a
very flexible architecture that can be configured by programming
two of the internal control registers in each codec block. The
AD73322 SPORT has three distinct modes of operation: Control
Mode, Data Mode and Mixed Control/Data Mode.
NOTE: As each codec has its own SPORT section, the register
settings in both SPORTs must be programmed. The registers
that control SPORT and sample rate operation (CRA and CRB)
must be programmed with the same values, otherwise incorrect
operation may occur.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), (CRA:1 = 0),
information sent to the device is used to update the decoder
section (DAC), while the encoder section (ADC) data is read
from the device. In this mode, only DAC and ADC data is
written to or read from the device. Mixed mode (CRA:0 = 1
and CRA:1 = 1) allows the user to choose whether the informa-
tion being sent to the device contains either control information
or DAC data. This is achieved by using the MSB of the 16-bit
frame as a flag bit. Mixed mode reduces the resolution to 15 bits
with the MSB being used to indicate whether the information in
the 16-bit frame is control information or DAC/ADC data.
The SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and out-
put data must share the same register, some precautions must be
observed. The primary precaution is that no information must
be written to the SPORT without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once the SPORT starts to output
the latest ADC word, it is safe for the DSP to write new control
or data words to the codec. In certain configurations, data can
be written to the device to coincide with the output sample
being shifted out of the serial register—see section on interfac-
ing devices. The serial clock rate (CRB:2–3) defines how many
16-bit words can be written to a device before the next output
sample event will happen.
The SPORT block diagram shown in Figure 14 details the
blocks associated with Codecs 1 and 2, including the eight
control registers (A–H), external MCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73322 features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to gen-
erate a lower frequency master clock internally in the codec,
which may be more suitable for either serial transfer or sampling
rate requirements. The master clock divider has five divider
options (‚1 default condition, ‚2, ‚3, ‚4, ‚5) that are set by
loading the master clock divider field in Register B with the
appropriate code (see Table VIII). Once the internal device master
The SPORT can work at four different serial clock (SCLK)
rates: chosen from DMCLK, DMCLK/2, DMCLK/4 or
DMCLK/8, where DMCLK is the internal or device master
clock resulting from the external or pin master clock being
divided by the master clock divider.
SPORT Register MapsThere are two register banks for each codec in the AD73322:
the control register bank and the data register bank. The con-
trol register bank consists of eight read/write registers, each
eight bits wide. Table XII shows the control register map for
the AD73322. The first two control registers, CRA and CRB,
are reserved for controlling the SPORT. They hold settings for
parameters such as serial clock rate, internal master clock rate,
sample rate and device count. As both codecs are internally
cascaded, registers CRA and CRB on each codec must be pro-
grammed with the same setting to ensure correct operation (this
is shown in the programming examples). The other five regis-
ters; CRC through CRH are used to hold control settings for
the ADC, DAC, Reference, Power Control and Gain Tap
sections of the device. It is not necessary that the contents of
CRC through CRH on each codec be similar. Control regis-
ters are written to on the negative edge of SCLK. The data
register bank consists of two 16-bit registers that are the DAC
and ADC registers.
Master Clock DividerThe AD73322 features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to pro-
duce an internal master clock signal (DMCLK) that is used to
calculate the sampling and serial clock rates. The master clock
divider is programmable by setting CRB:4-6. Table VIII shows
the division ratio corresponding to the various bit settings. The
default divider ratio is divide-by-one.
Table VIII.DMCLK (Internal) Rate Divider Settings
Serial Clock Rate DividerThe AD73322 features a programmable serial clock divider that
allows users to match the serial clock (SCLK) rate of the data to
that of the DSP engine or host processor. The maximum SCLK
rate available is DMCLK and the other available rates are:
DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
is programmable by setting bits CRB:2–3. Table IX shows the
serial clock rate corresponding to the various bit settings.
Table IX.SCLK Rate Divider Settings
Sample Rate DividerThe AD73322 features a programmable sample rate divider that
allows users flexibility in matching the codec’s ADC and DAC
sample rates (decimation/interpolation rates)to the needs of the
DSP software. The maximum sample rate available is DMCLK/
256, which offers the lowest conversion group delay, while the
other available rates are: DMCLK/512, DMCLK/1024 and
DMCLK/2048. The slowest rate (DMCLK/2048) is the default
sample rate. The sample rate divider is programmable by set-
ting bits CRB:0-1. Table X shows the sample rate correspond-
ing to the various bit settings.
Table X.Sample Rate Divider Settings
DAC Advance RegisterThe loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The de-
fault DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(FS · 32); see Table XI. The sample rate
FS is dependent on the setting of both the MCLK divider and
the Sample Rate divider; see Tables VIII and X. In certain cir-
cumstances this DAC update adjustment can reduce the group
delay when the ADC and DAC are used to process data in
series. Appendix C details how the DAC advance feature can be
used.
NOTE: The DAC advance register should not be changed while
the DAC section is powered up.
Table XI.DAC Timing Control
AD73322
Table XII.Control Register Map
Table XIII.Control Word Description
Table XIV.Control Register A Description
CONTROL REGISTER A
Table XV.Control Register B Description
CONTROL REGISTER B
Table XVI.Control Register C Description
CONTROL REGISTER C
AD73322
Table XVII.Control Register D Description
CONTROL REGISTER D
Table XVIII.Control Register E Description
CONTROL REGISTER E
Table XIX.Control Register F Description
CONTROL REGISTER F
