AD73311L ,Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech and TelephonySPECIFICATIONS2, 3Maximum Input Range at VIN 1.578 V p-p Measured Differentially–2.85 dBm Max Input ..
AD73311LAR ,Low Cost, Low Power CMOS General Purpose Analog Front EndAPPLICATIONSThe AD73311L is available in 20-lead SOIC, SSOP andGeneral Purpose Analog I/OTSSOP pack ..
AD73311LARS ,Low Cost, Low Power CMOS General Purpose Analog Front EndSPECIFICATIONS2Maximum Voltage Output SwingSingle-Ended 1.578 V p-p PGA = 6 dB–2.85 dBm Max Output ..
AD73311LARU ,Low Cost, Low Power CMOS General Purpose Analog Front EndSPECIFICATIONS2, 3Maximum Input Range at VIN 1.578 V p-p Measured Differentially–2.85 dBm Max Input ..
AD73311LARUZ , Low Cost, Low Power CMOS General Purpose Analog Front End
AD73311LARUZ , Low Cost, Low Power CMOS General Purpose Analog Front End
ADE3000 ,LCD Display Engines with Integrated DVI, ADC and YUV PortsFunctional Description . . . .132.1 Global Control Block .......132.2 FM Frequency Synthesizer ..
ADE3000SX ,LCD Display Engines with Integrated DVI, ADC and YUV PortsFeatures (Sheet 1 of 2)Feature Description of ADE3XXX Operation Blocks Used PagesPower Up / Initial ..
ADE3000T ,LCD DISPLAY ENGINES WITH INTEGRATED DVI, ADC AND YUV PORTSFeaturesmodes● Flexible data inversion / transition Perfect Picture™ Technologyminimization, single ..
ADE3100 ,LCD Display Engines with Integrated DVI, ADC and YUV PortsfeaturesFeature Overview■ Framelock operation with Safety Mode™■ Programmable Context Sensitive™ Sc ..
ADE3300 ,LCD DISPLAY ENGINES WITH INTEGRATED DVI, ADC AND YUV PORTSfeatures of today’s LCD monitor products. For maximum flexibility, an external microcontroller (MC ..
ADE3700SX ,Analog LCD Display Engine for XGA and SXGA Resolutionsfeaturesgeneration of ADE3xxx Scaling Engines.■ Framelock operation with Safety Mode™■ Serial I²C i ..
AD73311L
Single-Channel, 3 V Front-End Processor for General Purpose Applications Including Speech and Telephony
REV. A
Low Cost, Low Power CMOS
General Purpose Analog Front End
FUNCTIONAL BLOCK DIAGRAM
AGND1AGND2DGND
DVDDAVDD2AVDD1
VINP
VINN
VOUTP
VOUTN
REFCAP
REFOUT
SDI
SDIFS
SCLK
SDO
SDOFS
MCLK
RESET
FEATURES
16-Bit A/D Converter
16-Bit D/A Converter
Programmable Input/Output Sample Rates
76 dB ADC SNR
77 dB DAC SNR
Programmable Sampling Rate
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25ms Typ per ADC Channel,
50 ms Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port Which Allows Up to Eight Devices
to Be Connected in Cascade
Single (+3 V) Supply OperationmW Max Power Consumption at 2.7V
On-Chip Reference
20-Lead SOIC/SSOP/TSSOP Packages
APPLICATIONS
General Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
GENERAL DESCRIPTIONThe AD73311L is a complete front-end processor for general
purpose applications including speech and telephony. It features
a 16-bit A/D conversion channel and a 16-bit D/A conversion
channel. Each channel provides 70dB signal-to-noise ratio over
a voiceband signal bandwidth. The final channel bandwidth can
be reduced, and signal-to-noise ratio improved, by external
digital filtering in a DSP engine.
The AD73311L is suitable for a variety of applications in the
speech and telephony area, including low bit rate, high quality
compression, speech enhancement, recognition and synthesis.
The low group delay characteristic of the part makes it suitable
for single or multichannel active control applications.
The gains of the A/D and D/A conversion channels are program-
mable over 38 dB and 21 dB ranges respectively. An on-chip
reference voltage is included to allow single supply operation.
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines.
The AD73311L is available in 20-lead SOIC, SSOP and
TSSOP packages.
AD73311L–SPECIFICATIONS1(AVDD = DVDD = 2.7V to 3.3 V; DGND = AGND = 0V, fDMCLK = 16.384 MHz,
FS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73311LLOGIC OUTPUT
NOTESOperating temperature range is as follows:–40°C to +105°C. Therefore, TMIN = –40°C and TMAX = +105°C.Test conditions:Input PGA set for 0dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).At input to sigma-delta modulator of ADC.Guaranteed by design.Overall group delay will be affected by the sample rate and the external digital filtering.The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.Between VOUTP and VOUTN.At VOUT output.Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38dB preamplifier
bypassed and input gain of 0 dB.Test Conditions:no load on digital inputs, analog inputs ac coupled to ground, no load on analog outputs.
Specifications subject to change without notice.
Table I.Current Summary (AVDD = DVDD = 3.3V)
AD73311L
Table II.Signal Ranges
TIMING CHARACTERISTICS
(AVDD = DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted)Figure 1.MCLK Timing
Figure 2.Load Circuit for Timing Specifications
Figure 4.Serial Port (SPORT)
Figure 5a.S/(N+D) vs. VIN (ADC @ 3V) over Voiceband
Bandwidth (300 Hz – 3.4kHz)
Figure 5b.S/(N+D) vs. VIN (DAC @ 3V) over Voiceband
Bandwidth (300 Hz – 3.4 kHz)
AD73311L
ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)
AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . .. –0.3 V to (DVDD + 0.3 V)
Analog I/O Voltage to AGND . . . –0.3 V to (AVDD + 0.3 V)
Operating Temperature RangeIndustrial (A Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
SSOP, θJA Thermal Impedance . . . . . . . . . . . . . . . .126°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
TSSOP, θJA Thermal Impedance . . . . . . . . . . . . . . .143°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD73311L features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDENOTESR = 0.3' Small Outline IC (SOIC), RS = Shrink Small Outline Package (SSOP),
RU = Thin Small Shrink Outline Package (TSSOP).The AD73311L evaluation board features a cascade of two codecs interfaced to
an ADSP-2185L DSP. The board features a DSP software monitor which
allows interface to a PC serial port.
PIN FUNCTION DESCRIPTIONS
AD73311L
TERMINOLOGY
Absolute GainAbsolute gain is a measure of converter gain for a known signal.
Absolute gain is measured (differentially) with a 1 kHz sine wave
at 0 dBm0 for the DAC and with a 1 kHz sine wave at 0dBm0
for the ADC. The absolute gain specification is used for gain
tracking error specification.
CrosstalkCrosstalk is due to coupling of signals from a given channel
to an adjacent channel. It is defined as the ratio of the ampli-
tude of the coupled signal to the amplitude of the input signal.
Crosstalk is expressed in dB.
Gain Tracking ErrorGain tracking error measures changes in converter output for
different signal levels relative to an absolute signal level. The
absolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHz
for the DAC and 0 dBm0 (equal to absolute gain) at 1 kHz for
the ADC. Gain tracking error at 0 dBm0 (ADC) and 0 dBm0
(DAC) is 0 dB by definition.
Group DelayGroup delay is defined as the derivative of radian phase with
respect to radian frequency, dø(f)/df. Group delay is a measure
of average delay of a system as a function of frequency. A linear
system with a constant group delay has a linear phase response.
The deviation of group delay from a constant indicates the degree
of nonlinear phase response of the system.
Idle Channel NoiseIdle channel noise is defined as the total signal energy measured
at the output of the device when the input is grounded (measured
in the frequency range 300Hz–3400 Hz).
Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For final testing, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
Power Supply RejectionPower supply rejection measures the susceptibility of a device to
noise on the power supply. Power supply rejection is measured
by modulating the power supply with a sine wave and measuring
the noise at the output (relative to 0 dB).
Sample RateThe sample rate is the rate at which the ADC updates its out-
put register and the DAC updates its output from its input
register. It is fixed relative to the DMCLK (= DMCLK/256)
and therefore may only be changed by changing the DMCLK.
SNR+THDSignal-to-noise ratio plus harmonic distortion is defined to be
the ratio of the rms value of the measured input signal to the
rms sum of all other spectral components in the frequency range
300Hz–3400 Hz, including harmonics but excluding dc.
ABBREVIATIONSADCAnalog-to-Digital Converter.
ALBAnalog Loop-Back.Bandwidth.
CRxA Control Register where x is a placeholder for an
alphabetic character (A–E). There are five read/
write control registers on the AD73311L—desig-
nated CRA through CRE.
CRx:nA bit position, where n is a placeholder for a
numeric character (0–7), within a control register;
where x is a placeholder for an alphabetic charac-
ter (A–E). Position 7 represents the MSB and
Position 0 represents the LSB.
DACDigital-to-Analog Converter.
DLBDigital Loop-Back.
DMCLKDevice (Internal) Master Clock. This is the
internal master clock resulting from the external
master clock (MCLK) being divided by the on-chip
master clock divider.
FSLBFrame Sync Loop-Back—where the SDOFS of
the final device in a cascade is connected to the
RFS and TFS of the DSP and the SDIFS of first
device in the cascade. Data input and output
occur simultaneously. In the case of nonFSLB,
SDOFS and SDO are connected to the Rx Port
of the DSP while SDIFS and SDI are connected
to the Tx Port.
PGAProgrammable Gain Amplifier.Switched Capacitor.
SNRSignal-to-Noise Ratio.
SPORTSerial Port.
THDTotal Harmonic Distortion.
VBWVoice Bandwidth.
FUNCTIONAL DESCRIPTION
Encoder ChannelThe encoder channel consists of an input configuration block, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input anti-
alias requirements are reduced such that a simple single pole
RC stage is sufficient to give adequate attenuation in the band
of interest.
Input Configuration BlockThe input configuration block consists of a multiplexing arrange-
ment that allows selection of various input configurations. This
includes ADC input selection from either the VINP, VINN pins
or from the DAC output via the Analog Loop-Back (ALB)
arrangement. Differential inputs can be inverted and it is also
possible to use the device in single-ended mode, which allows
the option of using the VINP, VINN pins as two separate
single-ended inputs, either of which can be selected under
software control.
Programmable Gain AmplifierThe encoder section’s analog front end comprises a switched
capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table III, may be
used to increase the signal level applied to the ADC from low
output sources such as microphones, and can be used to avoid
placing external amplifiers in the circuit. The input signal level
to the sigma-delta modulator should not exceed the maximum
input voltage permitted.
The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)
in Control Register D.
Table III.PGA Settings for the Encoder Channel
ADCThe ADC consists of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modu-
lator noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bitstream, representing the analog input
signal, is input to the antialiasing decimation filter. The decima-
tion filter reduces the sample rate and increases the resolution.
Analog Sigma-Delta ModulatorThe AD73311L input channel employs a sigma-delta conver-
sion technique, which provides a high resolution 16-bit output
with system filtering being implemented on-chip.
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to FS/2 = DMCLK/16
(Figure 6a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 6b). The combi-
nation of these techniques, followed by the application of a
digital filter, reduces the noise in band sufficiently to ensure
good dynamic performance from the part (Figure 6c).
Figure 6.Sigma-Delta Noise Reduction
Figure 7 shows the various stages of filtering that are employed
in a typical AD73311L application. In Figure 7a we see the
transfer function of the external analog antialias filter. Even
though it is a single RC pole, its cutoff frequency is sufficiently
far away from the initial sampling frequency (DMCLK/8) that
it takes care of any signals that could be aliased by the sampling
frequency. This also shows the major difference between the
initial oversampling rate and the bandwidth of interest. In Figure
7b, the signal and noise-shaping responses of the sigma-delta
modulator are shown. The signal response provides further
rejection of any high frequency signals while the noise-shaping
will push the inherent quantization noise to an out-of-band
position. The detail of Figure 7c shows the response of the
digital decimation filter (Sinc-cubed response) with nulls every
multiple of DMCLK/256, which is the decimation filter update
rate. The final detail in Figure 7d shows the application of a
final antialias filter in the DSP engine. This has the advantage
AD73311L
FB = 4kHzFSINIT = DMCLK/8Analog Antialias Filter Transfer FunctionAnalog Sigma-Delta Modulator Transfer FunctionDigital Decimator Transfer FunctionFinal Filter LPF (HPF) Transfer Function
Figure 7.AD73311L ADC Frequency Responses
Decimation FilterThe digital filter used in the AD73311L carries out two impor-
tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 at the modula-
tor to an output rate at the SPORT of DMCLK/M (where M
depends on the sample rate setting—M = 256 @ 64 kHz; M =
512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and
increases the resolution from a single bit to 15 bits. Its Z trans-
form is given as: [(1–Z–N)/(1–Z–1)]3 where N is determined by
the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N =
128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal
group delay of 25 µs at the 64 kHz sampling rate.
ADC CodingThe ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the 16-bit
transfer being used as a flag bit to indicate either control or data
in the frame.
Figure 8.ADC Transfer Function
Decoder ChannelThe decoder channel consists of a digital interpolator, digital
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing filter and a programmable gain
amplifier with differential output.
DAC CodingThe DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation FilterThe anti-imaging interpolation filter is a sinc-cubed digital filter
which up-samples the 16-bit input words from the SPORT
input rate of DMCLK/M (where M depends on the sample rate
setting—M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @
16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while
filtering to attenuate images produced by the interpolation pro-
cess. Its Z transform is given as: [(1–Z–N)/(1–Z–1)]3 where N is
determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @
32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC
receives 16-bit samples from the host DSP processor at a rate of
DMCLK/M. If the host processor fails to write a new value to
the serial port, the existing (previous) data is read again. The
data stream is filtered by the anti-imaging interpolation filter,
but there is an option to bypass the interpolator for the mini-
mum group delay configuration by setting the IBYP bit (CRE:5) of
Control Register E. The interpolation filter has the same charac-
The output of the interpolation filter is fed to the DAC’s digital
sigma-delta modulator, which converts the 16-bit data to 1-bit
samples at a rate of DMCLK/8. The modulator noise-shapes
the signal so that errors inherent to the process are minimized
in the passband of the converter. The bitstream output of the
sigma-delta modulator is fed to the single bit DAC where it is
converted to an analog voltage.
Analog Smoothing Filter and PGAThe output of the single-bit DAC is sampled at DMCLK/8,
therefore it is necessary to filter the output to reconstruct the
low frequency signal. The decoder’s analog smoothing filter
consists of a continuous-time filter preceded by a third-order
switched-capacitor filter. The continuous-time filter forms part
of the output programmable gain amplifier (PGA). The PGA
can be used to adjust the output signal level from –15 dB todB in 3 dB steps, as shown in Table IV. The PGA gain is
set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control
Register D.
Table IV.PGA Settings for the Decoder Channel
Differential Output AmplifiersThe decoder has a differential analog output pair (VOUTP and
VOUTN). The output channel can be muted by setting the
MUTE bit (CRD:7) in Control Register D. The output signal
is dc-biased to the codec’s on-chip voltage reference.
Voltage ReferenceThe AD73311L reference, REFCAP, is a bandgap reference
that provides a low noise, temperature-compensated reference
to the DAC and ADC. A buffered version of the reference is
also made available on the REFOUT pin and can be used to
bias other external analog circuitry. The reference has a default
nominal value of 1.2V.
The reference output (REFOUT) can be enabled for biasing
external circuitry by setting the RU bit (CRC:6) of CRC.
Serial Port (SPORT)The codec communicates with a host processor via the bidirec-
tional synchronous serial port (SPORT) which is compatible
with most modern DSPs. The SPORT is used to transmit and
receive digital data and control information.
In both transmit and receive modes, data is transferred at the
serial clock (SCLK) rate with the MSB being transferred first.
Due to the fact that the SPORT uses a common serial register for
serial input and output, communications between an AD73311L
codec and a host processor (DSP engine) must always be initi-
ated by the codec itself. This ensures that there is no danger of
SPORT OverviewThe AD73311L SPORT is a flexible, full-duplex, synchronous
serial port whose protocol has been designed to allow up to eight
AD73311L devices to be connected, in cascade, to a single DSP
via a six-wire interface. It has a very flexible architecture that can
be configured by programming two of the internal control regis-
ters. The AD73311L SPORT has three distinct modes of opera-
tion: Control Mode, Data Mode and Mixed Control/Data Mode.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the five internal control
registers. In this mode, control information can be written to or
read from the codec. In Data Mode (CRA:0 = 1), information
that is sent to the device is used to update the decoder section
(DAC), while the encoder section (ADC) data is read from the
device. In this mode, only DAC and ADC data is written to or
read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)
allows the user to choose whether the information being sent to
the device contains either control information or DAC data.
This is achieved by using the MSB of the 16-bit frame as a flag
bit. Mixed mode reduces the resolution to 15 bits with the MSB
being used to indicate whether the information in the 16-bit
frame is control information or DAC/ADC data.
The SPORT features a single 16-bit serial register that is used
for both input and output data transfers. As the input and out-
put data must share the same register there are some precautions
that must be observed. The primary precaution is that no infor-
mation must be written to the SPORT without reference to an
output sample event, which is when the serial register will be
overwritten with the latest ADC sample word. Once the SPORT
starts to output the latest ADC word then it is safe for the DSP
to write new control or data words to the codec. In certain con-
figurations, data can be written to the device to coincide with
the output sample being shifted out of the serial register—see
section on interfacing devices. The serial clock rate (CRB:2–3)
defines how many 16-bit words can be written to a device before
the next output sample event will happen.
The SPORT block diagram, shown in Figure 9, details the six
control registers (A–F), external MCLK to internal DMCLK
divider and serial clock divider. The divider rates are controlled
by the setting of Control Register B. The AD73311L features a
master clock divider that allows users the flexibility of dividing
externally available high frequency DSP or CPU clocks to gener-
ate a lower frequency master clock internally in the codec which
may be more suitable for either serial transfer or sampling rate
requirements. The master clock divider has five divider options
(÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are set by loading
the master clock divider field in Register B with the appropriate
code. Once the internal device master clock (DMCLK) has
been set using the master clock divider, the sample rate and
serial clock settings are derived from DMCLK.
The SPORT can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the
master clock divider. When working at the lower SCLK rate of
DMCLK/8, which is intended for interfacing with slower DSPs,
AD73311L
SPORT Register MapsThere are two register banks for the AD73311L: the control
register bank and the data register bank. The control register
bank consists of six read/write registers, each eight bits wide.
Table IX shows the control register map for the AD73311L.
The first two control registers, CRA and CRB, are reserved for
controlling the SPORT. They hold settings for parameters such
as bit rate, internal master clock rate and device count (used
when more than one AD73311L is connected in cascade from
a single SPORT). The other three registers; CRC, CRD and
CRE are used to hold control settings for the ADC, DAC,
Reference and Power Control sections of the device. Control
registers are written to on the negative edge of SCLK. The
data register bank consists of two 16-bit registers that are the
DAC and ADC registers.
Master Clock DividerThe AD73311L features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to
produce an internal master clock signal (DMCLK) that is used
to calculate the sampling and serial clock rates. The master
clock divider is programmable by setting CRB:4-6. Table V shows
the division ratio corresponding to the various bit settings. The
default divider ratio is divide-by-one.
Table V.DMCLK (Internal) Rate Divider Settings
Serial Clock Rate DividerThe AD73311L features a programmable serial clock divider that
allows users to match the serial clock (SCLK) rate of the data to
that of the DSP engine or host processor. The maximum SCLK
Figure 9.SPORT Block Diagram
is programmable by setting bits CRB:2–3. Table VI shows the
serial clock rate corresponding to the various bit settings.
Table VI.SCLK Rate Divider Settings
Sample Rate DividerThe AD73311L features a programmable sample rate divider
that allows users flexibility in matching the codec’s ADC and
DAC sample rates to the needs of the DSP software. The maxi-
mum sample rate available is DMCLK/256 which offers the
lowest conversion group delay, while the other available rates
are: DMCLK/512, DMCLK/1024 and DMCLK/2048. The
slowest rate (DMCLK/2048) is the default sample rate. The
sample rate divider is programmable by setting bits CRB:0-1.
Table VII shows the sample rate corresponding to the various
bit settings.
Table VII.Sample Rate Divider Settings
DAC Advance RegisterThe loading of the DAC is internally synchronized with the
unloading of the ADC data in each sampling interval. The
default DAC load event happens one SCLK cycle before the
SDOFS flag is raised by the ADC data being ready. However,
this DAC load position can be advanced before this time by
modifying the contents of the DAC Advance field in Control
Register E (CRE:0–4). The field is five bits wide, allowing 31
increments of weight 1/(DMCLK/8); see Table VIII. In certain
circumstances this can reduce the group delay when the ADC
Table X.Control Word Description
Table IX.Control Register Map
Table VIII.DAC Timing Control*DMCLK = 16.384 MHz.
OPERATION
Resetting the AD73311LThe pin RESET resets all the control registers. All registers are
reset to zero indicating that the default SCLK rate (DMCLK/8)
and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the RESET pin, the
device can be reset using the RESET bit (CRA:7) in Control
Register A. Both hardware and software resets require 4 DMCLK
cycles. On reset, DATA/PGM (CRA:0) is set to 0 (default condi-
tion) thus enabling Program Mode. The reset conditions ensure
that the device must be programmed to the correct settings after
power-up or reset. Following a reset, the SDOFS will be asserted
2048 DMCLK cycles after RESET going high. The data that
is output following RESET and during Program Mode is ran-
dom and contains no valid information until either Data or
Mixed Mode is set.
Power ManagementThe individual functional blocks of the AD73311L can be
enabled separately by programming the power control register
CRC. It allows certain sections to be powered down if not
required, which adds to the device’s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. The power
control register provides individual control settings for the major
functional blocks and also a global override that allows all sec-
tions to be powered up by setting the bit. Using this method the
user could, for example, individually enable a certain section,
such as the reference (CRC:5), and disable all others. The glo-
bal power-up (CRC:0) can be used to enable all sections but if
power-down is required using the global control, the reference
will still be enabled, in this case, because its individual bit is set.
Refer to Table XIII for details of the settings of CRC.
AD73311L
Table XI.Control Register A Description
CONTROL REGISTER A
Table XII.Control Register B Description
CONTROL REGISTER B
Table XIII.Control Register C Description
CONTROL REGISTER C
Table XIV.Control Register D Description
CONTROL REGISTER D
Table XV.Control Register E Description
CONTROL REGISTER E
Table XVI.Control Register F Description
CONTROL REGISTER F
AD73311L
Operating ModesThere are five operating modes available on the AD73311L.
Two of these—Digital Loop-Back and Sport Loop-Back—are
provided as diagnostic modes with the other three, Program,
Data and Mixed Program/Data, being available for general
purpose use. The device configuration—register settings—can
be changed only in Program and Mixed Program/Data Modes.
In all modes, transfers of information to or from the device
occur in 16-bit packets, therefore the DSP engine’s SPORT will
be programmed for 16-bit transfers.
Program (Control) ModeIn Program Mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation—SPORT
operation, cascade length, power management, input/output
gain, etc. In this mode, the 16-bit information packet sent to the
device by the DSP engine is interpreted as a control word whose
format is shown in Table X. In this mode, the user must address
the device to be programmed using the address field of the control
word. This field is read by the device and if it is zero (000 bin)
then the device recognizes the word as being addressed to it. If the
address field is not zero, it is then decremented and the control
word is passed out of the device—either to the next device in a
cascade or back to the DSP engine. This 3-bit address format
allows the user to uniquely address any one of up to eight devices
in a cascade; please note that this addressing scheme is valid only
in sending control information to the device —a different format
is used to send DAC data to the device(s). In a single codec
configuration, all control word addresses must be zero, other-
wise they will not be recognized; in a multi-codec configuration
all addresses from zero to N-1 (where N = number of devices in
cascade) are valid.
Following reset, when the SE pin is enabled, the codec responds
by raising the SDOFS pin to indicate that an output sample
event has occurred. Control words can be written to the device to
coincide with the data being sent out of the SPORT, as shown in
Figure 10, or they can lag the output words by a time interval
that should not exceed the sample interval. After reset, output
frame sync pulses will occur at a slower default sample rate, which
is DMCLK/2048, until Control Register B is programmed after
which the SDOFS pulses will occur at a rate set by the DIR0-1 bits
of CRB. This is to allow slow controller devices to establish
communication with the AD73311L. During Program Mode,
the data output by the device is random and should not be inter-
preted as ADC data.
Data ModeOnce the device has been configured by programming the cor-
rect settings to the various control registers, the device may exit
Program Mode and enter Data Mode. This is done by program-
ming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to
0. Once the device is in Data Mode, the 16-bit input data frame
is now interpreted as DAC data rather than a control frame. This
data is therefore loaded directly to the DAC register. In Data
Mode, as the entire input data frame contains DAC data, the
device relies on counting the number of input frame syncs
received at the SDIFS pin. When that number equals the device
count stored in the device count field of CRA, the device knows
that the present data frame being received is its own DAC update
data. When the device is in normal Data Mode (i.e., mixed
mode disabled), it must receive a hardware reset to reprogram
any of the control register settings. In a single codec configura-
tion, each 16-bit data frame sent from the DSP to the device is
interpreted as DAC data. The default device count is 1, therefore
each input frame sync will cause the 16-bit data frame to be
loaded to the DAC register.
Mixed Program/Data ModeThis mode allows the user to send control words to the device
along with the DAC data. This permits adaptive control of the
device whereby control of the input/output gains can be effected
by interleaving control words along with the normal flow of
DAC data. The standard data frame remains 16 bits, but now
the MSB is used as a flag bit to indicate whether the remaining
15 bits of the frame represent DAC data or control information.
In the case of DAC data, the 15 bits are loaded with MSB justi-
fication and LSB set to 0 to the DAC register. Mixed mode is
enabled by setting the MM bit (CRA:1) to 1 and the DATA/PGM
bit (CRA:0) to 1. In the case where control setting changes will
be required during normal operation, this mode allows the
ability to load both control and data information with the slight
inconvenience of formatting the data. Note that the output
samples from the ADC will also have the MSB set to zero to
indicate it is a data word.
Digital Loop-BackThis mode can be used for diagnostic purposes and allows the
user to feed the ADC samples from the ADC register directly to
the DAC register. This forms a loop-back of the analog input to
the analog output by reconstructing the encoded signal using
the decoder channel. The serial interface will continue to work,
which allows the user to control gain settings, etc. Only when
DLB is enabled with Mixed Mode operation can the user disable
the DLB, otherwise the device must be reset.
Sport Loop-BackThis mode allows the user to verify the DSP interfacing and
connection by writing words to the SPORT of the device and
have them returned back unchanged at the next sample interval.
The frame sync and data word that are sent to the device are
returned via the output port. Again, SLB mode can only be
disabled when used in conjunction with mixed mode, otherwise
the device must be reset.
Analog Loop-BackIn Analog Loop-Back mode, the differential DAC output is
connected, via a loop-back switch, to the ADC input (see Figure
12). This mode allows the ADC channel to check functionality
of the DAC channel as the reconstructed output signal can be
monitored using the ADC as a sampler. Analog Loop-Back is
enabled by setting the ALB bit (CRF:7).
Figure 10.Interface Signal Timing for Single Device Operation
Figure 11.Interface Signal Timing for Cascade of Two Devices
AD73311LFigure 12.Analog Loop-Back Connectivity
INTERFACINGThe AD73311L can be interfaced to most modern DSP engines
using conventional serial port connections and an extra enable
control line. Both serial input and output data use an accompa-
nying frame synchronization signal which is active high one
clock cycle before the start of the 16-bit word or during the last
bit of the previous word if transmission is continuous. The serial
clock (SCLK) is an output from the codec and is used to define
the serial transfer rate to the DSP’s Tx and Rx ports. Two primary
configurations can be used: the first is shown in Figure 13, where
the DSP’s Tx data, Tx frame sync, Rx data and Rx frame sync
are connected to the codec’s SDI, SDIFS, SDO and SDOFS,
respectively. This configuration, referred to as indirectly coupled
or nonframe sync loop-back, has the effect of decoupling the
transmission of input data from the receipt of output data. The
delay between receipt of codec output data and transmission of
input data for the codec is determined by the DSP’s software
latency. When programming the DSP serial port for this con-
figuration, it is necessary to set the Rx FS as an input and the Tx
FS as an output generated by the DSP. This configuration is
most useful when operating in mixed mode, as the DSP has the
ability to decide how many words (either DAC or control) can be
sent to the codec(s). This means that full control can be imple-
mented over the device configuration as well as updating the
DAC in a given sample interval. The second configuration
(shown in Figure 14) has the DSP’s Tx data and Rx data con-
nected to the codec’s SDI and SDO, respectively while the
DSP’s Tx and Rx frame syncs are connected to the codec’s
SDIFS and SDOFS. In this configuration, referred to as directly
coupled or frame sync loop-back, the frame sync signals are
connected together and the input data to the codec is forced to
be synchronous with the output data from the codec. The DSP
must be programmed so that both the Tx FS and Rx FS are
inputs as the codec SDOFS will be input to both. This configura-
tion guarantees that input and output events occur simultaneously
and is the simplest configuration for operation in normal Data
Mode. Note that when programming the DSP in this configura-
tion it is advisable to preload the Tx register with the first control
word to be sent before the codec is taken out of reset. This
ensures that this word will be transmitted to coincide with the
first output word from the device(s).
Figure 13.Indirectly Coupled or Nonframe Sync Loop-
Back Configuration
Cascade OperationThe AD73311L has been designed to support up to eight codecs
in a cascade connected to a single serial port (see Figure 37).
The SPORT interface protocol has been designed so that device
addressing is built into the packet of information sent to the device.
This allows the cascade to be formed with no extra hardware
overhead for control signals or addressing. A cascade can be
formed in either of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. Table XVII details the requirements for SCLK rate
for cascade lengths from 1 to 8 devices. This assumes a directly
coupled frame sync arrangement as shown in Figure 13.
Table XVII.Cascade OptionsFigure 14. Directly Coupled or Frame Sync Loop-
