AD724JR-REEL ,RGB to NTSC/PAL EncoderSPECIFICATIONSParameter Conditions Min Typ Max UnitsSIGNAL INPUTS (RIN, GIN, BIN)Input Amplitude Fu ..
AD724JRZ ,RGB to NTSC/PAL Encoder
AD7276YUJZ-REEL7 , 3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7278BUJZ-REEL7 , 3 MSPS, 12-/10-/8-Bit ADCs in 6-Lead TSOT
AD7302BRU ,2.7 V to 5.5 V, Parallel Input Dual Voltage Output 8-Bit DAC
AD7303BRM ,+2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC
ADDAC80-CCD-V ,COMPLETE LOW COST 12-BIT D/A CONVERTERSCHARACTERISTICS
ACCURACY
Linearity Error Ca, + 25%
CBI LS B 1
CCD LS B
TA 6? Trninto Tm" LSB
..
ADDAC80CCD-V ,COMPLETE LOW COST 12-BIT D/A CONVERTERSapplications where reliability and cost are of paramount
importance.
Advanced circuit design an ..
ADDAC80D-CBI-V ,COMPLETE LOW COST 12-BIT D/A CONVERTERSSpecifications shown in boldfm: are tested on til production units at final clcclri-
53:: tml." 1v ..
ADDAC80DCBI-V ,COMPLETE LOW COST 12-BIT D/A CONVERTERSFEATURES
Single Chip Construction
On-Board Output Amplifier
Low Power Dissipation: 300mW mm”
..
ADDAC80N-CBI-V ,COMPLETE LOW COST 12-BIT D/A CONVERTERSCHARACTERISTICS
ACCURACY
Linearity Error GI + 25'C
CBI t 1/2 LSB'
CCD t U4 LSB
TA Crt Tu, 10 T ..
ADDAC85-CBI-I ,COMPLETE LOW COST 12-BIT D/A CONVERTERSapplications where low cost and high
reliability are major considerations.
3. The high speed ou ..
AD724JR-AD724JR--AD724JR-REEL
RGB to NTSC/PAL Encoder
RGB to NTSC/PAL EncoderFEATURES
Low Cost, Integrated Solution
+5 V Operation
Accepts FSC Clock or Crystal, or 4FSC Clock
Composite Video and Separate Y/C (S-Video) Outputs
Luma and Chroma Outputs Are Time Aligned
Minimal External Components:
No External Filters or Delay Lines Required
Onboard DC Clamp
Accepts Either HSYNC and VSYNC or CSYNC
Phase Lock to External Subcarrier
Drives 75 V Reverse-Terminated Loads
Logic Selectable NTSC or PAL Encoding Modes
Compact 16-Lead SOIC
APPLICATIONS
RGB to NTSC or PAL Encoding
PRODUCT DESCRIPTIONThe AD724 is a low cost RGB to NTSC/PAL Encoder that
converts red, green and blue color component signals into their
corresponding luminance (baseband amplitude) and chromi-
nance (subcarrier amplitude and phase) signals in accordance
with either NTSC or PAL standards. These two outputs are also
combined to provide composite video output. All three outputs can
simultaneously drive 75 W, reverse-terminated cables. All logi-
cal inputs are TTL, 3 V and 5 V CMOS compatible. The chip
operates from a single +5 V supply. No external delay lines or
filters are required. The AD724 may be powered down when
not in use.
The AD724 accepts either FSC or 4FSC clock. When a clock is
not available, a low cost parallel-resonant crystal (3.58 MHz
(NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscilla-
tor generate the necessary subcarrier clock. The AD724 also
accepts the subcarrier clock from an external video source.
The interface to graphics controllers is simple: an on-chip logic
“XNOR” accepts the available vertical (VSYNC) and horizon-
tal sync (HSYNC) signals and creates the composite sync
(CSYNC) signal on-chip. If available, the AD724 will also
accept a standard CSYNC signal by connecting VSYNC to
Logic HI and applying CSYNC to the HSYNC pin. The
AD724 contains decoding logic to identify valid horizontal sync
pulses for correct burst insertion.
Delays in the U and V chroma filters are matched by an on-chip
sampled-data delay line in the Y signal path. To prevent alias-
ing, a prefilter at 5 MHz is included ahead of the delay line and
a post-filter at 5 MHz is added after the delay line to suppress
harmonics in the output. These low-pass filters are optimized
for minimum pulse overshoot. The overall luma delay, relative
to chroma, has been designed to be time aligned for direct input to
a television’s baseband. The AD724 comes in a space-saving
SOIC and is specified for the 0°C to +70°C commercial tem-
perature range.
FUNCTIONAL BLOCK DIAGRAMSUB-
CARRIER
NTSC/PAL
HSYNC
VSYNCRED
GREEN
BLUE
NTSC/PAL
LUMINANCE
OUTPUT
COMPOSITE
OUTPUT
CHROMINANCE
OUTPUT
BURSTREV.B
AD724–SPECIFICATIONS
(Unless otherwise noted, VS = +5, TA = +258C, using FSC synchronous clock. All loads are
150 V 6 5% at the IC pins. Outputs are measured at the 75 V reverse terminated load.)NOTESR, G, and B signals are inputted via an external ac coupling capacitor.Except during dc restore period (back porch clamp).All outputs measured at a 75 W reverse-terminated load; ac voltages at the IC output pins are twice those specified here.Ratio of chroma amplitude to burst amplitude, difference from ideal.Difference between ideal color-bar phases and the actual values.Driving the logic inputs with VOH < 4 V will increase static supply current approximately 150 mA per input.
Specifications are subject to change without notice.
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*SupplyVoltage, APOS to AGND . . . . . . . . . . . . . . . . . .+6V
SupplyVoltage, DPOS to DGND . . . . . . . . . . . . . . . . . .+6V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Inputs . . . . . . . . . . . . . . . . .DGND – 0.3 V to DPOS + 0.3 V
InternalPowerDissipation . . . . . . . . . . . . . . . . . . . . . .800 mW
Operating Temperature Range . . . . . . . . . . . . .0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +125°C
Lead Temperature Range (Soldering30sec) . . . . . . . .+230°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Thermal Characteristics: 16-Lead SOIC Package: qJA = 100°C/W.
PIN CONFIGURATION
16-Lead Wide Body (SOIC)
(R-16)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD724 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD724
PIN FUNCTION DESCRIPTIONS*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75 W reverse-terminated lines.
DPOS
DGND
VBIAS
DPOS
DGND
VCLAMP
DPOS
DGND
APOS
AGNDDGND
DPOSCircuit A Circuit C
IRE
VOLTSFigure 2.Modulated Pulse and Bar, NTSC
VOLTSFigure 3.Modulated Pulse and Bar, PAL
GENLOCK
+5V
FINFigure 1.Evaluation Setup
Figure 4.100% Color Bars, NTSC
VOLTSFigure 5.100% Color Bars, PAL
AD724Figure 6. 100% Color Bars on Vector Scope, NTSC
Figure 7.100% Color Bars on Vector Scope, PAL
Figure 8.Multipulse, NTSC
Figure 9.Multipulse, PAL
1ST2ND3RD4TH5TH6TH
DG DP (NTSC) (SYNC = EXT)
FIELD = 1 LINE = 27, 100 IRE RAMP
DIFFERENTIAL GAIN (%)
DIFFERENTIAL PHASE (deg)
MIN = –0.53MAX = 0.00p–p/MAX = 0.53
MIN = –1.14MAX = 0.00pk–pk = 1.14
–1.5 Figure 10.Composite Output
Differential Phase and Gain, NTSC
1ST2ND3RD4TH5TH6TH
DG DP (PAL) (SYNC = EXT)
LINE = 25, 700mV RAMP
DIFFERENTIAL GAIN (%)
DIFFERENTIAL PHASE (deg)
MIN = –0.32MAX = 0.10pk–pk = 0.42
MIN = –1.18MAX = 0.70pk–pk = 1.89
–2.0 Figure 11.Composite Output
Differential Phase and Gain, PAL
Figure 12.Horizontal Timing, NTSC
AVERAGE $ 256
102ns
94ns
H TIMING (PAL)
LINE = 25 Figure 13.Horizontal Timing, PAL
AD724
THEORY OF OPERATIONThe AD724 was designed to have three allowable modes of
applying a clock via the FIN pin. These are FSC (frequency of
subcarrier) mode with CMOS clock applied, FSC mode using
on-chip crystal oscillator, and 4FSC mode with CMOS clock
applied. The FSC frequency is 3.579545 MHz for NTSC or
4.433618 MHz for PAL.
To use FSC mode the SELECT pin is pulled low and either a
CMOS FSC clock is applied to FIN, or a parallel-resonant
crystal and appropriate tuning capacitor is placed between the
FIN pin and AGND to utilize the on-chip oscillator. The on-
chip Phase Locked Loop (PLL) is used in these modes to gener-
ate an internal 4FSC clock that is divided to perform the digital
timing as well as create the quadrature subcarrier signals for the
chrominance modulation.
In 4FSC mode, the SELECT pin is pulled high and the PLL is
bypassed.
Referring to the AD724 block diagram (Figure 14), the RGB
inputs (each 714 mV p-p max) are dc clamped using external
coupling capacitors. These clamps allow the user to have a black
level that is not at 0 V. The clamps will adjust to an on-chip
black input signal level of approximately 0.8 V. This clamping
occurs on the back porch during the burst period.
The RGB inputs then pass into an analog encoding matrix,
which creates the luminance (“Y”) signal and the chrominance
color difference (“U” and “V”) signals. The RGB to YUV en-
coding is performed using the following standard transformations:
Y = 0.299 · R + 0.587 · G + 0.114 · B
U = 0.493 · (B–Y)
V = 0.877 · (R–Y)
After the encoding matrix, the AD724 has two parallel analog
paths. The Y (luminance) signal is first passed through a 3-pole
4.85 MHz/6 MHz (NTSC/PAL) Bessel low-pass filter to pre-
vent aliasing in the sampled-data delay line. In this first low-pass
filter, the unclocked sync is injected into the Y signal. The Y
signal then passes through the sampled-data delay line, which is
clocked at 8FSC. The delay line was designed to match the
overall chrominance and luminance delays. Following the
sampled-data delay line is a 5.25 MHz/6.5 MHz (NTSC/PAL)
2-pole low-pass Bessel filter to smooth the reconstructed lumi-
nance signal.
The second analog path is the chrominance path in which the U
and V color difference signals are processed. The U and V sig-
nals first pass through 4-pole modified Bessel low-pass filters
with –3 dB frequencies of 1.2 MHz/1.5 MHz (NTSC/PAL) to
prevent aliasing in the modulators. The color burst levels are
injected into the U channel for NTSC (U and V for PAL) in
these premodulation filters. The U and V signals are then inde-
pendently modulated by a pair of balanced switching modula-
tors driven in quadrature by the color subcarrier.
The bandwidths of the on-chip filters are tuned using propri-
etary auto-tuning circuitry. The basic principle is to match an
RC time constant to a reference time period, that time being
one cycle of a subcarrier clock. The auto-tuning is performed
during the vertical blanking interval and has added hysteresis so
that once an acceptable tuning value is reached the part won’t
toggle tuning values from field to field. The bandwidths stated
in the above discussion are the design target bandwidths for
NTSC and PAL.
The AD724’s 4FSC clock (either produced by the on-chip PLL
or user supplied) drives a digital divide-by-four circuit to create
the quadrature signals for modulation. The reference phase 0° is
used for the U signal. In the NTSC mode, the V signal is modu-
lated at 90°, but in PAL mode, the V modulation alternates
between 90° and 270° at the horizontal line rate as required by
the PAL standard. The outputs of the U and V balanced modu-
lators are summed and passed through a 3-pole low-pass filter with
3.6 MHz/4.4 MHz bandwidths (NTSC/PAL) in order to re-
move the harmonics generated during the switching modulation.
SUB-
CARRIER
NTSC/PAL
HSYNC
VSYNCRED
GREEN
BLUE
CSYNC
NTSC/PAL
LUMINANCE
OUTPUT
COMPOSITE
OUTPUT
CHROMINANCE
OUTPUT
POWER AND GROUNDS
+5V
+5V
AGND
DGND
LOGIC
ANALOG
ANALOG
LOGIC
NOTE:
THE LUMINANCE, COMPOSITE, AND
CHROMINANCE OUTPUTS ARE AT
TWICE NORMAL LEVELS FOR DRIVING
75V REVERSE-TERMINATED LINES.
