AD7248AAN ,LC2MOS 12-Bit DACPORTsfeatures include extended temperature rangeDDoperation for commercial and industrial grades.The AD7 ..
AD7248AAN ,LC2MOS 12-Bit DACPORTsCHARACTERISTICS (V = +12 V to +15 V; V = O V or –12 V to –15 V; See Figures 5 and 7.)DD SSParameter ..
AD7248AAP ,LC2MOS 12-Bit DACPORTsfeatures a wide power supply rangeDACPORT is a registered trademark of .allowing operation from 12 ..
AD7248AAP ,LC2MOS 12-Bit DACPORTsfeatures include extended temperature rangeDDoperation for commercial and industrial grades.The AD7 ..
AD7248AAP ,LC2MOS 12-Bit DACPORTsFEATURESAD7245A FUNCTIONAL BLOCK DIAGRAM12-Bit CMOS DAC with Output Amplifier andReferenceImproved ..
AD7248AAR ,LC2MOS 12-Bit DACPORTsspecifications T to T unless otherwise noted.)L L MIN MAX2 2 2A B TParameter Version Version Versio ..
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ADD8704ACPZ-REEL7 ,16 V Quad Operational AmplifierGENERAL DESCRIPTION +IN A 2 ADD8704 11 +IN DThe ADD8704 is a single-supply quad operational amplifi ..
ADD8704ARU ,16 V Quad Operational AmplifierCHARACTERISTICS Offset Voltage V 2 15 mV OSOffset Voltage Drift –40°C ≤ T ≤ +85°C 10 µV/° ..
ADD8704ARUZ ,16 V Quad Operational AmplifierGENERAL DESCRIPTION +IN A 2 ADD8704 11 +IN DThe ADD8704 is a single-supply quad operational amplifi ..
ADD8704ARUZ-REEL ,16 V Quad Operational AmplifierCHARACTERISTICS Offset Voltage V 2 15 mV OSOffset Voltage Drift –40°C ≤ T ≤ +85°C 10 µV/° ..
ADD8710 ,10-Channel Gamma Buffer with Vcom Driver Data SheetSpecifications subject to change without notice. No license is granted by implication www.analog.c ..
AD7245AAN.-AD7245AAP-AD7245AAQ-AD7245AAR-AD7245ABN-AD7245ABR-AD7245ATQ-AD7248AAN-AD7248AAP-AD7248AAR-AD7248ABN-AD7248ABR
LC2MOS 12-Bit DACPORTs
REV.A
LC2MOS
12-Bit DACPORTs
FEATURES
12-Bit CMOS DAC with Output Amplifier and
Reference
Improved AD7245/AD7248:
12 V to 15 V Operation61/2 LSB Linearity Grade
Faster Interface–30 ns typ Data Setup Time
Extended Plastic Temperature Range (–408C to +858C)
Single or Dual Supply Operation
Low Power–65 mW typ in Single Supply
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A
GENERAL DESCRIPTIONThe AD7245A/AD7248A is an enhanced version of the industry
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a ±1/2 LSB linearity grade, faster
interface times and better full scale and reference variations with
VDD. Additional features include extended temperature range
operation for commercial and industrial grades.
The AD7245A/AD7248A is a complete, 12-bit, voltage output,
digital-to-analog converter with output amplifier and Zener volt-
age reference on a monolithic CMOS chip. No external user
trims are required to achieve full specified performance.
Both parts are microprocessor compatible, with high speed data
latches and double-buffered interface logic. The AD7245A ac-
cepts 12-bit parallel data which is loaded into the input latch on
the rising edge of CS or WR. The AD7248A has an 8-bit wide
data bus with data loaded to the input latch in two write opera-
tions. For both parts, an asynchronous LDAC signal transfers
data from the input latch to the DAC latch and updates the ana-
log output. The AD7245A also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.
The on-chip 5 V buried Zener diode provides a low noise, tem-
perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to +5 V and 0 V to +10 V
are available, while these two ranges plus an additional ±5 V
range are available with dual supplies. The output amplifiers are
capable of developing +10 V across a 2 kΩ load to GND.
The AD7245A/AD7248A is fabricated in linear compatible
CMOS (LC2MOS), an advanced, mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
The AD7245A is available in a small, 0.3" wide, 24-pin DIP and
DACPORT is a registered trademark of Analog Devices, Inc.
AD7245A FUNCTIONAL BLOCK DIAGRAM
AD7248A FUNCTIONAL BLOCK DIAGRAMSOIC and in 28-terminal surface mount packages. The
AD7248A is packaged in a small, 0.3" wide, 20-pin DIP and
SOIC and in 20-terminal surface mount packages.
PRODUCT HIGHLIGHTS1. The AD7245A/AD7248A is a 12-bit DACPORT® on a single
chip. This single chip design and small package size offer
considerable space saving and increased reliability over
multichip designs.
2. The improved interface times on the part allows easy, direct
interfacing to most modern microprocessors.
3. The AD7245A/AD7248A features a wide power supply range
allowing operation from 12 V supplies.
DIGITAL INPUTS
ANALOG OUTPUTS
NOTESPower supply tolerance is ±10% for A Version and ±5% for B and T Versions.Temperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version;–55°C to +125°C.See Terminology.With appropriate power supply tolerances.FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and ±5 V output ranges.This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.This error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and ±5 V ranges; it is calculated with respect to an ideal 9.9976 V on the
0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors.Full-Scale TC = ΔFS/ΔT, where ΔFS is the full-scale change from TA = +25°C to TMIN or TMAX.Sample tested at +25°C to ensure compliance.0 V to +10 V output range is available only when VDD ≥ +14.25 V.
Specifications subject to change without notice.
AD7245A/AD7248A–SPECIFICATIONS
(VDD = +12 V to +15 V,1 VSS = O V or –12 V to –15 V,1
AGND = DGND = O V, RL = 2 kV, CL = 1OO pF. All specifications TMIN to TMAX unless otherwise noted.)
SWITCHING CHARACTERISTICS1(VDD = +12 V to +15 V;2 VSS = O V or –12 V to –15 V;2 See Figures 5 and 7.)NOTES
1Sample tested at +25°C to ensure compliance.
2Power supply tolerance is ±10% for A Version and ±5% for B and T Versions.
ABSOLUTE MAXIMUM RATINGS1VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +34 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . .–0.3 V, VDD +0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
VOUT to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, +24 V
VOUT to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–32 V, 0 V
REF OUT2 to AGND . . . . . . . . . . . . . . . . . . . . . . . .0 V, VDD
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .6 mW/°C
Operating Temperature
Commercial (A, B Versions) . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . .–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.The output may be shorted to voltages in this range provided the power dissipa-
tion of the package is not exceeded. VOUT short circuit current is typically
80 mA.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality.
AD7245A/AD7248A
DAC GAIN ERRORDAC Gain Error is a measure of the output error between an
ideal DAC and the actual device output with all 1s loaded after
offset error has been allowed for. It is, therefore defined as:
Measured Value—Offset—Ideal Value
where the ideal value is calculated relative to the actual refer-
ence value.
UNIPOLAR OFFSET ERRORUnipolar Offset Error is a combination of the offset errors of the
voltage mode DAC and the output amplifier and is measured
when the part is configured for unipolar outputs. It is present
for all codes and is measured with all 0s in the DAC register.
BIPOLAR ZERO OFFSET ERRORBipolar Zero Offset Error is measured when the part is config-
ured for bipolar output and is a combination of errors from the
DAC and output amplifier. It is present for all codes and is
measured with a code of 2048 (decimal) in the DAC register.
SINGLE SUPPLY LINEARITY AND GAIN ERRORThe output amplifier of the AD7245A/AD7248A can have a
true negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is 0 V, the output voltage cannot actually go nega-
tive. Instead the output voltage sits on the lower rail and this re-
sults in the transfer function shown. This is an offset effect and
the transfer function would have followed the dotted line if the
output voltage could have gone negative. Normally, linearity is
measured after offset and full scale have been adjusted or al-
lowed for. On the AD7245A/AD7248A the negative offset is al-
lowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. This code is given by the
negative offset specification. For example, the single supply lin-
earity specification applies between Code 3 and Code 4095 for
the 25°C specification and between Code 5 and Code 4095 over
the TMIN to TMAX temperature range. Since gain error is also
measured after offset has been allowed for, it is calculated between
the same codes as the linearity error. Bipolar linearity and gain er-
ror are measured between Code 0 and Code 4095.
TERMINOLOGY
RELATIVE ACCURACYRelative Accuracy, or end-point nonlinearity, is a measure of the
actual deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after allow-
ing for zero and full scale and is normally expressed in LSBs or
as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITYDifferential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGHDigital Feedthrough is the glitch impulse injected from the digi-
tal inputs to the analog output when the inputs change state. It
is measured with LDAC high and is specified in nV-s.
AD7245A ORDERING GUIDENOTESTo order MIL-STD-883, Class B. processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.This grade will be available to /883B processing only.
AD7248A ORDERING GUIDENOTESTo order MIL-STD-883, Class B, processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.This grade will be available to /883B processing only.
AD7248A PIN FUNCTION DESCRIPTION
(DIP PIN NUMBERS)
PinMnemonicDescriptionlVSSNegative Supply Voltage (0 V for single
supply operation).
2ROFSBipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.REF OUTReference Output. The on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.AGNDAnalog Ground.DB11Data Bit 11. Most Significant Bit (MSB).
6-11DB10-DB5Data Bit 10 to Data Bit 5.DGNDDigital Ground.
13-16DB4-DB1Data Bit 4 to Data Bit 1.DB0Data Bit 0. Least Significant Bit (LSB).CSChip Select Input (Active LOW). The de-
vice is selected when this input is active.
PinMnemonicDescriptionWRWrite Input (Active LOW). This is used in
conjunction with CS to write data into the
input latch of the AD7245A.LDACLoad DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.CLRClear Input (Active LOW). When this in-
put is active the contents of the DAC latch
are reset to all 0s.VDDPositive Supply Voltage.RFBFeedback Resistor. This allows access to
the amplifier’s feedback loop.
24VOUTOutput Voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V,
0 V to +10 V or –5 V to +5 V.
PLCC
AD7245A PIN CONFIGURATIONS
DIP and SOICLCCC
AD7245A/AD7248A
AD7248A PIN FUNCTION DESCRIPTION
(ANY PACKAGE)
PinMnemonicDescription lVSSNegative Supply Voltage (0 V for single
supply operation).
2ROFSBipolar Offset Resistor. This provides
access to the on-chip application resistors
and allows different output voltage ranges.
3REF OUTReference Output. The on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
4AGNDAnalog Ground.
5DB7Data Bit 7.
6DB6Data Bit 6.
7DB5Data Bit 5.
8DB4Data Bit 4.
9DB3Data Bit 3.DGNDDigital Ground.DB2Data Bit 2/Data Bit 10.DB1Data Bit 1/Data Bit 9.DB0Data Bit 0 (LSB)/Data Bit 8.
PinMnemonicDescriptionCSMSBChip Select Input for MS Nibble. (Active
LOW). This selects the upper 4 bits of the
input latch. Input data is right justified.CSLSBChip Select Input for LS byte. (Active
LOW). This selects the lower 8 bits of the
input latch.WRWrite Input. This is used in conjunction
with CSMSB and CSLSB to load data
into the input latch of the AD7248A.LDACLoad DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.VDDPositive Supply Voltage.RFBFeedback Resistor. This allows access to
the amplifier’s feedback loop.VOUTOutput Voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V,
0 V to +10 V or –5 V to +5 V.
AD7248A PIN CONFIGURATIONS
LCCCPLCCDIP and SOIC
Power Supply Current vs. Temperature
Noise Spectral Density vs. Frequency
Positive-Going Settling Time
(VDD = +15 V, VSS = –15 V)
Reference Voltage vs. Temperature
Power Supply Rejection Ration vs. Frequency
Negative Going Settling Time
(VDD = +15 V, VSS = –15 V)
AD7245A/AD7248A
CIRCUIT INFORMATION
D/A SECTIONThe AD7245A/AD7248A contains a 12-bit voltage mode digi-
tal-to-analog converter. The output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. The reference voltage for the DAC is
provided by an on-chip buried Zener diode.
The DAC consists of a highly stable, thin-film, R–2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in Figure 1.
Figure 1.D/A Simplified Circuit Diagram
The input impedance of the DAC is code dependent and can
vary from 8 kΩ to infinity. The input capacitance also varies
with code, typically from 50 pF to 200 pF.
OP AMP SECTIONThe output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different out-
put voltage ranges (discussed later). The buffer amplifier is ca-
pable of developing up to 10 V across a 2 kΩ load to GND.
The output amplifier can be operated from a single positive
power supply by tying VSS = AGND = 0 V. The amplifier can
also be operated from dual supplies to allow a bipolar output
range of –5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the en-
tire output range and elimination of the effects of negative offset
on the transfer characteristic (outlined previously). Figure 2
shows the sink capability of the amplifier for single supply
operation.
The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz.
The broadband noise from the amplifier has a typical peak-to-
peak figure of 150 μV for a 1 MHz output bandwidth. There is
no significant difference in the output noise between single and
dual supply operation.
VOLTAGE REFERENCEThe AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. The reference is internally con-
nected to the DAC. Since the DAC has a variable input imped-
ance at its reference input the Zener diode reference is buffered.
This buffered reference is available to the user to drive the cir-
cuitry required for bipolar output ranges. It can be used as a ref-
erence for other parts in the system provided it is externally
buffered. The reference will give long-term stability comparable
with the best discrete Zener reference diodes. The performance
of the AD7245A/AD7248A is specified with internal reference,
and all the testing and trimming is done with this reference. The
reference should be decoupled at the REF OUT pin and recom-
mended decoupling components are 10 μF and 0.1 μF capaci-
tors in series with a 10 Ω resistor. A simplified schematic of the
reference circuitry is shown in Figure 3.
Figure 3.Internal Reference
DIGITAL SECTIONThe AD7245A/AD7248A digital inputs are compatible with ei-
ther TTL or 5 V CMOS levels. All data inputs are static pro-
tected MOS gates with typical input currents of less than 1 nA.
The control inputs sink higher currents (150 μA max) as a result
of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.
The AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. This is due to the volt-
age mode configuration of the DAC. Most of the impulse is ac-
tually as a result of feedthrough across the package.
INTERFACE LOGIC INFORMATION—AD7245ATable I shows the truth table for AD7245A operation. The part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC con-
trols the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
