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AD7243AN-AD7243AR-AD7243BN-AD7243BR
LC2MOS 12-Bit Serial DACPORT
REV.A
LC2MOS
12-Bit Serial DACPORT
FUNCTIONAL BLOCK DIAGRAM
AGND
DGND
REFOUT
REFIN
SDINCLRSCLKDCENSDO
ROFS
VOUT
VSS
VDD
BIN/
COMP
SYNCLDAC
FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
Three Selectable Output Ranges
–5 V to +5 V, 0 V to +5 V, 0 V to +10 V
Serial Interface
300 kHz DAC Update Rate
Small Size: 16-Lead DIP or SOIC
Nonlinearity: �1/2 LSB TMIN to TMAX
Low Power Dissipation: 100 mW Typical
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
GENERAL DESCRIPTIONThe AD7243 is a complete 12-bit, voltage output, digital-to-
analog converter with output amplifier and Zener voltage refer-
ence on a monolithic CMOS chip. No external trims are
required to achieve full specified performance.
The output amplifier is capable of developing +10 V across a
2 kΩ load. The output voltage ranges with single supply opera-
tion are 0 V to +5 V or 0 V to +10 V, while an additional bipo-
lar ±5 V output range is available with dual supplies. The ranges
are selected using the internal gain resistor.
The data format is natural binary in both unipolar ranges, while
either offset binary or two’s complement format may be selected
in the bipolar range. A CLR function is provided which sets the
output to 0 V in both unipolar ranges and in the two’s comple-
ment bipolar range, while with offset binary data format, the
output is set to –REFIN. This function is useful as a power-on
reset as it allows the output to be set to a known voltage level.
The AD7243 features a fast versatile serial interface which
allows easy connection to both microcomputers and 16-bit digi-
tal signal processors with serial ports. The serial data may be
applied at rates up to 5 MHz allowing a DAC update rate of
300 kHz. A serial data output capability is also provided which
allows daisy chaining in multi-DAC systems. This feature allows
any number of DACs to be used in a system with a simple
4-wire interface. All DACs may be updated simultaneously
using LDAC.
The AD7243 is fabricated on Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process. It is pack-
aged in 16-lead DIP and 16-lead SOIC packages.
PRODUCT HIGHLIGHTSComplete 12-Bit DACPORT®
The AD7243 is a complete, voltage output, 12-bit DAC on
a single chip. The single chip design is inherently more
reliable than multichip designs.Single or Dual Supply Operation.Minimum 3-wire interface to most DSP processors.DAC Update Rate–300 kHz.Serial Data Output allows easy daisy-chaining in multiple
DAC systems.
DACPORT is a registered trademark of Analog Devices, Inc.
AD7243–SPECIFICATIONSDIGITAL OUTPUT
AC CHARACTERISTICS
POWER REQUIREMENTS
NOTESPower Supply Tolerance A, B Versions: ±10%; S Version: ±5%.Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.See terminology.Measured with respect to REFIN and includes unipolar/bipolar offset error.Guaranteed by design and characterization, not production tested.0 V to +10 V output range is available only with VDD ≥ +14.25 V.
Specifications subject to change without notice.
(VDD = +12 V to +15 V,1 VSS = 0 V or –12 V to –15 V,1 AGND = DGND = O V, REFIN = +5 V,
RL = 2 k�, CL = 100 pF to AGND. All Specifications TMIN to TMAX unless otherwise noted.)
NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figures 7 & 8.SCLK mark/space ratio range is 40/60 to 60/40.SDO load capacitance is no greater than 50 pF.At 25°C t10 is 130ns max.Guaranteed by design.
ORDERING GUIDENOTESN = Plastic DIP; R = SOIC; Q = Cerdip.Available to /883B processing only. Contact your local sales office for military data sheet.
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to AGND, DGND . . . . . . . . . . . . . . . . .–0.3 V to +17 V
VSS to AGND, DGND . . . . . . . . . . . . . . . . .+0.3 V to –17 V
AGND to DGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
VOUT2 to AGND . . . . . . . . . . . . . . . . . . .–6 V to VDD + 0.3 V
REFOUT to AGND . . . . . . . . . . . . . . . . . . . . . . .0 V to VDD
REFIN to AGND . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . .–0.3 V to VDD + 0.3 V
SDO to DGND . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . .–40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . .–55°C to +125°C
TIMING CHARACTERISTICS1, 2Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation (Any Package) to +75°C . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . .6 mW/°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one Absolute
Maximum Rating may be applied at any time.
2The outputs may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.
(VDD = +10.8 V to +16.5 V, VSS = 0 V or –10.8 V to –16.5 V, AGND = DGND = 0 V,
RL = 2 k�, CL = 100 pF. All Specifications TMIN to TMAX unless otherwise noted.)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7243 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
AD7243
AD7243 PIN FUNCTION DESCRIPTIONS (DIP and SOIC PIN NUMBERS)
TERMINOLOGY
Bipolar Zero ErrorBipolar Zero Error is the voltage measured at VOUT when the
DAC is configured for bipolar output and loaded with all 0s
(Two’s Complement Coding) or with 1000 0000 0000 (Offset
Binary Coding). It is due to a combination of offset errors in the
DAC, amplifier and mismatch between the internal gain resis-
tors around the amplifier.
Full-Scale ErrorFull-Scale Error is a measure of the output error when the am-
plifier output is at full scale (for the bipolar output range full
scale is either positive or negative full scale). It is measured with
respect to the reference input voltage and includes the offset
errors.
Digital-to-Analog Glitch ImpulseThis is the voltage spike that appears at VOUT when the digital
code in the DAC latch changes, before the output settles to its
final value. The energy in the glitch is specified in nV secs, and
is measured for an all codes change from 0000 0000 0000 to
1111 1111 1111 and vice versa.
Digital FeedthroughThis is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7243. It
is measured with LDAC held high.
Relative Accuracy (Linearity)Relative Accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a
straight line passing through the endpoints of the transfer func-
tion. It is measured after allowing for zero and full-scale errors
and is expressed in LSBs or as a percentage of full-scale reading.
Single Supply Linearity and Gain ErrorThe output amplifier on the AD7243 can have true negative off-
sets even when the part is operated from a single +15 V supply.
However, because the negative supply rail (VSS) is 0 V, the out-
put cannot actually go negative. Instead, when the output offset
voltage is negative, the output voltage sits at 0 V, resulting in the
transfer function shown in Figure 1.
Figure 1.Effect of Negative Offset (Single Supply)
TERMINOLOGY (Continued)This “knee” is an offset effect, not a linearity error, and the
transfer function would have followed the dotted line if the out-
put voltage could have gone negative.
Normally, linearity is measured between zero (all 0s input code)
and full scale (all 1s input code) after offset and full scale have
been adjusted out or allowed for, but this is not possible in
single supply operation if the offset is negative, due to the knee
in the transfer function. Instead, linearity of the AD7243 in the
unipolar mode is measured between full scale and the lowest
code which is guaranteed to produce a positive output voltage.
This code is calculated from the maximum specification for
negative offset. For the A and B versions the linearity is mea-
sured between Codes 3 and 4095. For the S grade, linearity is
measured between Code 5 and Code 4095.
Differential NonlinearityDifferential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB or less
over the operating temperature range ensures monotonicity.
Unipolar Offset ErrorUnipolar Offset Error is the measured output voltage from
VOUT with all zeros loaded into the DAC latch when the DAC is
configured for unipolar output. It is due to a combination of the
offset errors in the DAC and output amplifier.
PIN CONFIGURATION
DIP and SOIC
CIRCUIT INFORMATION
D/A SectionThe AD7243 contains a 12-bit voltage mode D/A converter
consisting of highly stable thin film resistors and high speed
NMOS single-pole, double-throw switches. The output voltage
from the converter has the same polarity as the reference volt-
age, REFIN, allowing single supply operation.
SHOWN FOR ALL 1S2RRRRR2R2R2R2R2R
REFIN*
ROFS
VOUT
Internal ReferenceThe AD7243 has an on-chip temperature compensated buried
Zener reference which is factory trimmed to 5 V ± 50 mV. The
reference voltage is provided at the REFOUT pin. This refer-
ence can be used to provide the reference voltage for the D/A
converter (by connecting the REFOUT pin to the REFIN pin.)
The reference voltage can also be used as a reference for other
components and is capable of providing up to 500 µA to an ex-
ternal load. The maximum recommended capacitance on
REFOUT for normal operation is 50 pF. If the reference is re-
quired for external use with capacitive loads greater than 50 pF
then it should be decoupled to AGND with a 200 Ω resistor in
series with a parallel combination of a 10 µF tantalum capacitor
and a 0.1 µF ceramic capacitor.
Figure 3.Reference Decoupling Scheme
External ReferenceIn some applications, the user may require a system reference or
some other external reference to drive the AD7243. References
such as the AD586 provide an ideal external reference source
(see Figure 10). The REFIN voltage is internally buffered by a
unity gain amplifier before being applied to the D/A converter.
The D/A converter is scaled for a 5 V reference and the device is
tested with 5 V applied to REFIN. Other reference voltages may
be used with degraded performance. Figure 4 shows the typical
degradation in linearity vs. REFIN.
Figure 4.Typical Linearity vs. REFIN Voltage
Op Amp SectionThe output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The ROFS input allows three out-
put voltage ranges to be selected. The buffer amplifier is capable
of developing +10 V across a 2 kΩ load to AGND.
The output amplifier can be operated from a single +12 V to
+15 V supply by tying VSS = 0 V.
AD72430 V, to allow full sink capability of 2.5 mA over the entire
output range and to eliminate the effects of negative offsets on
the transfer characteristic (outlined previously). A plot of the
output sink capability of the amplifier is shown in Figure 5.
Figure 5.Amplifier Sink Current
DIGITAL INTERFACEThe AD7243 contains an input serial to parallel shift register
and a DAC latch. A simplified diagram of the input loading
Figure 6.Simplified Loading Structure
SCLK
SDIN
SYNC
LDACcircuitry is shown in Figure 6. Serial data on the SDIN input is
loaded to the input register under control of DCEN, SYNC and
SCLK. When a complete word is held in the shift register, it
may then be loaded into the DAC latch under control of
LDAC. Only the data in the DAC latch determines the analog
output on the AD7243.
The DCEN (daisy-chain enable) input is used to select either a
standalone mode or a daisy-chain mode. The loading format is
slightly different depending on which mode is selected.
Serial Data Loading Format (Standalone Mode)With DCEN at Logic 0 the standalone mode is selected. In this
mode a low SYNC input provides the frame synchronization
signal which tells the AD7243 that valid serial data on the SDIN
input will be available for the next 16 falling edges of SCLK. An
internal counter/decoder circuit provides a low gating signal so
that only 16 data bits are clocked into the input shift register.
After 16 SCLK pulses the internal gating signal goes inactive
(high) thus locking out any further clock pulses. Therefore, ei-
ther a continuous clock or a burst clock source may be used to
clock in the data.
The SYNC input should be taken high after the complete 16-bit
word is loaded in.
