AD7237AAN ,LC2MOS Dual 12-Bit DACPORTsGENERAL DESCRIPTIONThe AD7237A/AD7247A is an enhanced version of the industrystandard AD7237/AD7247 ..
AD7237AAR ,LC2MOS Dual 12-Bit DACPORTsFEATURESComplete Dual 12-Bit DAC ComprisingTwo 12-Bit CMOS DACsOn-Chip Voltage ReferenceOutput Ampl ..
AD7237ABN ,LC2MOS Dual 12-Bit DACPORTsSPECIFICATIONS DGND = 0 V [AD7237A], GND = 0 V [AD7247A], REF IN = +5 V,R = 2 kΩ, C = 100 pF. All
AD7237ABR ,LC2MOS Dual 12-Bit DACPORTsSpecifications subject to change without notice.–2– REV. 0AD7237A/AD7247A3 3(V = +12 V to +15 V, V ..
AD7237KN ,LC2MOS DUAL 12-BIT DACPORT
AD7237KN ,LC2MOS DUAL 12-BIT DACPORT
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ADCMP600BKSZ-REEL7 , Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators
AD7233AN
LC2MOS 12-Bit Serial Mini-DIP DACPORT
FUNCTIONAL BLOCK DIAGRAMREV.A
LC2MOS
12-Bit Serial Mini-DIP DACPORT
GENERAL DESCRIPTIONThe AD7233 is a complete 12-bit, voltage-output, digital-to-
analog converter with output amplifier and Zener voltage refer-
ence all in an 8-lead package. No external trims are required to
achieve full specified performance. The data format is two’s
complement, and the output range is –5 V to +5 V.
The AD7233 features a fast, versatile serial interface which al-
lows easy connection to both microcomputers and 16-bit digital
signal processors with serial ports. When the SYNC input is
taken low, data on the SDIN pin is clocked into the input shift
register on each falling edge of SCLK. On completion of the
16-bit data transfer, bringing LDAC low updates the DAC latch
with the lower 12 bits of data and updates the output. Alterna-
tively, LDAC can be tied permanently low, and in this case the
DAC register is automatically updated with the contents of the
shift register when all sixteen data bits have been clocked in.
The serial data may be applied at rates up to 5 MHz allowing a
DAC update rate of 300 kHz.
For applications which require greater flexibility and unipolar
output ranges with single supply operation, please refer to the
AD7243 data sheet.
The AD7233 is fabricated on Linear Compatible CMOS
(LC2MOS), an advanced, mixed-technology process. It is pack-
aged in an 8-lead DIP package.
PRODUCT HIGHLIGHTSComplete 12-Bit DACPORT®.The AD7233 is a complete, voltage output, 12-bit DAC on a
single chip. This single-chip design is inherently more reli-
able than multichip designs.Simple 3-wire interface to most microcontrollers and DSP
processors.DAC Update Rate—300 kHz.Space Saving 8-Lead Package.
FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
–5 V to +5 V Output Range
Serial Interface
300 kHz DAC Update Rate
Small Size: 8-Pin Mini-DIP
Nonlinearity: �1/2 LSB TMIN to TMAX
Low Power Dissipation: 100 mW typ
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
DACPORT is a registered trademark of Analog Devices, Inc.
AD7233–SPECIFICATIONS1(VDD = +12 V to +15 V,2 VSS = –12 V to –15 V,2 GND = 0 V, RL = 2 k�,
CL = 100 pF to GND. All specifications TMIN to TMAX unless otherwise noted.) DIGITAL INPUTS
NOTESTemperature Ranges are as follows: A, B Versions: –40°C to +85°C.Power Supply Tolerance: A, B Versions: ±10%.See Terminology.Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2NOTESSample tested at +25°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.See Figure 3.SCLK Mark/Space Ratio range is 40/60 to 60/40.
(VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, GND = O V, RL = 2 k�,
CL = 100 pF. All Specifications TMIN to TMAX unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS1(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V
VOUT2 to GND . . . . . . . . . . . . . . . . . . . .–6 V to VDD +0.3 V
Digital Inputs to GND . . . . . . . . . . . . .–0.3 V to VDD +0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . .+300°C
Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . .450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . .10 mW/°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>4000 V
NOTESStresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.The output may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.
ORDERING GUIDE*N = Plastic DIP.
TERMINOLOGY
RELATIVE ACCURACY (LINEARITY)Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a straight
line passing through the endpoints of the transfer function. It is
measured after allowing for zero and full-scale errors and is ex-
pressed in LSBs or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITYDifferential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB or less
over the operating temperature range ensures monotonicity.
BIPOLAR ZERO ERRORBipolar zero error is the voltage measured at VOUT when the
DAC is loaded with all 0s. It is due to a combination of offset
errors in the DAC, amplifier and mismatch between the internal
gain resistors around the amplifier.
FULL-SCALE ERRORFull-scale error is a measure of the output error when the am-
plifier output is at full scale (full scale is either positive or nega-
tive full scale).
DIGITAL-TO-ANALOG GLITCH IMPULSEThis is the voltage spike that appears at the output of the DAC
when the digital code in the DAC latch changes before the out-
put settles to its final value. The energy in the glitch is specified
in nV secs, and is measured for an all codes change (0000 0000
0000 to 1111 1111 1111).
DIGITAL FEEDTHROUGHThis is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7233. It
is measured with LDAC held high.
AD7233
PIN FUNCTION DESCRIPTION
DIGITAL INTERFACEThe AD7233 contains an input serial to parallel shift register
and a DAC latch. A simplified diagram of the input loading cir-
cuitry is shown in Figure 2. Serial data on the SDIN input is
loaded to the input register under control of SYNC and SCLK.
When a complete word is held in the shift register it may then be
loaded into the DAC latch under control of LDAC. Only the
data in the DAC latch determines the analog output on the
AD7233.
A low SYNC input provides the frame synchronization signal
which tells the AD7233 that valid serial data on the SDIN input
will be available for the next 16 falling edges of SCLK. An inter-
nal counter/decoder circuit provides a low gating signal so that
only 16 data bits are clocked into the input shift register. After
16 SCLK pulses the internal gating signal goes inactive (high)
thus locking out any further clock pulses. Therefore, either a
continuous clock or a burst clock source may be used to clock in
the data.
The SYNC input should be taken high after the complete 16-bit
word is loaded in.
Although 16 bits of data are clocked into the input register, only
the latter 12 bits get transferred into the DAC latch. The first 4
bits in the 16-bit stream are don’t cares since their value does
not affect the DAC latch data. Therefore the data format is 4
don’t cares followed by the 12-bit data word with the LSB as the
last bit in the serial stream.
CIRCUIT INFORMATION
D/A SectionThe AD7233 contains a 12-bit voltage-mode D/A converter
consisting of highly stable thin-film resistors and high speed
NMOS single-pole, double-throw switches.
Op Amp SectionThe output of the voltage-mode D/A converter is buffered by a
noninverting CMOS amplifier. The buffer amplifier is capable
of developing ±5 V across a 2 kΩ load to GND.
Figure 1.Simplified D/A Converter
There are two ways in which the DAC latch and hence the ana-
log output may be updated. The status of the LDAC input is
examined after SYNC is taken low. Depending on its status, one
of two update modes is selected.
If LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated auto-
matically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
If LDAC = 1 then the automatic update is disabled and the
DAC latch is updated by taking LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of LDAC. This facility is useful for simultaneous
update in multi-DAC systems. Note that the LDAC input must
be taken back high again before the next data transfer is initiated.
Figure 2.Simplified Loading Structure
SCLK
SDIN
SYNC
LDACFigure 3. Timing Diagram
AD7233–Typical Performance Graphs
APPLYING THE AD7233
Bipolar (�5 V) ConfigurationThe AD7233 provides an output voltage range from –5 V to
+5 V without any external components. This configuration is
shown in Figure 4. The data format is two's complement. The
output code table is shown in Table I. If offset binary coding is
required, then this can be done by inverting the MSB in soft-
ware before the data is loaded to the AD7233.
Figure 4.Circuit Configuration
Power Supply DecouplingTo achieve optimum performance when using the AD7233, the
VDD and VSS lines should each be decoupled to GND using
0.1 µF capacitors. In very noisy environments it is recom-
mended that 10 µF capacitors be connected in parallel with the
0.1 µF capacitors.
Table I.AD7233 Bipolar Code TableX = Don’t Care
Note: 1 LSB = 5 V/2048 ≈ 2.4 mV
Power Supply Rejection Ratio
vs. Frequency
Linearity vs. Power Supply Voltage
Noise Spectral Density
vs. Frequency
