AD7228ABP ,LC2MOS Octal 8-Bit DACSpecifications except for negative full-scale settling-time when V = 0 V.SS
AD7228ABR ,LC2MOS Octal 8-Bit DACSpecifications5DYNAMIC PERFORMANCEVoltage Output Slew Rate 2 2 2 2 V/μs minVoltage Output Settling ..
AD7228ACN ,LC2MOS Octal 8-Bit DACspecifications T to T unless otherwise noted.MIN MAXSTATIC PERFORMANCEResolution 8 8 8 8 Bits3Total ..
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AD7228ABN-AD7228ABP-AD7228ABR-AD7228ACN
LC2MOS Octal 8-Bit DAC
REV.A
LC2MOS
Octal 8-Bit DAC
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS1. Eight DACs and Amplifiers in Small Package
The single-chip design of eight 8-bit DACs and amplifiers al-
lows a dramatic reduction in board space requirements and
offers increased reliability in systems using multiple convert-
ers. Its pinout is aimed at optimizing board layout with all
analog inputs and outputs at one side of the package and all
digital inputs at the other.
2. Single or Dual Supply Operation
The voltage-mode configuration of the DACs allows single
supply operation of the AD7228A. The part can also be oper-
ated with dual supplies giving enhanced performance for
some parameters.
3. Microprocessor Compatibility
The AD7228A has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered and speed compatible with most high per-
formance 8-bit microprocessors.
FEATURES
Eight 8-Bit DACs with Output Amplifiers
Operates with Single +5 V, +12 V or +15 V
or Dual SuppliesmP Compatible (95 ns WR Pulse)
No User Trims Required
Skinny 24-Pin DlPs, SOIC, and 28-Terminal Surface
Mount Packages
GENERAL DESCRIPTIONThe AD7228A contains eight 8-bit voltage-mode digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the eight D/A
converters. Data is transferred into the data latches through a
common 8-bit TTL/CMOS (5 V) compatible input port. Ad-
dress inputs A0, A1 and A2 determine which latch is loaded
when WR goes low. The control logic is speed compatible with
most 8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 to +10 V when using dual supplies. The part is also
specified for single supply +15 V operation using a reference of
+10 V and single supply +5 V operation using a reference of
+1.23 V. Each output buffer amplifier is capable of developing
+10 V across a 2 kΩ load.
The AD7228A is fabricated on an all ion-implanted, high-
speed, Linear Compatible CMOS (LC2MOS) process which has
been specifically developed to integrate high-speed digital logic
circuits and precision analog circuits on the same chip.
AD7228A–SPECIFICATIONS
(VDD = 10.8 V to 16.5 V; VSS = –5 V 6 10%; GND = 0 V; VREF = +2 V to +10 V1; RL = 2 kΩ, CL = 100 pF unless otherwise
noted.) All specifications TMIN to TMAX unless otherwise noted.Sample tested at 25°C to ensure compliance.
(VDD = +15 V 6 10%, VSS; = GND = 0 V; VREF = +10 V, RL = 2 kΩ, CL = 100 pF unless otherwise noted.)
AII specifications TMIN to TMAX unless otherwise noted.
DUAL SUPPLYSTATIC PERFORMANCE
REFERENCE INPUT
DIGITAL INPUTS
DYNAMIC PERFORMANCE
POWER SUPPLIES
SINGLE SUPPLYREFERENCE INPUT
POWER SUPPLIES
NOTES
1VOUT must be less than VDD by 3.5 V to ensure correct operation.
2Temperature ranges are as follows:
SWITCHING CHARACTERISTICS1, 2NOTES
1Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, tR = tF = 5 ns.
2Timing measurement reference level is
VINH+VINL
INTERFACE LOGIC INFORMATIONAddress lines A0, A1 and A2 select which DAC accepts data
from the input port. Table I shows the selection table for the
eight DACs with Figure 1 showing the input control logic.
When the WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high, the analog outputs remain
at the value corresponding to the data held in their respective
latches.
Table I.AD7228A Truth Table
+5 V SUPPLY OPERATIONREFERENCE INPUT
POWER REQUIREMENTS
NOTES
All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when VSS = 0 V.
Specifications subject to change without notice.
(VDD = +5 V 6 5%, VSS; = 0 to –5 V 6 10%, GND = 0 V, VREF = +1.25 V, RL = 2 kV, CL = 100 pF
unless otherwise noted.) AII specifications TMIN to TMAX unless otherwise noted.
(See Figures 1, 2; VDD = +5 V 6 5% or +10.8 V to +16.5 V; VSS = 0 V or –5 V 6 10%)Figure 1.Input Control Logic
AD7228A
OP AMP SECTIONEach voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. This buffer amplifier is
tested with a 2 kΩ and 100 pF load but will typically drive a
2 kΩ and 500 pF load.
The AD7228A can be operated single or dual supply. Operating
the part from single or dual supplies has no effect on the positive-
going settling time. However, the negative-going settling time to
voltages near 0 V in single supply will be slightly longer than the
settling time for dual supply operation. Additionally, to ensure
that the output voltage can go to 0 V in single supply, a transis-
tor on the output acts as a passive pull-down as the output volt-
age nears 0 V. As a result, the sink capability of the amplifier is
reduced as the output voltage nears 0 V in single supply. In dual
supply operation, the full sink capability of 400 μA at 25°C is
maintained over the entire output voltage range. The single sup-
ply output sink capability is shown in Figure 4. The negative
VSS also gives improved output amplifier performance allowing
an extended input reference voltage range and giving improved
slew rate at the output.
Figure 4.Single Supply Sink Current
The output broadband noise from the amplifier is 300 μV
peak-to-peak. Figure 5 shows a plot of noise spectral density
versus frequency.
Figure 5.Noise Spectral Density vs. Frequency
SUPPLY CURRENTThe AD7228A has a maximum IDD specification of 22 mA and
a maximum ISS of 20 mA over the –55°C to +125°C tempera-
ture range. This maximum current specification is actually de-
termined by the current at –55°C. Figure 6 shows a typical plot
of power supply current versus temperature.
Figure 6.Power Supply Current vs. Temperature
APPLYING THIS AD7228A
UNIPOLAR OUTPUT OPERATIONThis is the basic mode of operation for each channel of the
AD7228A, with the output voltage having the same positive po-
larity as VREF. Connections for unipolar output operation are
shown in Figure 7. The AD7228A can be operated from single
or dual supplies as outlined earlier. The voltage at the reference
input must never be negative with respect to GND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. The code table for unipolar output
operation is shown in Table II.
AD7228A
Table II.Unipolar Code TableNote: 1 LSB = (VREF)(2–8) = VREF
256
BIPOLAR OUTPUT OPERATIONEach of the DACs on the AD7228A can be individually config-
ured for bipolar output operation. This is possible using one ex-
ternal amplifier and two resistors per channel. Figure 8 shows a
circuit used to implement offset binary coding (bipolar opera-
tion) with DAC1 of the AD7228A. In this case
VOUT=1+R2·D1·VREF()±R2·VREF()
With R1 = R2
VOUT = (2D1 – 1) • (VREF)
where D1 is a fractional representation of the digital word in
latch 1 of the AD7228A. (0 ≤ D1 ≤ 255/256)
Figure 8. Bipolar Output Circuit
Table III.Bipolar Code TableMismatch between R1 and R2 causes gain and offset errors, and
therefore, these resistors must match and track over temperature.
Once again, the AD7228A can be operated from single supply
or from dual supplies. Table III shows the digital code versus
output voltage relationship for the circuit of Figure 8 with
R1 = R2.
AC REFERENCE SIGNALIn some applications it may be desirable to have an ac signal ap-
plied as the reference input to the AD7228A. The AD7228A
has multiplying capability within the upper (+10 V) and lower
(+2 V) limits of reference voltage when operated with dual sup-
plies. Therefore, ac signals need to be ac coupled and biased up
before being applied to the reference input. Figure 9 shows a
sine-wave signal applied to the reference input of the AD7228A.
For input frequencies up to 50 kHz, the output distortion typi-
cally remains less than 0.1%. The typical 3 dB bandwidth for
small signal inputs is 800 kHz.
Figure 9. Applying a AC Signal to the AD7228A
TIMING DESKEWA common problem in ATE applications is the slowing or
“rounding-off” of signal edges by the time they reach the
pin-driver circuitry. This problem can easily be overcome by
“squaring-up” the edge at the pin-driver. However, since each
edge will not have been “rounded-off” by the same extent, this
“squaring-up” could lead to incorrect timing relationship be-
tween signals. This effect is shown in Figure 10a.
Figure 10a.Time Skewing Due to Slowing of Edges
The circuit of Figure 10b shows how two DACs of the
AD7228A can help in overcoming this problem. The same two
signals are applied to this circuit as were applied in Figure 10b.
The output of each DAC is applied to one input of a high-speed
comparator, and the signals are applied to the other inputs.
Varying the output voltage of the DAC effectively varies the
trigger point at which the comparator flips. Thus the timing re-
