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AD7228ABN ,LC2MOS Octal 8-Bit DACSPECIFICATIONS1(V = 10.8 V to 16.5 V; V = –5 V 6 10%; GND = 0 V; V = +2 V to +10 V ; R = 2 kΩ, C = ..
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AD7226BQ-AD7226KN-AD7226KP-AD7226KR-AD7226TQ
LC2MOS Quad 8-Bit D/A Converter
REV.A
LC2MOS
Quad 8-Bit D/A Converter
FUNCTIONAL BLOCK DIAGRAMFEATURES
Four 8-Bit DACs with Output Amplifiers
Skinny 20-Pin DIP, SOIC and 20-Terminal
Surface Mount Packages
Microprocessor Compatible
TTL/CMOS Compatible
No User Trims
Extended Temperature Range Operation
Single Supply Operation Possible
APPLICATIONS
Process Control
Automatic Test Equipment
Automatic Calibration of Large System Parameters,
e.g., Gain/Offset
PRODUCT HIGHLIGHTS1. DAC-to-DAC Matching
Since all four DACs are fabricated on the same chip at the
same time, precise matching and tracking between the DACs
is inherent.
2. Single Supply Operation
The voltage mode configuration of the DACs allows the
AD7226 to be operated from a single power supply rail.
3. Microprocessor Compatibility
The AD7226 has a common 8-bit data bus with individual
DAC latches, providing a versatile control architecture for
simple interface to microprocessors. All latch enable signals
are level triggered.
4. Small Size
Combining four DACs and four op amps plus interface logic
into a 20-pin DIP or SOIC or a 20-terminal surface mount
package allows a dramatic reduction in board space require-
ments and offers increased reliability in systems using mul-
tiple converters. Its pinout is aimed at optimizing board
layout with all the analog inputs and outputs at one end of the
package and all the digital inputs at the other.
GENERAL DESCRIPTIONThe AD7226 contains four 8-bit voltage-output digital-to-
analog converters, with output buffer amplifiers and interface
logic on a single monolithic chip. No external trims are required
to achieve full specified performance for the part.
Separate on-chip latches are provided for each of the four D/A
converters. Data is transferred into one of these data latches
through a common 8-bit TTL/CMOS (5 V) compatible input
port. Control inputs A0 and A1 determine which DAC is loaded
when WR goes low. The control logic is speed-compatible with
most 8-bit microprocessors.
Each D/A converter includes an output buffer amplifier capable
of driving up to 5 mA of output current. The amplifiers’ offsets
are laser-trimmed during manufacture, thereby eliminating any
requirement for offset nulling.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V with dual supplies. The part is also speci-
fied for single supply operation at a reference of +10 V.
The AD7226 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
AD7226–SPECIFICATIONS
DUAL SUPPLYREFERENCE INPUT
DIGITAL INPUTS
DYNAMIC PERFORMANCE
NOTES
1Maximum possible reference voltage.
2Temperature ranges are as follows:
K Version: –40°C to +85°C
B Version: –40°C to +85°C
T Version: –55°C to +125°C
3Guanteed by design. Not production tested.
4Sample Tested at 25°C to ensure compliance.
(VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)
ORDERING GUIDENOTES
1To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for Military data sheet, for U.S. Standard Military
Drawing (SMD), see DESC drawing #5962–87802.E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
SINGLE SUPPLYREFERENCE INPUT
DIGITAL INPUTS
DYNAMIC PERFORMANCE
NOTESMaximum possible reference voltage.Temperature ranges are as follows:
K Version: –40°C to +85°C
B Version: –40°C to +85°C
T Version: –55°C to +125°CGuanteed by design. Not production tested.Sample Tested at 25°C to ensure compliance.Switching Characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
(VDD = +15 V 6 5%; VSS = AGND = DGND = O V; VREF = +10 V1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)
CIRCUIT INFORMATION
D/A SECTIONThe AD7226 contains four, identical, 8-bit, voltage mode
digital-to-analog converters. The output voltages from the con-
verters have the same polarity as the reference voltage allowing
single supply operation. A novel DAC switch pair arrangement
on the AD7226 allows a reference voltage range from +2 V to
+12.5 V.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. The simplified circuit diagram for one channel is
shown in Figure 1. Note that VREF (Pin 4) and AGND (Pin 5)
are common to all four DACs.
Figure 1.D/A Simplified Circuit Diagram
The input impedance at the VREF pin of the AD7226 is the par-
allel combination of the four individual DAC reference input
impedances. It is code dependent and can vary from 2 kΩ to in-
finity. The lowest input impedance (i.e., 2 kΩ) occurs when all
four DACs are loaded with the digital code 01010101. There-
fore, it is important that the reference presents a low output im-
pedance under changing load conditions. The nodal capacitance
at the reference terminals is also code dependent and typically
varies from 100 pF to 250 pF.
Each VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
VOUTX = DX VREF
where DX is fractional representation of the digital input code
and can vary from 0 to 255/256.
The source impedance is the output resistance of the buffer
amplifier.
OP AMP SECTIONEach voltage-mode D/A converter output is buffered by a unity
gain, noninverting CMOS amplifier. This buffer amplifier is
capable of developing +10 V across a 2 kΩ load and can drive
capacitive loads of 3300 pF. The output stage of this amplifier
consists of a bipolar transistor from the VDD line and a current
load to the VSS, the negative supply for the output amplifiers.
This output stage is shown in Figure 2.
The NPN transistor supplies the required output current drive
(up to 5 mA). The current load consists of NMOS transistors
which normally act as a constant current sink of 400 μA to VSS,
giving each output a current sink capability of approximately
400 μA if required.
The AD7226 can be operated single or dual supply resulting
Figure 2.Amplifier Output Stage
the current load ceases to act as a current sink and begins to act
as a resistive load of approximately 2 kΩ to AGND. This occurs
as the NMOS transistors come out of saturation. This means
that, in single supply operation, the sink capability of the ampli-
fiers is reduced when the output voltage is at or near AGND. A
typical plot of the variation of current sink capability with out-
put voltage is shown in Figure 3.
Figure 3.Variation of ISINK with VOUT
If the full sink capability is required with output voltages at or
near AGND (=0 V), then VSS can be brought below 0 V by 5 V
and thereby maintain the 400 μA current sink as indicated in
Figure 3. Biasing VSS below 0 V also gives additional headroom
in the output amplifier which allows for better zero code error
performance on each output. Also improved is the slew-rate
and negative-going settling-time of the amplifiers (discussed
later).
Each amplifier offset is laser trimmed during manufacture to
eliminate any requirement for offset nulling.
DIGITAL SECTIONThe digital inputs of the AD7226 are both TTL and CMOS
(5 V) compatible from VDD = +11.4 V to +16.5 V. All logic in-
puts are static protected MOS gates with typical input currents
AD7226
INTERFACE LOGIC INFORMATIONAddress lines A0 and A1 select which DAC will accept data
from the input port. Table I shows the selection table for the
four DACs with Figure 4 showing the input control logic. When
the WR signal is LOW, the input latches of the selected DAC
are transparent and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high the analog outputs remain
at the value corresponding to the data held in their respective
latches.
Table I.AD7226 Truth TableL = Low State, H = High State, X = Don’t Care
Figure 4.Input Control Logic
Typical Performance Characteristics
(TA = 258C, VDD = +15 V, VSS = –5 V)Figure 6.Channel-to-Channel Matching
Figure 7.Relative Accuracy vs. VREF
