AD7224 Fast Delivery |IC PHOENIX CO.,LIMITED

AD7224 ,LC2MOS 8-Bit DAC with Output AmplifiersGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7224 is a precision 8-bit voltage-output, digital-to- 1 ..
AD7224BQ ,LC2MOS 8-Bit DAC with Output AmplifiersSpecifications subject to change without notice.–2– REV. BAD72241(V = +15 V 6 5%; V = AGND = DGND ..
AD7224CQ ,LC2MOS 8-Bit DAC with Output Amplifiersspecifications T to T unless otherwise noted.)MIN MAXK, B, T L, C, U2 2Parameter Versions Versions ..
AD7224KN ,LC2MOS 8-Bit DAC with Output AmplifiersSPECIFICATIONS1(V = 11.4 V to 16.5 V, V = –5 V 6 10%; AGND = DGND = O V; V = +2 V to (V – 4 V) unle ..
AD7224KP ,LC2MOS 8-Bit DAC with Output Amplifiersspecifications T to T unless otherwise noted.)MIN MAXK, B, T L, C, U2 2Parameter Versions Versions ..
AD7224KR-1 ,LC2MOS 8-Bit DAC with Output AmplifiersGENERAL DESCRIPTION PRODUCT HIGHLIGHTSThe AD7224 is a precision 8-bit voltage-output, digital-to- 1 ..
ADC912A ,CMOS Microprocessor-Compatible 12-Bit A/D ConverterSPECIFICATIONSDD SS REFIN10 V; External f = 1.25 MHz; –40C to +85C applies to ADC912A/F unless ot ..
ADC-ET10BC , MONOLITHIC A/D CONVERTERS WITH THREE- STATE OUTPUTS
ADC-ET12BC , MONOLITHIC A/D CONVERTERS WITH THREE- STATE OUTPUTS
ADC-ET8BC , MONOLITHIC A/D CONVERTERS WITH THREE- STATE OUTPUTS
ADC-HX12BGC , 12-Bit, 8 and 20μsec Analog-to-Digital Converters
ADC-HX12BGC , 12-Bit, 8 and 20μsec Analog-to-Digital Converters

AD7224
LC2MOS 8-Bit DAC with Output Amplifiers
REV.BLC2MOS
8-Bit DAC with Output Amplifiers
FUNCTIONAL BLOCK DIAGRAMFEATURES
8-Bit CMOS DAC with Output Amplifiers
Operates with Single or Dual Supplies
Low Total Unadjusted Error:
Less Than 1 LSB Over Temperature
Extended Temperature Range Operation
mP-Compatible with Double Buffered Inputs
Standard 18-Pin DIPs, and 20-Terminal Surface
Mount Package and SOIC Package
PRODUCT HIGHLIGHTS
1. DAC and Amplifier on CMOS Chip
The single-chip design of the 8-bit DAC and output amplifier
is inherently more reliable than multi-chip designs. CMOS
fabrication means low power consumption (35 mW typical
with single supply).
2. Low Total Unadjusted Error
The fabrication of the AD7224 on Analog Devices Linear
Compatible CMOS (LC2MOS) process coupled with a novel
DAC switch-pair arrangement, enables an excellent total un-
adjusted error of less than 1 LSB over the full operating tem-
perature range.
3. Single or Dual Supply Operation
The voltage-mode configuration of the AD7224 allows opera-
tion from a single power supply rail. The part can also be op-
erated with dual supplies giving enhanced performance for
some parameters.
4. Versatile Interface Logic
The high speed logic allows direct interfacing to most micro-
processors. Additionally, the double buffered interface en-
ables simultaneous update of the AD7224 in multiple DAC
systems. The part also features a zero override function.
GENERAL DESCRIPTION
The AD7224 is a precision 8-bit voltage-output, digital-to-
analog converter, with output amplifier and double buffered
interface logic on a monolithic CMOS chip. No external trims
are required to achieve full specified performance for the part.
The double buffered interface logic consists of two 8-bit regis-
ters–an input register and a DAC register. Only the data held in
the DAC registers determines the analog output of the con-
verter. The double buffering allows simultaneous update in a
system containing multiple AD7224s. Both registers may be
made transparent under control of three external lines, CS, WR
and LDAC. With both registers transparent, the RESET line
functions like a zero override; a useful function for system cali-
bration cycles. All logic inputs are TTL and CMOS (5 V) level
compatible and the control logic is speed compatible with most
8-bit microprocessors.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. The part is also
specified for single supply operation using a reference of +10 V.
The output amplifier is capable of developing +10 V across a
2 kΩ load.
The AD7224 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
AD7224–SPECIFICATIONS
(VDD = 11.4 V to 16.5 V, VSS = –5 V 6 10%; AGND = DGND = O V; VREF = +2 V to (VDD – 4 V)1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)DUAL SUPPLY
NOTESMaximum possible reference voltage.Temperature ranges are as follows:
K, L Versions: –40°C to +85°C
AD7224
SINGLE SUPPLY
DIGITAL INPUTS
NOTESMaximum possible reference voltage.Temperature ranges are as follows:
AD7224KN, LN: 0°C to +70°C
AD7224BQ, CQ: –25°C to +85°C
AD7224TD, UD: –55°C to +125°CSee Terminology.Sample tested at 25°C by Product Assurance to ensure compliance.
Specifications subject to change without notice.
(VDD = +15 V 6 5%; VSS = AGND = DGND = O V; VREF = +10 V1 unless otherwise noted.
All specifications TMIN to TMAX unless otherwise noted.)
AD7224
ABSOLUTE MAXIMUM RATINGS1
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD
Digital Input Voltage to DGND . . . . . . .–0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .VSS, VDD
Power Dissipation (Any Package) to +75°C . . . . . . . .450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . .6 mW/°C
Operating Temperature
Commercial (K, L Versions) . . . . . . . . . . .–40°C to +85°C
Industrial (B, C Versions) . . . . . . . . . . . . .–40°C to +85°C
Extended (T, U Versions) . . . . . . . . . . . .–55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.The outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. Typically short circuit current to AGND is 60 mA.
ORDERING GUIDE
NOTES
1To order MIL-STD-883 processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7224 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP and SOIC(SOIC)(SOIC)
LCCCPLCC
VOUT = D • VREF
where D is a fractional representation of the digital input code
and can vary from 0 to 255/256.
OP-AMP SECTION
The voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. This buffer amplifier is
capable of developing +10 V across a 2 kΩ load and can drive
capacitive loads of 3300 pF.
The AD7224 can be operated single or dual supply resulting in
different performance in some parameters from the output am-
plifier. In single supply operation (VSS = 0 V = AGND) the sink
capability of the amplifier, which is normally 400 μA, is reduced
as the output voltage nears AGND. The full sink capability of
400 μA is maintained over the full output voltage range by tying
VSS to –5 V. This is indicated in Figure 2.
Figure 2.Variation of ISINK with VOUT
Settling-time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by VSS.
Additionally, the negative VSS gives more headroom to the out-
put amplifier which results in better zero code performance and
improved slew-rate at the output, than can be obtained in the
single supply mode.
DIGITAL SECTION
The AD7224 digital inputs are compatible with either TTL or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. To minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practi-
cally possible.
INTERFACE LOGIC INFORMATION
Table I shows the truth table for AD7224 operation. The part
contains two registers, an input register and a DAC register. CS
and WR control the loading of the input register while LDAC
and WR control the transfer of information from the input regis-
ter to the DAC register. Only the data held in the DAC register
will determine the analog output of the converter.
All control signals are level-triggered and therefore either or
TERMINOLOGY
TOTAL UNADJUSTED ERROR
Total Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy and zero code error.
Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. The LSB size will vary over the VREF range.
Hence the zero code error, relative to the LSB size, will increase
as VREF decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the VREF range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGH
Digital Feedthrough is the glitch impulse transferred to the out-
put due to a change in the digital input code. It is specified in
nV secs and is measured at VREF = 0 V.
FULL-SCALE ERROR
Full-Scale Error is defined as:
Measured Value – Zero Code Error – Ideal Value
CIRCUIT INFORMATION
D/A SECTION
The AD7224 contains an 8-bit voltage-mode digital-to-analog
converter. The output voltage from the converter has the same
polarity as the reference voltage, allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7224 al-
lows a reference voltage range from +2 V to +12.5 V.
The DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS single pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in
Figure 1.
Figure 1.D/A Simplified Circuit Diagram
The input impedance at the VREF pin is code dependent and can
vary from 8 kΩ minimum to infinity. The lowest input imped-
ance occurs when the DAC is loaded with the digital code
01010101. Therefore, it is important that the reference presents
a low output impedance under changing load conditions. The
nodal capacitance at the reference terminals is also code depen-
AD7224
Table I.AD7224 Truth Table
H = High State, L = Low State, X = Don’t Care.
All control inputs are level triggered.
The contents of both registers are reset by a low level on the
RESET line. With both registers transparent, the RESET line
functions like a zero override with the output brought to 0 V for
the duration of the RESET pulse. If both registers are latched, a
“LOW” pulse on RESET will latch all 0s into the registers and
the output remains at 0 V after the RESET line has returned
“HIGH”. The RESET line can be used to ensure power-up to
0 V on the AD7224 output and is also useful, when used as a
zero override, in system calibration cycles. Figure 3 shows the
input control logic for the AD7224.
Figure 3.Input Control Logic
Figure 4.Write Cycle Timing Diagram
SPECIFICATION RANGES
For the DAC to maintain specified accuracy, the reference volt-
age must be at least 4 V below the VDD power supply voltage.
This voltage differential is required for correct generation of bias
voltages for the DAC switches.
With dual supply operation, the AD7224 has an extended VDD
range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to
+16.5 V). Operation is also specified for a single VDD power
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that in order to achieve an output voltage range
of 0 V to +10 V, a nominal +15 V ± 5% power supply voltage is
required by the AD7224.
GROUND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. This is especially true in micropro-
cessor systems where digital noise is prevalent. The simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7224. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7224 AGND and
DGND pins (IN914 or equivalent).
Applying the AD7224
UNIPOLAR OUTPUT OPERATION
This is the basic mode of operation for the AD7224, with the
output voltage having the same positive polarity as VREF. The
AD7224 can be operated single supply (VSS = AGND) or with
positive/negative supplies (see op-amp section which outlines
the advantages of having negative VSS). Connections for the uni-
polar output operation are shown in Figure 5. The voltage at
VREF must never be negative with respect to DGND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. The code table for unipolar output
operation is shown in Table II.
Figure 5.Unipolar Output Circuit
Table III. Unipolar Code Table

Partno	Mfg	Dc	Qty	Available	Descript
AD7224	ADI	N/a	2	avai	LC2MOS 8-Bit DAC with Output Amplifiers