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AD7112BN-AD7112BR-AD7112CN-AD7112CR
LC2MOS LOGDAC Dual Logarithmic D/A Converter
REV.0
LC2MOS LOGDAC
Dual Logarithmic D/A Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Dynamic Range: 88.5 dB
Resolution: 0.375 dB
On-Chip Data Latches for Both DACs
Four-Quadrant Multiplication
+5 V Operation
Pin Compatible with AD7528
Low Power
APPLICATIONS
Audio Attenuators
Sonar Systems
Function Generators
GENERAL DESCRIPTIONThe LOGDAC® AD7112 is a monolithic dual multiplying D/A
converter featuring wide dynamic range and excellent DAC-to-
DAC matching. Both DACs can attenuate an analog input sig-
nal over the range 0 dB to 88.5 dB in 0.375 dB steps. It is
available in skinny 0.3" wide 20-pin DIPs and in 20-terminal
surface mount packages.
The degree of attenuation in either channel is determined by the
8-bit word applied to the onboard decode logic. This 8-bit word
is decoded into a 17-bit word which is then loaded into one of
the 17-bit data latches, determined by DACA/DACB. The fine
step resolution over the entire dynamic range is due to the use of
these 17-bit DACs.
The AD7112 is easily interfaced to a standard 8-bit MPU bus
via an 8-bit data port and standard microprocessor control lines.
It should be noted that the AD7112 is exactly pin-compatible
with the AD7528, an industry standard dual 8-bit multiplying
DAC. This allows an easy upgrading of existing AD7528 de-
signs which would benefit both from the wider dynamic range
and the finer step resolution offered by the AD7112.
The AD7112 is fabricated in Linear Compatible CMOS
(LC2MOS), an advanced, mixed technology process that com-
bines precision bipolar circuits with low power CMOS logic.
*. Patent No. 4521764.
LOGDAC is a registered trademark of Analog Devices, Inc.
PRODUCT HIGHLIGHTSDAC-to-DAC Matching: Since both of the AD7112 DACs
are fabricated at the same time on the same chip, precise
matching and tracking between the two DACs is inherent.Small Package: The AD7112 is available in a 20-pin DIP
and a 20-terminal SOIC package.Fast Microprocessor Interface: The AD7112 has bus inter-
face timing compatible with all modern microprocessors.
AD7112–SPECIFICATIONS(VDD = +5 V 6 5%; OUT A = OUT B = AGND = DGND = 0 V; VIN A = VIN B = 10 V.
Output amplifier AD712 except where noted. All specifications TMIN to TMAX unless otherwise noted.)NOTESTemperature range as follows: B, C Versions: –40°C to +85°C.Guaranteed by design, not production tested.The part will function with VDD = 5 V ± 10% with degraded performance.
Specifications subject to change without notice.
TIMING SPECIFICATIONS1DAC Select to WR Setup Time
DAC Select to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
NOTESTiming specifications guaranteed by design not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS1DC Supply Rejection Δ Gain/Δ VDD
Digital-to-Analog Glitch Impulse
Output Capacitance, COUT A, COUT B
Channel-to-Channel Isolation
NOTESGuaranteed by design, not production tested.
Specifications subject to change without notice.
(VDD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = O V; VIN A = VIN B = 10 V)
(VDD = +5 V 6 5%; 0UT A = OUT B = AGND = DGND = 0 V; VIN A =
VIN B = 10 V. Output amplifier AD712 except where noted.)
AD7112
ABSOLUTE MAXIMUM RATINGS*VDD to AGND or DGND . . . . . . . . . . . . . . . . . .–0.3 V, +7 V
AGND to DGND . . . . . . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . . .–0.3 V, VDD + 0.3 V
OUT A, OUT B to AGND . . . . . . . . . . .–0.3 V, VDD + 0.3 V
VIN A, VIN B to AGND . . . . . . . . . . . . . . . . . . . . . . . . .±25 V
VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . .±25 V
Operating Temperature Range
All Versions . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Power Dissipation, DIP . . . . . . . . . . . . . . . . . . . . . . . . . .1 W
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . .102°C/W
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . .+300°C
Power Dissipation, SOIC . . . . . . . . . . . . . . . . . . . . . . . . .1 W
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . .75°C/W
Lead Temperature (Soldering)
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Only
one Absolute Maximum Rating may be applied at any one time.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7112 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TERMINOLOGYRESOLUTION: Nominal change in attenuation when moving
between two adjacent codes.
MONOTONICITY: The device is monotonic if the analog out-
put decreases or remains constant as the wdigital code in-
creases.
FEEDTHROUGH ERROR: That portion of the input signal
which reaches the output when all digital inputs are high.
OUTPUT CAPACITANCE: Capacitance from OUT A or
OUT B to ground.
GAIN ERROR: Gain error results from a mismatch between
RFB (the feedback resistance) and the R-2R ladder resistance.
Its effect in a LOGDAC is to produce a constant additive at-
tenuation error in dB over the whole range of the DAC.
ACCURACY: The difference (measured in dB) between the
ideal transfer function as listed in Table I and the actual trans-
fer function as measured with the device.
DIGITAL-TO-ANALOG GLITCH IMPULSE: The amount
of charge injected from the digital inputs to the analog output
when the inputs change state. This is normally specified as the
area of the glitch in either pA-s or nV-s depending on whether
the glitch is measured as a current or voltage signal. Glitch im-
pulse is measured with VIN = AGND.
ORDERING INFORMATIONAD7112CN
AD7112BR
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
DIP/SOIC
AGND
OUT A
DGND
(MSB) DB7
DAC A/DAC B
DB6
DB5
DB4
RFB A
VIN A
OUT B
RFB B
VIN B
VDD
DB0 (LSB)
DB1
DB2
DB3WR
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATIONThe AD7112 consists of a dual 17-bit R-2R CMOS multiplying
D/A converter with extensive digital logic. Figure 1 shows a sim-
plified circuit of the D/A converter section of the AD7112. The
logic translates the 8-bit binary input into a 17-bit word which is
used to drive the D/A converter. Figure 2 shows a typical circuit
configuration for the AD7112.
The transfer function for the circuit of Figure 2 is given by: VO=±VIN×10exp±0.375N dB=±0.375N
where 0.375 is the step size (resolution ) in dB and N is the
input code in decimal for values 0 to 239. For 240 ≤ N ≤ 255
the output is zero. Table I gives the output attenuation relative
to 0 dB for all possible input codes.
VINA
RFB A
OUT A
AGNDFigure 1.Simplified D/A Circuit of 1/2 AD7112
Figures 16 and 17 give a pictorial representation of the specified
accuracy and monotonic ranges for all grades of the AD7112.
High attenuation levels are specified with less accuracy than low
attenuation levels. The range of monotonic behavior depends
upon the attenuation step size used. To achieve monotonic op-
eration over the entire 88.5 dB range, it is necessary to select in-
put codes so that the attenuation step size at any point is
consistent with the step size guaranteed for monotonic opera-
tion at that point.
Figure 2.Typical Circuit Configuration
Table I.Ideal Attenuation in dB vs. Input Code
AD7112
INTERFACE LOGIC INFORMATION
DAC SelectionBoth DAC latches share a common 8-bit port. The control in-
put DAC A/DAC B selects which DAC can accept data from
the input port.
Mode SelectionInputs CS and WR control the operating mode of the selected
DAC. See the Mode Selection Table below.
Write ModeWhen CS and WR are both low the DAC is in the write mode.
The input data latches of the selected DAC are transparent and
its analog output responds to activity on DB0–DB7.
Hold ModeThe selected DAC latch retains the data which was present on
DB0–DB7 just prior to CS and WR assuming a high state. Both
analog outputs remain at the values corresponding to the data in
their respective latches.
Mode Selection TableL = Low State, VIL; H = High State, VIH; X = Don’t Care.
tAS
DAC A/DAC B
tAH
VIH
tCStCH
DB0–DB7
NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF VDD. tR = tF = 20ns.
2. CONTROL TIMING MEASUREMENT REFERENCE LEVEL = (VIH + VIL) / 2Figure 3.Write Cycle Timing Diagram
DYNAMIC PERFORMANCEThe dynamic performance of the AD7112 will depend on the
gain and phase characteristics of the output amplifier, together
with the optimum choice of PC board layout and decoupling
components. Circuit layout is most important if the optimum
performance of the AD7112 is to be achieved. Most application
problems stem from either poor layout, grounding errors, or in-
appropriate choice of amplifier. Ensure that the layout of the
printed circuit board has the digital and analog lines separated
as much as possible. Take care not to run any digital track
alongside an analog signal track. Establish a single point analog
ground (star ground) separate from the logic system ground.
Place this ground as close as possible to the AD7112. Connect
all analog grounds to this star ground, and also connect the
AD7112 DGND to this ground. Do not connect any other digi-
tal grounds to this analog ground point. Low impedance analog
and digital power supply common returns are essential for low
noise and high performance of these converters, therefore the
foil width of these tracks should be as wide as possible. The use
of ground planes is recommended as this minimizes impedance
paths and also guards the analog circuitry from digital noise.
It is recommended that when using the AD7112 with a high
speed amplifier, a capacitor (C1) be connected in the feedback
path as shown in Figure 2. This capacitor which should be be-
tween 5 pF and 15 pF, compensates for the phase lag intro-
duced by the output capacitance of the D/A converter. Figures
4 and 5 show the performance of the AD7112 using the
AD712, a high speed, low cost BiFET amplifier, and the
OP275, a dual bipolar/JFET amplifier suitable for audio appli-
cations. The performance with and without the compensation
capacitor is shown in both cases. For operation beyond
250 kHz, capacitor C1 may be reduced in value. This gives an
increase in bandwidth at the expense of a poorer transient re-
sponse as shown in Figure 7. In circuits where C1 is not in-
cluded, the high frequency roll-off point is primarily determined
by the characteristics of the output amplifier and not the AD7112.
Feedthrough and accuracy are sensitive to output leakage cur-
rents effects. For this reason it is recommended that the operat-
ing temperature of the AD7112 be kept as close to +25°C as is
practically possible, particularly where the devices performance
at high attenuation levels is important. A typical plot of leakage
current vs. temperature is shown in Figure 11.
Some solder fluxes and cleaning materials can form slightly
conductive films which cause leakage effects between analog in-
put and output. The user is cautioned to ensure that the manu-
facturing process for circuits using the AD7112 does not allow
such films to form. Otherwise the feedthrough, accuracy and
maximum usable range will be affected.
STATIC ACCURACY PERFORMANCEThe D/A converter section of the AD7112 consists of a 17-bit
R–2R type converter. To obtain optimum static performance at
this level of resolution it is necessary to pay great attention to
amplifier selection, circuit grounding, etc.
Amplifier input bias current results in a dc offset at the output
of the amplifier due to current flowing in the feedback resistor
RFB. It is recommended that amplifiers with input bias currents
