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AD71028-AD71028JST
Dual Digital BTSC Encoder with Integrated DAC
Dual Digital BTSC Encoder
with Integrated DAC
Rev. 0
FEATURES
2 complete independent BTSC encoders
Pilot tone generator
Includes subcarrier modulation
Typical 23 dB to 27 dB separation, 16 dB minimum
Signal bandwidth of 14 kHz
Phat-StereoTM algorithm for stereo image enhancement
Dialog enhancement function for playing wide dynamic
range video sources over built-in TV speakers
Includes L-R dual-band compressor
SPI® port for control of modes and effects
Differential output for optimum performance
DAC performance: 92 dB dynamic range, –92 dB THD+N
Output level control for setting aural carrier deviation
Flexible serial data port with right-justified, left-justified, 2S compatible, and DSP serial port modes
48-lead LQFP plastic package
APPLICATIONS
Digital set-top box BTSC encoder
PRODUCT OVERVIEW The AD71028 dual digital BTSC encoder provides two complete
digital BTSC encoder channels, including the pilot-tone
generation and subcarrier mixing functions. Two built-in high
performance DACs are provided to output the BTSC baseband
composite signal. The output of the AD71028 can be connected
with minimal external circuitry to the input of a 4.5 MHz aural
FM modulator.
In addition to the BTSC encoders, the AD71028 also includes a
stereo image enhancement function, Phat Stereo, to increase the
sense of spaciousness available from closely spaced TV
loudspeakers. A dialog enhancement algorithm is also included
to solve the problem of playing wide dynamic range sources
over limited-performance TV speakers and amplifiers. An
extensive SPI port allows click-free parameter updates.
The AD71028 also includes ADI’s patented multibit Σ-∆ DAC
architecture. This architecture provides 92 dB SNR and THD+N
of –92 dB.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INPUTA
SERIALINPUTB
SPII/O
GROUP
BTSC
ENCODED
OUTPUTA
BTSC
ENCODED
OUTPUTB
ANALOG
BIAS
CLOCK
SIGNAL
GROUPFigure 1. Functional Block Diagram
TABLE OF CONTENTS Specifications.....................................................................................3
DAC Analog Performance...........................................................3
BTSC Encoder Performance.......................................................3
Digital I/O.....................................................................................3
Power..............................................................................................4
Temperature Range......................................................................4
Digital Timing...............................................................................4
Absolute Maximum Ratings............................................................5
Pin Configuration and Functional Descriptions..........................6
Features..............................................................................................8
Pin Functions................................................................................8
Signal Processing............................................................................10
Background of BTSC.................................................................10
Performance Factors..................................................................10
Separation Alignment................................................................10
Phase Linearity of the External Analog Filter.........................11
Input Levels.................................................................................11
Clock Relationships....................................................................11
SPI Port............................................................................................12
Overview.....................................................................................12
SPI Address Decoding...............................................................12
Parameter RAM..........................................................................13
Control Register.........................................................................13
Output Level Register................................................................13
Stereo Enhancement Register...................................................13
Dialog Enhancement Register..................................................13
SPI Read/Write Data Formats..................................................14
Initialization................................................................................14
Serial Data Input Port................................................................14
Analog Output Section..................................................................16
Outline Dimensions.......................................................................17
Ordering Guide..........................................................................17
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED Supply Voltages (AVDD, DVDD) 5.0 V
Ambient Temperature 25°C
Input Clock 12.288 MHz
Input Signal 1 kHz, 0 dBFS
Input Sample Rate 48 kHz
Measurement Bandwidth 20 Hz to 14 kHz
Word Width 24 Bits
Load Capacitance 50 pF
Input Voltage HI 2.4 V
Input Voltage LO 0.4 V
DAC ANALOG PERFORMANCE
Table 1. Measurement of encoded BTSC signal, not a measurement of end-to-end system.
BTSC ENCODER PERFORMANCE
Table 2. These specifications are measured with a –25 dB, 1 kHz input signal.
DIGITAL I/O
Table 3.
POWER
Table 4.
TEMPERATURE RANGE
Table 5.
DIGITAL TIMING
Table 6. ABSOLUTE MAXIMUM RATINGS
Table 7. AD71028 Stress Ratings
Table 8. Package Characteristics (48-Lead LQFP) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
NC = NO CONNECT
AD71028
TOP VIEW
(Not to Scale)
DIV1_PB
DIV2_PB
AGND
OUTB–
OUTB+
AVDD
AGND
DGND
DVDD
ODVDD
COUT
CDATA
AVDD
OUTA+
OUTA–
AGND
DOUBLE
CCLK
CLATCH
DGND
ESETB
DATA_
BCLK_
LRCLK_
DATA_
BCLK_
LRCLK_
IV1_PA
MCLK_
PLL_PBDV
DGND
MCLK_
PLL_PACLK2
CLK2
FILTCAPRE
FCAP
04482-0-002Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP)
Table 9. Pin Function Descriptions
FEATURES The AD71028 is comprised of two independent digital-input
BTSC encoders. The two processors allow two completely
asynchronous BTSC channels to be encoded, each with its own
clock signals. Figure 1 shows the block diagram of the device.
Signal processing parameters are stored in a 256-location
parameter RAM, which is initialized on power-up by an internal
boot ROM. The values stored in the parameter RAM control all
the filter coefficients, mixing, and dynamics processing code
used in the BTSC algorithm.
The AD71028 has an SPI port that supports complete read/
write capability of the parameter RAM, as well as a control port
and several other registers that allow the various signal proces-
sing parameters to be controlled. The AD71028 can run as a
standalone processor without SPI control.
The AD71028 has a very flexible serial data input port that
allows for glueless interconnection to a variety of signal sources.
The AD71028 can be configured in left-justified, I2S, right-
justified, or DSP serial port compatible modes. It can support
16, 20, and 24 bits in all modes. The AD71028 accepts serial
audio data in MSB first, twos complement format.
The AD71028 operates from a single 5 V power supply. It is fab-
ricated on a single monolithic integrated circuit and is housed
in a 48-lead LQFP package for operation over the 0°C to 70°C
temperature range.
PIN FUNCTIONS Pin names and functions are shown below. Note that pins with a
“_PA” designation are connected to Processor A, while those
with a “_PB” designation are connected to Processor B. All input
pins have a logic threshold compatible with TTL input levels,
and may therefore be used in systems with 3.3 V logic. All
digital output levels are controlled by the ODVDD pin, which
may range from 2.7 V to 5.5 V, for compatibility with a wide
range of external devices.
LRCLK_PA, LRCLK_PB Left/right clocks for framing the input data. The interpretation
of the LRCLK changes according to the serial mode, set by
writing to the control registers.
BCLK_PA, BCLK_PB Serial bit clocks for clocking in the serial data. The interpreta-
tion of BCLK changes according to the serial mode, which is set
by writing to the control registers.
SDATA_PA, SDATA_PB Serial data inputs to each processor. The serial format is selected
by writing to Bits <3:0> of the control registers.
MCLK_PA, MCLK_PB Master clock inputs. The master clock frequency must be either
256 × fS or 512 × fS, where fS is the input sampling frequency. If
the DOUBLE pin is high, an internal clock doubler is used to
take a 256 × fS input clock and produce the 512 × fS internal
clock required by the DSP core. If the DOUBLE pin is low, the
frequency of the input clock must be set to 512 × fS. In case
these clock signals are not available, a simple external PLL may
be used to generate the master clock signals. On-chip dividers
are provided to simplify this task.
CDATA Serial data in for the SPI control port. See the SPI Port section
for more information on SPI port timing.
COUT Serial data output. This is used for reading back registers and
memory locations. It is three-stated when an SPI read is not
active. See the SPI Port section for more information on SPI
port timing.
CCLK SPI bit-rate clock. This pin may either run continuously or be
gated in between SPI transactions. See the SPI Port section for
more information on SPI port timing.
CLATCH SPI latch signal. This signal must go low at the beginning of an
SPI transaction and high at the end of a transaction. Each SPI
transaction may take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the
beginning of the SPI transaction. Detailed SPI timing informa-
tion can be found in the SPI Port section.
RESETB Active-low reset signal. After RESETB transitions from low to
high, the AD71028 goes through an initialization sequence
where the parameter RAMs are initialized with the contents of
the on-board boot ROM. All SPI registers are set to 0, and the
data RAMs are also zeroed. The initialization is complete after
1024 MCLK cycles. New values should not be written to the SPI
port until the initialization is complete.
DOUBLE When this pin is set high, the internal clock doubler is turned
on so a 256 × fS MCLK can be input to the AD71028.
PLL_PA, PLL_PB PLL clock input pins for Processor A and Processor B. These
pins are connected to an internal divide-by-1024 circuit (or
divide-by-512 if DOUBLE is high). This makes it possible to use
an inexpensive external PLL to generate the system clock. If an
external PLL is used, this pin should also be connected to the
CLK27_PA, CLK27_PB Input pins to the divide-by-1125 block. If an external PLL is
used to generate the audio master clock, the 27 MHz video
master clock may be applied to these pins where it is divided by
1125 to produce a 24 kHz feedback clock to the external PLL
phase detector.
DIV1_PA, DIV1_PB Output of divide-by-1024 circuit. Divides the master clock
signal by 1024 (or 512 when DOUBLE is asserted). Used to
interface to external PLL.
DIV2_PA, DIV2_PB Output of divide-by-1125 circuit. Divides the master-clock
signal by 1125. Used to interface to external PLL. The output
signal is a pulse with a duration of one master clock, and should
therefore be used with edge-triggered phase detectors.
REFCAP Analog reference voltage input. The nominal REFCAP input
voltage is 2.5 V; the analog gain scales directly with the voltage
on this pin. Any ac signal on this pin will cause distortion, and
therefore a large decoupling capacitor should be used to ensure
that the voltage on REFCAP is clean. The input impedance of
REFCAP is greater than 1 MΩ.
FILTCAP Filter cap point. This pin is used to reduce the noise on an
internal biasing point in order to provide the highest
performance. It may not be necessary to connect this pin,
depending on the quality of the layout and grounding used in
the application circuit.
DVDD Digital VDD for core. 5 V nominal.
ODVDD Digital VDD for all digital outputs. Variable from 2.7 V to 5.5 V.
DGND Digital ground.
AVDD Analog VDD. 5 V nominal. Bypass capacitors should be placed
close to the pins and connected directly to the analog ground
plane.
AGND Analog ground.
OUTA+, OUTA– Differential analog outputs for Processor A. The nominal output
voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This
level may be adjusted by writing to SPI location 258.
OUTB+, OUTB– Differential analog outputs for Processor B. The nominal output
voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This
level may be adjusted by writing to SPI location 770.
SIGNAL PROCESSING TO
DAC
Fh PILOT
L– R
04482-0-003Figure 3. Signal Processing Flow
BACKGROUND OF BTSC BTSC is the name of the standard for adding stereo audio
capability to the US television system. It is in many ways similar
to the algorithm used for FM stereo broadcasts, with the
addition of a sophisticated compressor circuit to improve the
signal-to-noise ratio.
The processing of mono (L = R) signals is unchanged from the
original pre-BTSC system in order to maintain compatibility
with non-BTSC TV receivers. The L + R signal is applied to a
75 µs pre-emphasis filter, and is then applied to a 4.5 MHz FM
modulator, which is later added into the video signal to create a
composite video signal.
Stereo capability is added by taking the L–R signal, applying it
to a 2-band dynamic compressor, and then multiplying this
signal by a carrier signal at twice the horizontal scanning rate
(Fh), or about 2 × 15.734 kHz. This multiplication is known as
double-sideband suppressed-carrier modulation, and it
effectively translates the compressed L – R spectrum up in
frequency so that it sits above the audio band (Figure 3).
In order for the receiver to recover this L – R signal, a pilot tone
at the horizontal rate is added to the signal. The receiver has a
PLL that locks to this pilot and generates a signal at the carrier
frequency. This signal is then used to multiply the composite
BTSC-encoded signal, which translates this component back
down to baseband. The L – R signal is then applied to a 2-band
expander, which is the complement to the earlier compressor
step. Once the L + R and L – R signals are recovered, a simple
addition/subtraction circuit (sometimes referred to as the
“matrix”) can be used to recover the L and R signal.
Since the pilot tone is added at 15.734 kHz, it is necessary to
reduce the signal’s bandwidth so that audio signals cannot
interfere with the pilot tone. In the AD71028, the bandwidth is
limited to 14 kHz; above this frequency, the response decays
very rapidly.
PERFORMANCE FACTORS In order to maintain good separation between left and right, it is
necessary to closely match the filtering and companding stan-
dards set forth in the standard (FCC OET60). Even small errors
can result in poor performance. The AD71028 has been pro-
grammed to match these standards as accurately as possible.
Separation typically ranges from 30 dB at frequencies below
1 kHz to 15 dB at 14 kHz. Measuring these numbers can be
difficult as significant differences exist between many so-called
reference decoders, which are all implemented with analog
components.
SEPARATION ALIGNMENT The BTSC encoder outputs are all specified in terms of the
deviation of the FM 4.5 MHz carrier. For the AD71028, a digital
input level of 0 dB (mono signal) should cause a carrier
deviation of ±25 kHz without the 75 µs pre-emphasis filter. In
practice, the pre-emphasis filter may be left in for this adjust-
ment, as long as the frequency is low enough to not be affected
by the pre-emphasis filter. It is critical to maintain the proper
gain relationship between the BTSC encoder and the 4.5 MHz
FM modulator. A common mistake is to assume that changing
the gain between the BTSC encoder output and the FM
modulator input has the same effect as changing the audio
input level going in to the BTSC encoder. The presence of a
complicated 2-band nonlinear dynamics processor means that
the encoder output must be connected to the decoder input
(through the FM modulation/demodulation process) with a
known gain. If this gain is changed, the separation will
significantly suffer.
When measuring the AD71028 on the bench, it is possible to
use a BTSC reference decoder box, so that the FM modulation/
demodulation process may be skipped. These units have a
method of adjusting the input voltage sensitivity to achieve best
separation. The output level of the AD71028 can also be
adjusted over a wide range using either the SPI control port or
by adjusting the values of the components used in the external
analog low-pass filter that is between the BTSC encoder output
and the input to the FM modulator.
