AD7013ARS Fast Delivery |IC PHOENIX CO.,LIMITED

AD7013ARS ,CMOS TIA IS-54 Baseband Receive PortSPECIFICATIONSV 1.23 Volts typREFReference Accuracy ±5 % maxReference Impedance 20 kΩ typLOGIC INPU ..
AD704 ,Quad Picoampere Input Current Bipolar Op AmpCHARACTERISTICSOffset Voltage 250 130 150 µ VT –T 400 200 250 µ VMIN MAX2Input Bias Current 500 300 ..
AD704AR ,Quad Picoampere Input Current Bipolar Op AmpFEATURESCONNECTION DIAGRAMSHigh DC Precision14-Pin Plastic DIP (N) 16-Pin SOIC75 mV max Offse ..
AD704AR ,Quad Picoampere Input Current Bipolar Op AmpCHARACTERISTICSVoltage Swing R = 10 kΩLOAD T –T ±13 ±14 ± 13 ±14 ±13 ±14 VMIN MAXCurrent Short Circ ..
AD704AR-16 ,Quad Picoampere Input Current Bipolar Op AmpCHARACTERISTICSOffset Voltage 250 130 150 µ VT –T 400 200 250 µ VMIN MAX2Input Bias Current 500 300 ..
AD704AR-16 ,Quad Picoampere Input Current Bipolar Op Ampapplications.The AD704 is an excellent choice for use in low frequency active 1filters in 12- and 1 ..
ADC1175CIMTC ,8-Bit, 20MHz, 60mW A/D ConverterFeaturesn Internal Sample-and-Hold FunctionThe ADC1175 is a low power, 20 Msps analog-to-digitalcon ..
ADC11DL066CIVS ,Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal ReferenceFeaturesn Single +3.3V supply operationThe ADC11DL066 is a dual, low power monolithic CMOSanalog-to ..
ADC11L066CIVY ,11-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-HoldFeaturesn Single supply operationTheADC11L066isamonolithicCMOSanalog-to-digitalcon-verter capable o ..
ADC12010CIVY ,12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-HoldFeaturesn Internal sample-and-holdTheADC12010 is a monolithic CMOS analog-to-digital con-verter cap ..
ADC12020CIVY ,12-Bit, 20 MSPS, 185mW A/D Converter with Internal Sample-and-HoldFeaturesn Internal sample-and-holdTheADC12020 is a monolithic CMOS analog-to-digital con-verter cap ..
ADC12030CIWM ,Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/HoldBlock Diagram01135401Connection Diagrams16-Pin Wide Body 20-Pin Wide BodySO Packages SO Packages011 ..

AD7013ARS
CMOS TIA IS-54 Baseband Receive Port
REV. A
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
CMOS
TIA IS-54 Baseband Receive Port
GENERAL DESCRIPTION
The AD7013 is a complete low power, CMOS, TIA IS-54 base-
band receive port with single +5 V power supply. The part is
designed to perform the baseband conversion of I and Q
waveforms in accordance with the American (TIA IS-54)
Digital Cellular Telephone system.
The receive path consists of two high performance sigma-delta
ADCs, each followed by a FIR digital filter. A primary and
auxiliary set of IQ differential analog inputs are provided,
where either can be selected as inputs to the sigma-delta
ADCs. Also, a choice of two frequency responses are available
for the receive FIR filters; a Root-Raised-Cosine filter for
digital mode or a brick wall response for analog mode.
Differential analog inputs are provided for both I and Q
channels. On-chip calibration logic is also provided to remove
either on-chip offsets or remove system offsets. A 16-bit serial
interface is provided, interfacing easily to most DSPs. The
receive path also provides a means to vary the sampling
instant, giving a resolution to 1/32 of a symbol interval.
The auxiliary section provides two 8-bit DACs and one 10-bit
DAC for functions such as automatic gain control (AGC),
automatic frequency control (AFC) and power amplifier
control.
As it is a necessity for all digital mobile systems to use the
lowest possible power, the device has receive and auxiliary
power down options. The AD7013 is housed in a space
efficient 28-pin SSOP (Shrink Small Outline Package).
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Single +5 V Supply
Receive Channel
Differential or Single-Ended Analog Inputs
Auxiliary Set of Analog I & Q Inputs
Two Sigma-Delta A/D Converters
Choice of Two Digital FIR Filters
Root-Raised-Cosine Rx Filters, α = 0.35
Brick Wall FIR Rx Filters
On-Chip or User Rx Offset Calibration
ADC Sampling Vernier
Three Auxiliary DACs
On-Chip Voltage Reference
Low Active Power Dissipation, Typical 45 mW
Low Sleep Mode Power Dissipation, <50 μW
28-Pin SSOP
APPLICATIONS
American TIA Digital Cellular Telephony
American Analog Cellular Telephony
Digital Baseband Receivers
(VAA = VDD = +5 V ± 10%; AGND = DGND = 0 V; fMCLK = 6.2208 MHz;
TA = TMIN to TMAX, unless otherwise noted)
AD7013–SPECIFICATIONS1
LOGIC INPUTS
LOGIC OUTPUTS
NOTESOperating temperature ranges as follows: A version: –40°C to +85°C.SNR calculation includes noise and distortion components.See Terminology.Sampled tested only.Measured while the digital inputs are static and equal to 0 V or VDD.With all sections powered down, IDD is proportional to the capacitive load on DxCLK. For example, IDD is typically 1.7 mA with 80 pF load and 600 μA with
10 pF load.
Specifications subject to change without notice.
AD7013
AD7013
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VAA, VDD to GND.........................–0.3 V to +7 V
AGND to DGND........................–0.3 V to +0.3 V
Digital I/O Voltage to DGND...........–0.3 V to VDD +0.3 V
Analog I/O Voltage to AGND...........–0.3 V to VDD +0.3 V
Operating Temperature Range
Industrial (A Version)...................–40°C to +85°C
Storage Temperature Range...............–65°C to +150°C
Maximum Junction Temperature...................+150°C
SSOP θJA Thermal Impedance....................+122°C/W
Lead Temperature Soldering
Vapor Phase (60 sec)...........................+215°C
Infrared (15 sec)..............................+220°C
NOTESStresses above those listed under “Absolute Maximum Ratings” may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions extended periods may affect device reliability.
TERMINOLOGY
Sampling Rate
This is the rate at which the modulators on the receive channels
sample the analog input.
Output Rate
This is the rate at which data words are made available at the
RxDATA pin.
Integral Nonlinearity
This is the maximum deviation from a straight line passing through
the endpoints of the DAC or ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the DAC or ADC.
Dynamic Range
Dynamic Range is the ratio of the maximum rms input signal to the
rms noise of the converter, expressed logarithmically, in decibels
(dB = 20 log10 [ratio]).
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the receive channel. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent upon the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal to (noise + distortion) ratio for a sine
wave is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Settling Time
This is the digital filter settling time in the AD7013 receive section.
Bias Offset Error
This is the amount of offset in the receive channel ADC when the
differential inputs are tied together.
Receive Error Vector Magnitude
This is a measure of the rms signal error vector introduced by the
receive Root-Raised Cosine digital filter. This is measured by
applying an ideal transmit signal (i.e., an ideal π/4 DQPSK
modulator and an ideal transmit Root-Raised Cosine filter) to the
receive channel and measuring the resulting rms error vector.
Offset Vector Magnitude
This is a measure of the offset vector introduced by the AD7013 as
illustratedinthefigurebelow. Theoffsetvectoriscalculatedsoasto
minimize the rms error vector for each of the constellation points.
PIN CONFIGURATION
ORDERING GUIDE
*RS = SSOP.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this device features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom-
PIN FUNCTION DESCRIPTIONS
SSOP Pin
NumberMnemonicFunction
POWER SUPPLY
1VAAPositive Power Supply for Analog section. A 0.1 μF decoupling capacitor should be
connected between this pin and AGND.VDDPositive Power Supply for Digital section. A 0.1 μF decoupling capacitor should be
connected between this pin and DGND. Both VAA and VDD should be externally
tied together.
10, 25, 27AGNDAnalog Ground.DGNDDigital Ground. Both AGND and DGND should be externally tied together.
ANALOG SIGNAL AND REFERENCEBYPASSReference Decoupling Output. A 10 nF decoupling capacitor should be connected
between this pin and AGND.
2, 4IRx, IRxDifferential Analog Inputs for the I receive channel. These are the primary receive
analog inputs and are selected by setting CR12 to a zero in the command register.
6, 8QRx, QRxDifferential Analog Inputs for the Q receive channel. These are the primary receive
analog inputs and are selected by setting CR12 to a zero in the command register.
3, 5AUX IRx, AUX IRxAuxiliary Differential Analog Inputs for the I receive channel. The Auxiliary inputs
are selected by setting CR12 to a one in the command register.
7, 9AUX QRx, AUX QRxAuxiliary Differential Analog Inputs for the Q receive channel. The Auxiliary inputs
are selected by setting CR12 to a one in the command register.AUX DAC1Analog output from the 10-bit auxiliary DAC.
3, 22AUX DAC2, AUX DAC3Analog outputs from the 8-bit auxiliary DACs.FS ADJUSTAn external resistor is connected from this pin to ground to determine the full-
scale current for AUX DAC1, AUX DAC2, and AUX DAC3.
SERIAL INTERFACE AND CONTROLMCLKMaster Clock, Digital Input. When operating in IS-54 Digital mode this pin should
be driven by a 6.2208 MHz CMOS compatible clock source and 5.12 MHz clock
source for Analog Mode.DxCLKTransmit Clock, Digital Output. This is a continuous clock equal to MCLK/2 which
can be used to clock the serial port of a DSP.FRAME INDigital Input. This is used to frame the clocking in of 16-bit words for the control
registers serial interface.DATA INDigital Input. Transmit Serial Data, digital input. This pin is used to clock in
data for the serial interface on the rising edge of DxCLK.FRAME OUTDigital Output. This output represents a buffered version of FRAME IN and is
controlled by the MODE1 pin. This pin can be used to daisy chain the
FRAME IN signal.MODE1Digital Input. This pin determines the state of FRAME OUT. When MODE1 is high,
FRAME IN is buffered and made available on FRAME OUT.
When MODE1 is low, FRAME OUT is in 3-STATE.
RECEIVE INTERFACE AND CONTROLRxCLKOutput Clock for the receive section interface.RxFRAMESynchronization output for framing I and Q data at the receive interface.RxDATAReceive Data, digital output. I and Q data are available at this pin via a 16-bit serial
interface. Data is valid on the falling edge of RxCLK. I and Q data are clocked out
as two 16-bits words, with the I word being clocked first. The last bit in each 16-bit
word is a I/Q flag bit, indicating whether that word is an I word or a Q word.
AD7013
NOTEt14 is derived from the measured time taken by the FRAME OUT pin to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the Timing Characteristics is the
(VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V,
fMCLK = 6.2208 MHz; TA = TMIN to TMAX, unless otherwise noted)CONTROL SERIAL INTERFACE TIMING1
Figure 2.16-Bit Serial Interface for Writing to the AD7013 Internal Registers
TO OUTPUT PIN
Figure 1.Load Circuit for Digital Outputs
RECEIVE SECTION TIMINGAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND = 0 V,fMCLK = 6.2208 MHz;
TA = TMIN to TMAX, unless otherwise noted)
Figure 3.Receive Serial Interface Timing with 4× Sampling of the Symbol Rate (CR10 = 1)
t17
t20
t21
t23
t24
AD7013
(VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V, fMCLK = 6.2208 MHz;
TA = TMIN to TMAX, unless otherwise noted)RECEIVE SECTION TIMINGt37 is derived from the measured time taken by the receive channel outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured
number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the
Timing Characteristics is the true relinquish time of the part and as such is independent of external loading capacitance.
Figure 4.Receive Serial Interface Timing with 2× Sampling of the Symbol Rate (CR10 = 0)
Figure 5.Receive Serial Interface 3-State Timing
AUX DAC2
AUX DAC3
RESET
6-Bit LOAD
N/A
Table I.Description and Address Map for AD7013 Internal Registers
Figure 6.AD7013 Registers
AD7013
Figure 7.Internal AD7013 Registers
Table II.Command Register One

Partno	Mfg	Dc	Qty	Available	Descript
AD7013ARS	AD	N/a	1110	avai	CMOS TIA IS-54 Baseband Receive Port