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AD7010ARS
CMOS JDC p/4 DQPSK Baseband Transmit Port
CMOSJDC p/4 DQPSK Baseband Transmit PortREV.B
GENERAL DESCRIPTIONThe AD7010 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion ofI and Q transmit
waveforms in accordance with the Japanese Digital Cellular
Telephone system.
The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the Root Raised
Cosine filters, generates I and Q data in response to the transmit
data stream. The AD7010 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.
Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7010 generates differential analog outputs for
both the I and Q signals.
As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has power down options. The
AD7010 is housed in a space efficient 24-pin SSOP (Shrink
Small Outline Package).
FEATURES
Single +5 V Supply
On-Chip p/4 DQPSK Modulator
Root-Raised-Cosine Tx Filters, a = 0.5
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Very Low Power Dissipation, 30 mW typ
Power Down Mode < 5 mA
On-Chip Voltage Reference
24-Pin SSOP
APPLICATIONS
Japanese Digital Cellular Telephony
FUNCTIONAL BLOCK DIAGRAM
AD7010–SPECIFICATIONS1(VAA = VDD = +5 V 6 10%; Test = AGND = DGND = 0 V; fMCLK = 2.688 MHz;
Power = VDD. All specifications are TMIN to TMAX unless otherwise noted.)NOTESOperating temperature ranges as follows: A Version: –40°C to +85°C.See Terminology.Measured in continuous transmission and Burst transmission with the I and Q channels ramping up and down at the beginning and end of each burst.Measured while the digital inputs to the transmit interface are static and equal to 0 V or VDD.
Specifications subject to change without notice.
ORDERING GUIDE
Figure 1.
Figure 2.
MASTER CLOCK TIMING
ABSOLUTE MAXIMUM RATINGS*(TA = +25°C unless otherwise noted)
VDD Tx, VDD Rx to AGND . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . .–0.3 V to VDD to + 0.3 V
Analog I/O Voltage to AGND . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .+150°C
SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . .+122°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table I.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7010 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(VAA = VDD = +5 V 6 10%; AGND = DGND = O V. All specifications are TMIN to TMAX unless
otherwise noted.)
AD7010
TRANSMIT SECTION TIMINGFigure 5.Transmit Timing at the Start of a Tx Burst
Figure 6.Transmit Timing at the End of a Tx Burst
(VAA = VDD = +5 V 6 10%; AGND = DGND = 0 V, fMCLK = 2.688 MHz. All specifications are
TMIN to TMAX unless otherwise noted.)
PIN FUNCTION DESCRIPTION
SSOP Pin
NumberMnemonicFunction
POWER SUPPLYVAAPositive power supply for analog section.
5VDDPositive power supply for digital section, both supplies should be externally tied together.
14, 18, 23 AGNDAnalog ground for transmit section. DGNDDigital ground for transmit section, both grounds should be externally tied together.
ANALOG SIGNAL AND REFERENCEBYPASS Reference decoupling output. A decoupling capacitor should be connected between this pin a
and AGND.
16, 17ITx, ITx Differential analog outputs for the I channel, representing true and complementary outputs
of the I waveform.
21, 20QTx, QTx Differential analog outputs for the Q channel, representing true and complementary outputs
of the Q waveform.
TRANSMIT INTERFACE AND CONTROLMCLKMaster clock, digital input. This pin should be driven by a 2.688 MHz CMOS compatible
clock source in digital mode.TxCLKThis is a digital output, transmit clock. This may be used to clock in transmit data at 42 kHz.TxDATAThis is a digital input. This pin is used to clock in transmit data on the falling edge of TxCLK
at a rate of 42 kHz.BINThis is a digital input. This input is used to initiate the ramping up (BIN high) or down (BIN
low) of the I and Q waveforms.BOUTBurst out, digital output. This is the BIN input delayed by the pipeline delay, both digital and
analog, of the AD7010. This can be used to turn on and off the RF amplifiers in synchroniza-
tion with the I and Q waveforms.POWERTransmit sleep mode, digital input. When this goes low, the AD7010 goes into sleep mode,
drawing minimal current. When this pin goes high, the AD7010 is brought out of sleep mode
and initiates a self-calibration routine to eliminate the offset between ITx & ITx and the offset
between QTx & QTx.READYTransmit ready, digital output. This output goes high once the self-calibration routine is complete.
9, 11MODE1,Mode control, digital inputs. These are used to enter the AD7010 into three different
MODE2operating modes, see Table I.
8, 10, 15, 22NCNo Connects. These pins are no connects and should not be used as routes for other circuit signals.
SSOP PIN CONFIGURATION
AD7010
TERMINOLOGY
Error Vector MagnitudeThis is a measure of the rms error vector introduced by the
AD7010 where signal error vector is defined as the rms devia-
tion of a transmitted symbol from its ideal position, as illustrated
in Figure 7, when filtered by an ideal RRC filter.
Gain Matching Between ChannelsThis is the Gain matching between the I and Q outputs, mea-
sured when transmitting all zeros.
Offset Vector MagnitudeThis is a measure of the offset vector introduced by the AD7010
as illustrated in Figure 7. The offset vector is calculated so as to
minimize the rms error vector for each of the constellation points.
Output Signal Range and Differential Output RangeThe output signal range is the output voltage swing and dc bias
level for each of the analog outputs. The Differential Output
Range is the difference between ITx and ITx for the I channel
and the difference between QTx and QTx for the Q Channel.
JDC Spurious PowerThis is the rms sum of the spurious power measured at multi-
ples of 25 kHz, in a rectangular window of ±10.5 kHz, relative
to twice the rms power in a RRC window in the 0 kHz to
10.5 kHz band.
Signal Vector MagnitudeThis is the radius of the IQ constellation diagram as illustrated
in Figure 7.
Figure 7.
CIRCUIT DESCRIPTION
TRANSMIT SECTIONThe transmit section of the AD7010 generates π/4 DQPSK I
and Q waveforms in accordance with JDC specification. This is
accomplished by a digital π/4 DQPSK modulator, which in-
cludes the Root-Raised Cosine filters (α = 0.5), followed by two
10-bit DACs and on-chip reconstruction filters. The π/4
DQPSK (Differential Quadrature Phase Shift Keying) digital
modulator generates 10-bit I and Q data in response to the
transmit data stream. The 10-bit I and Q DACs are filtered by
on-chip reconstruction filters, which also generate differential
analog outputs for both I and Q channels.
p/4 DQPSK Modulator
Table II.Figure 8 shows the functional block diagram of the π/4 DQPSK
modulator. The transmit serial data (TxDATA) is first con-
verted into Di-bit symbols [Xk, Yk], using a 2-bit serial to paral-
lel converter. The data is then differentially encoded; symbols
are transmitted as changes in phase rather than absolute phases.
Each symbol represents a phase change, as illustrated in Table
II, and this along with the previously transmitted symbol deter-
mines the next symbol to be transmitted. The differential phase
encoder generates I and Q impulses [Ik, Qk] in response to the
Di-bit symbols according to:
Ik = COS[φk–1 + Δφk]
Qk = SIN[φk–1 + Δφk]
Figure 8.π/4 DQPSK Modulator Functional Block Diagram
Figure 9 illustrates the π/4 DQPSK constellation diagram as de-
scribed above, showing the eight possible states for [Ik, Qk].
The Ik and Qk impulses are then filtered by FIR Root-Raised
Cosine Filters (α = 0.5), generating 10-bit I and Q data. The
FIR Root-Raised Cosine Filters have an impulse response of
±4 symbols.
Figure 9. π/4 DQPSK Constellation Diagram
Transmit CalibrationWhen the transmit section is brought out of sleep mode (Power
high), the transmit section initiates a self-calibration routine to
