AD698-AD698AP Fast Delivery |IC PHOENIX CO.,LIMITED

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AD698-AD698AP
Universal LVDT Signal Conditioner
REV.BUniversal
LVDT Signal Conditioner
FEATURES
Single Chip Solution, Contains Internal Oscillator and
Voltage Reference
No Adjustments Required
Interfaces to Half-Bridge, 4-Wire LVDT
DC Output Proportional to Position
20 Hz to 20 kHz Frequency Range
Unipolar or Bipolar Output
Will Also Decode AC Bridge Signals
Outstanding Performance
Linearity: 0.05%
Output Voltage: 611 V
Gain Drift: 20 ppm/8C (typ)
Offset Drift: 5 ppm/8C (typ)
PRODUCT DESCRIPTION
The AD698 is a complete, monolithic Linear Variable Differen-
tial Transformer (LVDT) signal conditioning subsystem. It is
used in conjunction with LVDTs to convert transducer mechan-
ical position to a unipolar or bipolar dc voltage with a high de-
gree of accuracy and repeatability. All circuit functions are
included on the chip. With the addition of a few external passive
components to set frequency and gain, the AD698 converts the
raw LVDT output to a scaled dc signal. The device will operate
with half-bridge LVDTs, LVDTs connected in the series op-
posed configuration (4-wire), and RVDTs.
The AD698 contains a low distortion sine wave oscillator to
drive the LVDT primary. Two synchronous demodulation
channels of the AD698 are used to detect primary and second-
ary amplitude. The part divides the output of the secondary by
the amplitude of the primary and multiplies by a scale factor.
This eliminates scale factor errors due to drift in the amplitude
of the primary drive, improving temperature performance and
stability.
The AD698 uses a unique ratiometric architecture to eliminate
several of the disadvantages associated with traditional ap-
proaches to LVDT interfacing. The benefits of this new cir-
cuit are: no adjustments are necessary; temperature stability is
improved; and transducer interchangeability is improved.
The AD698 is available in two performance grades:
GradeTemperature RangePackage
AD698AP–40°C to +85°C28-Pin PLCC
AD698SQ–55°C to +125°C24-Pin Cerdip
PRODUCT HIGHLIGHTSThe AD698 offers a single chip solution to LVDT signal
conditioning problems. All active circuits are on the mono-
lithic chip with only passive components required to com-
plete the conversion from mechanical position to dc voltage.The AD698 can be used with many different types of posi-
tion sensors. The circuit is optimized for use with any
LVDT, including half-bridge and series opposed, (4 wire)
configurations. The AD698 accommodates a wide range of
input and output voltages and frequencies.The 20 Hz to 20 kHz excitation frequency is determined by a
single external capacitor. The AD698 provides up to 24 volts
rms to differentially drive the LVDT primary, and the
AD698 meets its specifications with input levels as low as
100 millivolts rms.Changes in oscillator amplitude with temperature will not af-
fect overall circuit performance. The AD698 computes the
ratio of the secondary voltage to the primary voltage to deter-
mine position and direction. No adjustments are required.Multiple LVDTs can be driven by a single AD698 either in
series or parallel as long as power dissipation limits are not
exceeded. The excitation output is thermally protected.The AD698 may be used as a loop integrator in the design of
simple electromechanical servo loops.The sum of the transducer secondary voltages do not need to
be constant.
FUNCTIONAL BLOCK DIAGRAM
AD698–SPECIFICATIONS
(@ TA = +258C, VCM = 0 V, and V+, V– = 615 V dc, unless otherwise noted)
AD698
NOTESA and B represent the Mean Average Deviation (MAD) of the detected sine waves VA and VB. The polarity of VOUT is affected by the sign of the A comparator, i.e.,
multiply VOUT × +1 for ACOMP+ > ACOMP–, and VOUT × –1 for ACOMP– > ACOMP+.Nonlinearity of the AD698 only in units of ppm of full scale. Nonlinearity is defined as the maximum measured deviation of the AD698 output voltage from a
straight line. The straight line is determined by connecting the maximum produced full-scale negative voltage with the maximum produced full-scale positive voltage.See Transfer Function.For example, if the excitation to the primary changes by 1 dB, the gain of the system will change by typically 100 ppm.Output ripple is a function of the AD698 bandwidth determined by C1 and C2. A 1000 pF capacitor should be connected in parallel with R2 to reduce the output
ripple. See Figures 7, 8 and 13.R1 is shown in Figures 7, 8 and 13.Excitation voltage drift is not an important specification because of the ratiometric operation of the AD698.From TMIN to TMAX the overall error due to the AD698 alone is determined by combining gain error, gain drift and offset drift. For example, the typical overall
error for the AD698AP from TMIN to TMAX is calculated as follows: Overall Error = Gain Error at +25°C (±0.2% Full Scale) + Gain Drift from –40°C to +25°C
(20 ppm/°C × 65°C) + Offset Drift from –40°C to +25°C (5 ppm/°C × 65°C) = ±0.36% of full scale. Note that 1000 ppm of full scale equals 0.1% of full scale.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tested are used to calculate outgoing quality levels.
All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ORDERING GUIDE
CONNECTION DIAGRAMS
28-Pin PLCC27261234131415161718
TOP VIEW
(Not to Scale)
LEV1
LEV2
FREQ1
SIG REF
SIG OUT
FEEDBACK
OUT FILT
NC = NO CONNECT
AD698
BFILT1
BFILT2
AFILT1
AFILT2
+ACOMP
FREQ2EXC2EXC1–V
NC –BIN +BIN –AIN +AIN
–ACOMP
OFF1OFF2
24-Pin Cerdip
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD698 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . .36 V
Storage Temperature Range
P Package . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Q Package . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Operating Temperature Range
AD698SQ . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C
AD698AP . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . .+300°C
Power Dissipation Derates above +65°C
P Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mW/°C
Q Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mW/°C
THERMAL CHARACTERISTICS
θJCθJA
P Package30°C/W60°C/W
Q Package26°C/W62°C/W
AD698
Typical Characteristics(at +25°C and VS = ±15 V unless otherwise noted)
Figure 1.Gain and Offset PSRR vs. Temperature
Figure 2.Gain and Offset CMRR vs. Temperature
Figure 3.Typical Gain Drift vs. Temperature
Figure 4.Typical Offset Drift vs. Temperature
THEORY OF OPERATION
A block diagram of the AD698 along with an LVDT (linear
variable differential transformer) connected to its input is shown
in Figure 5 below. The LVDT is an electromechanical trans-
ducer—its input is the mechanical displacement of a core, and
its output is an ac voltage proportional to core position. Two
popular types of LVDTs are the half-bridge type and the series
opposed or four-wire LVDT. In both types the moveable core
couples flux between the windings. The series-opposed con-
nected LVDT transducer consists of a primary winding ener-
gized by an external sine wave reference source and two
secondary windings connected in the series opposed configuration.
The output voltage across the series secondary increases as the core
is moved from the center. The direction of movement is detected
by measuring the phase of the output. Half-bridge LVDTs have a
single coil with a center tap and work like an autotransformer. The
excitation voltage is applied across the coil; the voltage at the center
tap is proportional to position. The device behaves similarly to a
resistive voltage divider.
Figure 5.Functional Block Diagram
The AD698 energizes the LVDT coil, senses the LVDT output
voltages and produces a dc output voltage proportional to core
position. The AD698 has a sine wave oscillator and power am-
plifier to drive the LVDT. Two synchronous demodulation
stages are available for decoding the primary and secondary
voltages. A decoder determines the ratio of the output signal
voltage to the input drive voltage (A/B). A filter stage and out-
put amplifier are used to scale the resulting output.
The oscillator comprises a multivibrator that produces a triwave
output. The triwave drives a sine shaper that produces a low dis-
tortion sine wave. Frequency and amplitude are determined by a
single resistor and capacitor. Output frequency can range from
20 Hz to 20 kHz and amplitude from 2 V to 24 V rms. Total har-
monic distortion is typically –50 dB.
The AD698 decodes LVDTs by synchronously demodulating
the amplitude modulated input (secondaries), A, and a fixed in-
put reference (primary or sum of secondaries or fixed input), B.
A common problem with earlier solutions was that any drift in
the amplitude of the drive oscillator corresponded directly to a
gain error in the output. The AD698, eliminates these errors by
calculating the ratio of the LVDT output to its input excitation in
order to cancel out any drift effects. This device differs from the
AD598 LVDT signal conditioner in that it implements a different
circuit transfer function and does not require the sum of the LVDT
secondaries (A + B) to be constant with stroke length.
The AD698 block diagram is shown below. The inputs consist
of two independent synchronous demodulation channels. The B
channel is designed to monitor the drive excitation to the LVDT.
The full wave rectified output is filtered by C2 and sent to the
computational circuit. Channel A is identical except that the
comparator is pinned out separately. Since the A channel may
reach 0 V output at LVDT null, the A channel demodulator is
usually triggered by the primary voltage (B Channel). In addi-
tion, a phase compensation network may be required to add a
phase lead or lag to the A Channel to compensate for the LVDT
primary to secondary phase shift. For half-bridge circuits the
phase shift is noncritical, and the A channel voltage is large
enough to trigger the demodulator.
Figure 6.AD698 Block Diagram
Once both channels are demodulated and filtered a division cir-
cuit, implemented with a duty cycle multiplier, is used to calcu-
late the ratio A/B. The output of the divider is a duty cycle.
When A/B is equal to 1, the duty cycle will be equal to 100%.
(This signal can be used as is if a pulse width modulated output
is required.) The duty cycle drives a circuit that modulates and
filters a reference current proportional to the duty cycle. The
output amplifier scales the 500 μA reference current converting
it to a voltage. The output transfer function is thus: VOUT=IREF×A/B×R2,whereIREF=500μA
AD698
CONNECTING THE AD698
The AD698 can easily be connected for dual or single supply
operation as shown in Figures 7, 8 and 13. The following gen-
eral design procedures demonstrate how external component
values are selected and can be used for any LVDT that meets
AD698 input/output criteria. The connections for the A and B
channels and the A channel comparators will depend on which
transducer is used. In general follow the guidelines below.
Parameters set with external passive components include: exci-
tation frequency and amplitude, AD698 input signal frequency,
and the scale factor (V/inch). Additionally, there are optional
features; offset null adjustment, filtering, and signal integration,
which can be implemented by adding external components.
SIGNAL–15V
+15V
Figure 7.Interconnection Diagram for Half-Bridge LVDT
and Dual Supply Operation
DESIGN PROCEDURE
DUAL SUPPLY OPERATION
Figure 7 shows the connection method for half-bridge LVDTs.
Figure 8 demonstrates the connections for 3- and 4-wire
LVDTs connected in the series opposed configuration. Both ex-
amples use dual ±15 volt power supplies.Determine the Oscillator Frequency
Frequency is often determined by the required BW of the sys-
tem. However, in some systems the frequency is set to match
the LVDT zero phase frequency as recommended by the
manufacturer; in this case skip to Step 4.Determine the mechanical bandwidth required for LVDT
position measurement subsystem, fSUBSYSTEM. For this ex-
ample, assume fSUBSYSTEM = 250 Hz.Select minimum LVDT excitation frequency approximately
10 × fSUBSYSTEM. Therefore, let excitation frequency = 2.5 kHz.
3. Select a suitable LVDT that will operate with an excitation
frequency of 2.5 kHz. The Schaevitz E100, for instance, will
operate over a range of 50 Hz to 10 kHz and is an eligible
candidate for this example.Select excitation frequency determining component C1. C1=35μFHz/fEXCITATION–VS
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
+AIN
1000pF
100nF6.8µF–15V
+15V6.8µFD
PHASE
LAG/LEAD
NETWORK
PHASE LEADCRSRSRTB
PHASE LAGPHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = RS// (RS + RT)
Figure 8.AD698 Interconnection Diagram for Series
Opposed LVDT and Dual Supply Operation
B. Determine the Oscillator Amplitude
Amplitude is set such that the primary signal is in the 1.0 V to
3.5 V rms range and the secondary signal is in the 0.25 V to
3.5 V rms range when the LVDT is at its mechanical full-scale
position. This optimizes linearity and minimizes noise suscepti-
bility. Since the part is ratiometric, the exact value of the excita-
tion is relatively unimportant.Determine optimum LVDT excitation voltage, VEXC. For a
4-wire LVDT determine the voltage transformation ratio,
VTR, of the LVDT at its mechanical full scale. VTR =
LVDT sensitivity × Maximum Stroke Length from null.
LVDT sensitivity is listed in the LVDT manufacturer’s cata-
log and has units of volts output per volts input per inch dis-
placement. The E100 has a sensitivity of 2.4 mV/V/mil. In
the event that LVDT sensitivity is not given by the manufac-
turer, it can be computed. See section on determining LVDT

Partno	Mfg	Dc	Qty	Available	Descript
AD698	AD	N/a	9	avai	Universal LVDT Signal Conditioner
AD698AP	ADI	N/a	402	avai	Universal LVDT Signal Conditioner