AD684AQ-AD684JQ-AD684SQ Fast Delivery |IC PHOENIX CO.,LIMITED

AD684JQ ,Four-Channel Sample-and-Hold Amplifierspecifications.The AD684 is specified for three temperature ranges. The Jgrade device is specified ..
AD684SQ ,Four-Channel Sample-and-Hold AmplifierCHARACTERISTICS2Output Drive Current –5 +5 –5 +5 –5 +5 mAOutput Resistance, dc 0.3 0.5 0.3 0.5 0.3 ..
AD688AQ ,High Precision +-10 V Referencespecifications.periodic recalibration can therefore be eliminated. Furthermore,the mechanical insta ..
AD688BQ ,High Precision +-10 V ReferenceSPECIFICATIONSSAD688AQ/SQ AD688BQMin Typ Max Min Typ Max UnitsOUTPUT VOLTAGE ERROR+10 V, –10 V Outp ..
AD693AD ,Loop-Powered 4.20 mA Sensor TransmitterFEATURESInstrumentation Amplifier Front EndLoop-Powered OperationPrecalibrated 30 mV or 60 mV Input ..
AD693AQ ,Loop-Powered 4.20 mA Sensor TransmitterSPECIFICATIONS R = 250 V, V = 3.1 V, with external pass transistor unless otherwise noted.)L CMMode ..
ADC10080CIMT ,10-Bit, 80 MSPS, 3V, 78.6 mW A/D ConverterApplicationsn Ultrasound and Imagingn Instrumentationn Cellular Based Stations/Communications Recei ..
ADC10154CIWM ,10-Bit Plus Sign 4 microseconds ADCs with 4- or 8-Channel MUX, Track/Hold and ReferenceADC10154/ADC10158 10-Bit Plus Sign 4 μs ADCs with 4- or 8-Channel MUX, Track/Hold andReferenceNovem ..
ADC10158CIN ,10-Bit Plus Sign 4 s ADCs with 4- or 8-Channel MUX/ Track/Hold and ReferencePin Descriptions+AV This is the positive analog supply. This pin RD This is the read control input. ..
ADC10158CIWM ,10-Bit Plus Sign 4 microseconds ADCs with 4- or 8-Channel MUX, Track/Hold and ReferencePin Descriptions+AV This is the positive analog supply. This pin RD This is the read control input. ..
ADC101S051CIMF , Single Channel, 200 to 500 ksps, 10-Bit A/D Converter
ADC101S101CIMF ,1MSPS, 10-Bit A/D Converter in SOT-23ADC121S101/ADC101S101/ADC081S101 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 & LLPJanuary 2005ADC ..

AD684AQ-AD684JQ-AD684SQ
Four-Channel Sample-and-Hold Amplifier
FUNCTIONAL BLOCK DIAGRAM
REV.AFour-Channel
Sample-and-Hold Amplifier
FEATURES
Four Matched Sample-and-Hold Amplifiers
Independent Inputs, Outputs and Control Pins
500ns Hold Mode Settlingms Maximum Acquisition Time to 0.01%
Low Droop Rate: 0.01mV/ms
Internal Hold Capacitors
75 ps Maximum Aperture Jitter
Low Power Dissipation: 430 mW
0.3" Skinny DIP Package
MIL-STD-883 Compliant Versions Available
PRODUCT HIGHLIGHTSFast acquisition time (1μs) and low aperture jitter (75 ps)
make the AD684 the best choice for multiple channel data
acquisition systems.Monolithic construction insures excellent interchannel
matching in terms of timing and accuracy, as well as high
reliability.Independent inputs, outputs and sample-and-hold controls
allow user flexibility in system architecture.Low droop (0.01μV/μs) and internally compensated hold
mode error results in superior system accuracy.The AD684’s fast settling time and low output impedance
make it ideal for driving high speed analog to digital
converters such as the AD578, AD674, AD7572 and the
AD7672.The AD684 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD684/883B data sheet for detailed
specifications.
PRODUCT DESCRIPTION
The AD684 is a monolithic quad sample-and-hold amplifier
(SHA). It features four complete sampling channels, each
controlled by an independent hold command. Each SHA is
complete with an internal hold capacitor. The high accuracy
SHA channels are self-contained and require no external
components or adjustments. The AD684 is manufactured on a
BiMOS process which provides a merger of high performance
bipolar circuitry and low power CMOS logic.
The AD684 is ideal for high performance, multichannel data
acquisition systems. Each SHA channel can acquire a signal in
less than 1 μs and retain the held value with a droop rate of less
than 0.01μV/μs. Excellent linearity and ac performance make
the AD684 an ideal front end for high speed 12- and 14-bit
ADCs.
The AD684 has a self-correcting architecture that minimizes
hold mode errors and insures accuracy over temperature. Each
channel of the AD684 is capable of sourcing 5 mA and
incorporates output short circuit protection.
The AD684 is specified for three temperature ranges. The J
grade device is specified for operation from 0 to +70°C, the A
grade from –40°C to +85°C and the S grade from –55°C to
+125°C.
*. Patent Number 4,962,325.
AD684–SPECIFICATIONS(TMIN to TMAX with VCC = +12 V 6 10%, VEE = –12 V 6 10%, unless otherwise noted)
NOTES
1Specified and tested over an input range of ±5 V.Maximum current the AD684 can source (or sink). Testing guarantees that the accuracy of the held signal remains within 2.5 mV of its initial value.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.
PIN CONFIGURATION
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD684 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
NOTESFor details on grade and package offerings screened in accordance
with MIL-STD-883, refer to the Analog Devices Military Prod-
ucts Databook or current AD684/883B data sheet.Q = Cerdip.
AD684–Typical Characteristics
Droop Rate vs. Temperature, VIN= 0 V
Effective Aperture Delay vs. FrequencyBias Current vs. Input VoltageSupply Current vs. Temperature
Supply Current vs. Supply Voltage
Interchannel Isolation vs. FrequencyPower Supply Rejection Ratio
vs. Frequency
Acquisition Time (to 0.01 %) vs. Input Step Size
DEFINITIONS OF SPECIFICATIONS
Acquisition Time — The length of time that the SHA must
remain in the sample mode in order to acquire a full-scale input
step to a given level of accuracy.
Small Signal Bandwidth — The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 100 mV p-p sine wave.
Full Power Bandwidth — The frequency at which the held
output amplitude is 3 dB below the input amplitude, under an
input condition of a 10 V p-p sine wave.
Effective Aperture Delay — The difference between the
switch delay and the analog delay of the SHA channel. A
negative number indicates that the analog portion of the overall
delay is greater than the switch portion. This effective delay
represents the point in time, relative to the hold command, that
the input signal will be sampled.
Aperture Jitter — The variations in aperture delay for
successive samples. Aperture jitter puts an upper limit on the
maximum frequency that can be accurately sampled.
Hold Settling Time —The time required for the output to
settle to within a specified level of accuracy of its final held
value after the hold command has been given.
Droop Rate — The drift in output voltage while in the hold
mode.
Feedthrough — The attenuated version of a changing input
signal that appears at the output when the SHA is in the hold
mode.
Hold Mode Offset — The difference between the input signal
and the held output. This offset term applies only in the hold
mode and includes the error caused by charge injection and all
other internal offsets. It is specified for an input of 0 V.
Tracking Mode Offset — The difference between the input
and output signals when the SHA is in the track mode.
Nonlinearity — The deviation from a straight line on a plot of
input vs. (held) output as referenced to a straight line drawn
between endpoints, over an input range of –5 V and +5 V.
Gain Error — Deviation from a gain of +1 on the transfer
function of input vs. held output.
Interchannel Isolation — The level of crosstalk between
adjacent channels while in the sample (track) mode with a full
scale 100 kHz input signal.
Interchannel Aperture Offset — The variation in aperture
time between the four channels for a simultaneous hold
command.
Differential Offset — The difference in hold mode offset
between the four SHA channels.
Power Supply Rejection Ratio — A measure of change in the
held output voltage for a specified change in the positive or
negative supply.
Sampled dc Uncertainty — The internal rms SHA noise that
is sampled onto the hold capacitor.
Hold Mode Noise — The rms noise at the output of the SHA
while in the hold mode, specified over a given bandwidth.
Total Output Noise — The total rms noise that is seen at the
output of the SHA while in the hold mode. It is the rms
summation of the sampled dc uncertainty and the hold mode
noise.
Output Drive Current — The maximum current the SHA can
source (or sink) while maintaining a change in hold mode offset
of less than 2.5 mV.
FUNCTIONAL DESCRIPTION
The AD684 is a complete quad sample-and-hold amplifier that
provides high speed sampling to 12-bit accuracy in less than 1 μs.
The AD684 is completely self-contained, including on-chip
hold capacitors, and requires no external components or
adjustments to perform the sampling function. Each SHA
channel can operate independently, having its own input, output
and sample/hold command. Both inputs and outputs are treated
as single ended signals, referred to common.
The AD684 utilizes a proprietary circuit design which includes a
self-correcting architecture. This sample-and-hold circuit
corrects for internal errors after the hold command has been
given, by compensating for amplifier gain and offset errors, and
charge injection errors. Due to the nature of the design, the
SHA output in the sample mode is not intended to provide an
accurate representation of the input. However, in hold mode,
the internal circuitry is reconfigured to produce an accurately
held version of the input signal. To the right is a block diagram
AD684
OP484
DYNAMIC PERFORMANCE
The AD684 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. The fast acquisition time, fast
hold settling time and good output drive capability allow the
AD684 to be used with high speed, high resolution A-to-D
converters like the AD674 and AD7672. The AD684’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. Typically, the sample and hold can
acquire a 10 V step in less than 750 ns. Figure 1 shows the
settling accuracy as a function of acquisition time.
Figure 1.VOUT Settling vs. Acquisition Time
The hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. The typical settling behavior of the AD684 is shown
in Figure 2. The settling time of the AD684 is sufficiently fast to
allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added “start convert” delay.
Figure 2.Typical AD684 Hold Mode
HOLD MODE OFFSET
The dc accuracy of the AD684 is determined primarily by the
hold mode offset. The hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. The hold mode offset arises from
a voltage error introduced onto the hold capacitor by charge injec-
tion of the internal switches. The nominal hold mode offset is
specified for a 0 V input condition. Over the input range of
Figure 3.Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). Only a single
adjustment of the offset is necessary for the four SHA channels as a
result of the excellent matching among them. The offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DECOUPLING AND GROUNDING
CONSIDERATIONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from
excessive high frequency noise (ripple). The supply connection
to the AD684 should also be capable of delivering transient
currents to the device. To achieve the specified accuracy and
dynamic performance, decoupling capacitors must be placed
directly at both the positive and negative supply pins to common.
Ceramic type 0.1 μF capacitors should be connected from VCC
and VEE to common.

Partno	Mfg	Dc	Qty	Available	Descript
AD684AQ	ADI	N/a	10	avai	Four-Channel Sample-and-Hold Amplifier
AD684JQ	ADI	N/a	44	avai	Four-Channel Sample-and-Hold Amplifier
AD684SQ	AD	N/a	1	avai	Four-Channel Sample-and-Hold Amplifier