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AD678JD ,12-Bit 200 kSPS Complete Sampling ADCapplications. In addition, the AD678K, B and T fully specified and tested ac and dc parameters. The ..
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ADC088S102CIMT , 8-Channel, 500 kSPS to 1 MSPS, 8-Bit A/D Converter
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AD678
12-Bit 200 kSPS Complete Sampling ADC
FUNCTIONAL BLOCK DIAGRAM12-Bit 200 kSPS
Complete Sampling ADC
FEATURES
AC and DC Characterized and Specified
(K, B and T Grades)
200k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
72 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M� Input Impedance
8-Bit or 16-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTIONThe AD678 is a complete, multipurpose 12-bit monolithic
analog-to-digital converter, consisting of a sample-hold ampli-
fier (SHA), a microprocessor compatible bus interface, a voltage
reference and clock generation circuitry.
The AD678 is specified for ac (or “dynamic”) parameters such
as S/N+D ratio, THD and IMD which are important in signal
processing applications. In addition, the AD678K, B and T
grades are fully specified for dc parameters which are important
in measurement applications.
The AD678 offers a choice of digital interface formats; the 12
data bits can be accessed by a 16-bit bus in a single read opera-
tion or by an 8-bit bus in two read operations (8+4), with right
or left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth ofMHz and a full linear bandwidth of 500 kHz. High input im-
pedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm which includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD678 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The AD678 is available in 28-lead plastic DIP,
ceramic DIP, and 44-lead J-leaded ceramic surface mount packages.
Screening to MIL-STD-883C Class B is also available.
*. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445;
4,808,908; RE30,586.
PRODUCT HIGHLIGHTS1. COMPLETE INTEGRATION:The AD678 minimizes ex-
ternal component requirements by combining a high speed
sample-hold amplifier (SHA), ADC, 5 V reference, clock and
digital interface on a single chip. This provides a fully speci-
fied sampling A/D function unattainable with discrete designs.
2. SPECIFICATIONS:The AD678K, B and T grades provide
fully specified and tested ac and dc parameters. The AD678J,
A and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD and IMD) are of value in signal process-
ing applications.
3. EASE OF USE:The pinout is designed for easy board lay-
out, and the choice of single or two read cycle output pro-
vides compatibility with 16- or 8-bit buses. Factory trimming
eliminates the need for calibration modes or external trim-
ming to achieve rated performance.
4. RELIABILITY:The AD678 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH:The AD678 provides the same pinout as
the 14-bit, 128 kSPS AD679 ADC.
6. The AD678 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD678/883B data sheet for detailed
specifications.
REV.C
AD678–SPECIFICATIONS
AC SPECIFICATIONSNOTESfIN amplitude = –0.5 dB (9.44 V p-p) bipolar mode full scale unless otherwise indicated. All measurements referred to a –0 dB (9.997 V p-p) input signal unless
otherwise indicated.See Figures 13 and 14 for higher frequencies and other input amplitudes.See Figure 12.fA = 9.08 kHz, fB = 9.58 kHz, with fSAMPLE = 200 kSPS. See Definition of Specifications section and Figure 16.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONSIIH
LOGIC OUTPUTS
VOH
Specifications subject to change without notice.
(TMIN to TMAX, VCC = +12 V � 5%, VEE = –12 V � 5%, VDD = +5 V � 10%, fSAMPLE = 200 kSPS,
flN = 10.06 kHz unless otherwise noted)1
(All device types TMIN to TMAX, VCC = +12 V � 5%, VEE = –12 V � 5%, VDD = +5 V � 10%)
DC SPECIFICATIONSNOTESAdjustable to zero.Includes internal voltage reference error.
AD678
(TMIN to TMAX, VCC = +12 V � 5%, VEE = –12 V � 5%, VDD = +5 V � 10% unless otherwise noted)
AD678
TIMING SPECIFICATIONSConversion Time
Conversion Rate
Convert Pulsewidth
Aperture Delay
Status Delay
Access Time
Float Delay
Output Delay
Format Setup
OE Delay
Read Pulsewidth
Conversion Delay
NOTESIncludes acquisition time.Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the data lines/EOC cross 2.0 V or 0.8 V. See Figure 3.COUT = 100 pF.COUT = 50 pF.Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the output voltage changes by 0.5 V. See Figure 3; COUT = 10 pF.
Specifications subject to change without notice.
(All grades, TMIN to TMAX, VCC = +12 V � 5%, VEE = –12V � 5%, VDD = +5 V � 10% unless
otherwise noted)Figure 1.Conversion Timing
Figure 2.EOC Timing
Figure 3.Load Circuit for Bus Timing Specifications
ORDERING GUIDENOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to Analog Devices Military Products Databook or /883 data sheet.N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
ABSOLUTE MAXIMUM RATINGS*VDD
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITYThe AD678 features input protection circuitry consisting of large “distributed” diodes and polysilicon
series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy
pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD678 has been
classified as a Category 1 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test equipment
and discharge without detection. Unused devices must be stored in conductive foam or shunts, and
the foam should be discharged to the destination socket before devices are removed. For further
information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
Functional Block Diagram
AD678
PIN DESCRIPTIONR/L (DB1)
SYNC
VCC
Type: AI = Analog Input; AO = Analog Output; DI = Digital Input (TTL and 5 V CMOS compatible); DO = Digital Output (TTL and 5 V CMOS compatible).
All DO pins are three-state drivers; P = Power.
PIN CONFIGURATIONS
DIP PACKAGE JLCC PACKAGE
VEE
AIN
AGND
REFOUT
REFIN
BIPOFF
VCC
DB9
DB8
DB7
DB10
DB6
DB5
DB4
DB3SCNCOENCEOCENV
EOCDB11NCNC
NYQUIST FREQUENCYAn implication of the Nyquist sampling theorem, the “Nyquist
Frequency” of a converter is that input frequency which is one-
half the sampling frequency of the converter.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIOS/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of a full-scale input signal and is ex-
pressed as a percentage or in decibels. For input signals or
harmonics that are above the Nyquist frequency, the aliased
component is used.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENTThe peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
INTERMODULATION DISTORTION (IMD)With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m + n), at sum and difference frequencies of mfa ±
nfb, where m, n = 0, 1, 2, 3.... Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb) and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of
the measured input sides to the rms sum of the distortion terms.
The two signals applied to the converter are of equal ampli-
tude and the peak value of their sum is –0.5 dB from full scale
(9.44 V p-p). The IMD products are normalized to a 0 dB
input signal.
BANDWIDTHThe full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
The full-linear bandwidth is the input frequency at which the
slew rate limit of the sample-hold-amplifier (SHA) is reached.
At this point, the amplitude of the reconstructed fundamental
has degraded by less than 0.1 dB. Beyond this frequency, distor-
tion of the sampled input signal increases significantly.
The AD678 has been designed to optimize input bandwidth, al-
lowing the AD678 to undersample input signals with frequen-
cies significantly above the converter’s Nyquist frequency.
APERTURE DELAYAperture delay is a measure of the SHA’s performance and is
measured from the falling edge of Start Convert (SC) to when
the input signal is held for conversion. In synchronous mode,
Chip Select (CS) should be LOW before SC to minimize aper-
ture delay.
APERTURE JITTERAperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INPUT SETTLING TIMESettling time is a function of the SHA’s ability to track fast slew-
ing signals. This is specified as the maximum time required in
track mode after a full-scale step input to guarantee rated con-
version accuracy.
DIFFERENTIAL NONLINEARITY (DNL)In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes (NMC) are guaranteed.
UNIPOLAR ZERO ERRORIn unipolar mode, the first transition should occur at a level 1/2
LSB above analog ground. Unipolar zero error is the deviation
of the actual transition from that point. This error can be ad-
justed as discussed in the Input Connections and Calibration
section.
BIPOLAR ZERO ERRORIn the bipolar mode, the major carry transition (1111 1111
1111 to 0000 0000 0000) should occur at an analog value 1/2
LSB below analog ground. Bipolar zero error is the deviation of
the actual transition from that point. This error can be adjusted
as discussed in the Input Connections and Calibration section.
GAIN ERRORThe last transition should occur at an analog value 1 1/2 LSB
below the nominal full scale (9.9963 volts for a 0–10 V range,
4.9963 volts for a ±5 V range). The gain error is the deviation of
the actual difference between the first and last code transition
from the ideal difference between the first and last code transi-
tion. This error can be adjusted as shown in the Input Connec-
tions and Calibration section.
INTEGRAL NONLINEARITY (INL)The ideal transfer function for a linear ADC is a straight line
drawn between “zero” and “full scale.” The point used as
“zero” occurs 1/2 LSB before the first code transition. “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition. Integral nonlinearity is the worst-case deviation of a code
from the straight line. The deviation of each code is measured
from the middle of that code.
POWER SUPPLY REJECTIONVariations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power Supply Rejection is the
maximum change in the full-scale transition point due to a
change in power-supply voltage from the nominal value.
TEMPERATURE DRIFTThis is the maximum change in the parameter from the initial
value (@ +25°C) to the value at TMIN or TMAX.
