AD677KD ,16-Bit 100 kSPS Sampling ADCapplications.The AD677 operates from +5 V and ±12 V supplies and typi-cally consumes 450 mW using a ..
AD677KN ,16-Bit 100 kSPS Sampling ADCSPECIFICATIONS MIN MAX, CC EE DD AD677J/A AD677K/BParameter Min Typ Max Min Ty ..
AD677KR ,16-Bit 100 kSPS Sampling ADCSPECIFICATIONS1(T to T V = +12 V 6 5%, V = –12 V 6 5%, V = +5 V 6 10%)AC
AD678 ,12-Bit 200 kSPS Complete Sampling ADCSPECIFICATIONS (T to T , V = +12 V 5%, V = –12 V 5%, V = +5 V 10% unless otherwise noted)MIN ..
AD678AJ ,12-Bit 200 kSPS Complete Sampling ADCSPECIFICATIONS (All device types T to T , V = +12 V 5%, V = –12 V 5%, V = +5 V 10%)MIN MAX CC ..
AD678BD ,12-Bit 200 kSPS Complete Sampling ADCSPECIFICATIONS f = 10.06 kHz unless otherwise noted)lNAD678J/A/S AD678K/B/T Parameter Min Typ Max M ..
ADC08831IMX ,8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold FunctionFeaturesrial I/O will interface to COPS family of micro-controllers,PLD’s, microprocessors, DSP’s, ..
ADC08831IN ,8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold FunctionADC08831/ADC08832 8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/HoldFunctionSept ..
ADC08831IWM ,8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold FunctionGeneral Descriptionn InstrumentationThe ADC08831/ADC08832 are 8-bit successive approxima-n Embedded ..
ADC08832IM ,8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold FunctionGeneral Descriptionn InstrumentationThe ADC08831/ADC08832 are 8-bit successive approxima-n Embedded ..
ADC08832IMM ,8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold FunctionApplicationsn Total unadjusted error: ±1LSBn Digitizing sensors and waveformsn No missing codes ove ..
ADC08832IMM ,8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold FunctionFeaturesrial I/O will interface to COPS family of micro-controllers,PLD’s, microprocessors, DSP’s, ..
AD677AD-AD677BD-AD677JD-AD677JN-AD677JR-AD677KD-AD677KN-AD677KR
16-Bit 100 kSPS Sampling ADC
FUNCTIONAL BLOCK DIAGRAM
AGND
VREFIN
CLK
SAMPLE
AGND SENSE
CAL
BUSYSCLK
SDATAREV.A
16-Bit 100 kSPS
Sampling ADC
FEATURES
Autocalibrating
On-Chip Sample-Hold Function
Serial Output
16 Bits No Missing Codes61 LSB INL
–99 dB THD
92 dB S/(N+D)
1 MHz Full Power Bandwidth
PRODUCT HIGHLIGHTS1. Autocalibration provides excellent dc performance while
eliminating the need for user adjustments or additional exter-
nal circuitry.
2. ±5 V to ±10 V input range (±VREF).
3. Available in 16-pin 0.3" skinny DIP or 28-lead SOIC.
4. Easy serial interface to standard ADI DSPs.
5. TTL compatible inputs/outputs.
6. Excellent ac performance: –99 dB THD, 92 dB S/(N+D)
peak spurious –101 dB.
7. Industry leading dc performance: 1.0 LSB INL, ±1 LSB full
scale and offset.
PRODUCT DESCRIPTIONThe AD677 is a multipurpose 16-bit serial output analog-to-
digital converter which utilizes a switched-capacitor/charge
redistribution architecture to achieve a 100 kSPS conversion
rate (10 μs total conversion time). Overall performance is opti-
mized by digitally correcting internal nonlinearities through
on-chip autocalibration.
The AD677 circuitry is segmented onto two monolithic chips—
a digital control chip fabricated on Analog Devices DSP CMOS
process and an analog ADC chip fabricated on our BiMOS II
process. Both chips are contained in a single package.
The AD677 is specified for ac (or “dynamic”) parameters such
as S/(N+D) Ratio, THD and IMD which are important in sig-
nal processing applications. In addition, dc parameters are
specified which are important in measurement applications.
The AD677 operates from +5 V and ±12 V supplies and typi-
cally consumes 450 mW using a 10 V reference (360 mW with
5 V reference) during conversion. The digital supply (VDD) is
separated from the analog supplies (VCC, VEE) for reduced digi-
tal crosstalk. An analog ground sense is provided to remotely
sense the ground potential of the signal source. This can be use-
ful if the signal has to be carried some distance to the A/D con-
verter. Separate analog and digital grounds are also provided.
The AD677 is available in a 16-pin narrow plastic DIP, 16-pin
narrow side-brazed ceramic package, or 28-lead SOIC. A paral-
lel output version, the AD676, is available in a 28-pin ceramic
or plastic DIP. All models operate over a commercial tempera-
ture range of 0°C to +70°C or an industrial range of –40°C to
+85°C.
AD677–SPECIFICATIONS
AC SPECIFICATIONSSignal-to-Noise and Distortion Ratio (S/(N+D))
Peak Spurious or Peak Harmonic Component
Intermodulation Distortion (IMD)
Full Power Bandwidth
DIGITAL SPECIFICATIONSVIL
IIH
LOGIC OUTPUTS
VOH
NOTESVREF = 10.0 V, Conversion Rate = 100 kSPS, flN = 1.0 kHz, VIN = –0.05 dB, Bandwidth = 50 kHz unless otherwise indicated. All measurements referred to a 0 dB
(20 V p-p) input signal. Values are post-calibration.For other input amplitudes, refer to Figure 12.For dynamic performance with different reference values see Figure 11.fa = 1008 Hz, fb = 1055 Hz. See Definition of Specifications section and Figure 16.
Specifications subject to change without notice.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
(for all grades TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)
AD677DC SPECIFICATIONSTEMPERATURE RANGE
ACCURACY
TEMPERATURE DRIFT
ANALOG INPUT
POWER SUPPLIES
NOTESVREF = 10.0 V, Conversion Rate = 100 kSPS unless otherwise noted. Values are post-calibration.Values shown apply to any temperature from TMIN to TMAX after calibration at that temperature at nominal supplies.Values shown are based upon calibration at +25°C with no additional calibration at temperature. Values shown are the typical variation from the value at +25°C.See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 11 for dynamic performance with other reference voltage values.See “APPLICATIONS” section for recommended input buffer circuit.Typical deviation of bipolar zero, –full scale or +full scale from min to max rating.
*For explanation of input characteristics, see “ANALOG INPUT” section.
Specifications subject to change without notice.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)1
AD677
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1TIMING SPECIFICATIONSNOTESSee the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the
internal sample/hold function. Operation at slower rates may degrade performance.tC = tFCD + 16 × tCLK + tLCS.580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle).If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse.tCH + tCL = tCLK and must be greater than 480 ns.
CAL
(INPUT)
BUSY
(OUTPUT)
CLK*
(INPUT)
tCTtCALH
tCALB
tCBtFCD
tCL
tCH
tCLK
*SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH. Figure 1. Calibration Timing
BUSY
(OUTPUT)
tFCD
tCH
SAMPLE*
(INPUT)
CLK*
(INPUT)1617
tLCSBIT2BIT13
SCLK
(OUTPUT)
SDATA
(OUTPUT)OLD BIT 16
tCD
tDSH
tSB
tSL
tCSH
tCL
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD677 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE*D = Ceramic DIP; N = Plastic DIP; R = Small Outline IC (SOIC).
ABSOLUTE MAXIMUM RATINGS*VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Vcc to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . .–18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V
Digiul Inputs to DGND . . . . . . . . . . . . . . . . . . . . . .0 to +5.5 V
Analog Inputs, VREF to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . .(VCC +0.3 V) to (VEE –0.3 V)
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD677
PIN DESCRIPTION 58
6, 7
Type:AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
SAMPLE
CLK
DGND
NC
AGND
VCC
CAL
BUSY
AGND
SENSEIN
VEE
VDD
VREF
NC = NO CONNECT
SCLKSDATADIP Pinout
INTERMODULATION DISTORTION (IMD)With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3 . . . . Intermodulation terms are those
for which m or n is not equal to zero. For example, the second
order terms are (fa + fb) and (fa – fb), and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals applied to the converter are of equal amplitude,
and the peak value of their sum is –0.5 dB from full scale. The
IMD products are normalized to a 0 dB input signal.
APERTURE DELAYAperture delay is the time required after SAMPLE pin is taken
LOW for the internal sample-hold of the AD677 to open, thus
holding the value of VIN.
APERTURE JITTERAperture jitter is the variation in the aperture delay from sample
to sample.
POWER SUPPLY REJECTIONDC variations in the power supply voltage will affect the overall
transfer function of the ADC, resulting in zero error and full-
scale error changes. Power supply rejection is the maximum
change in either the bipolar zero error or full-scale error value.
Additionally, there is another power supply variation to con-
sider. AC ripple on the power supplies can couple noise into the
ADC, resulting in degradation of dynamic performance. This is
displayed in Figure 15.
INPUT SETTLING TIMESettling time is a function of the SHA’s ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
NOISE/DC CODE UNCERTAINTYIdeally, a fixed dc input should result in the same output code
for repetitive conversions. However, as a consequence of un-
avoidable circuit noise within the wideband circuits in the ADC,
there is a range of output codes which may occur for a given in-
put voltage. If you apply a dc signal to the ADC and record a
large number of conversions, the result will be a distribution of
codes. If you fit a Gaussian probability distribution to the histo-
gram, the standard deviation is approximately equivalent to the
rms input noise of the ADC.
NYQUIST FREQUENCYAn implication of the Nyquist sampling theorem, the “Nyquist
frequency’’ of a converter is that input frequency which is one
half the sampling frequency of the converter.
TOTAL HARMONIC DISTORTIONTotal harmonic distortion (THD) is the ratio of the rms sum of
the harmonic components to the rms value of a full-scale input
signal and is expressed in percent (%) or decibels (dB). For in-
put signals or harmonics that are above the Nyquist frequency,
the aliased components are used.
SIGNAL-TO-NOISE PLUS DISTORTION RATIOSignal-to-noise plus distortion is defined to be the ratio of the
rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc.
+/– FULL-SCALE ERRORThe last + transition (from 011 . . . 10 to 011 . . . 11) should
occur for an analog voltage 1.5 LSB below the nominal full
scale (4.99977 volts for a ±5 V range). The full-scale error is
the deviation of the actual level of the last transition from the
ideal level.
BIPOLAR ZERO ERRORBipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the mid-
scale output code.
DIFFERENTIAL NONLINEARITY (DNL)In an ideal ADC, code transitions are one LSB apart. Differen-
tial nonlinearity is the maximum deviation from this ideal value.
It is often specified in terms of resolution for which no missing
codes are guaranteed.
INTEGRAL NONLINEARITY (INL)The ideal transfer function for an ADC is a straight line bisect-
ing the center of each code drawn between “zero” and “full
scale.” The point used as “zero” occurs 1/2 LSB before the
most negative code transition. “Full scale” is defined as a level
1.5 LSB beyond the most positive code transition. Integral non-
linearity is the worst-case deviation of a code center average
from the straight line.
BANDWIDTHThe full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
AD677
FUNCTIONAL DESCRIPTIONThe AD677 is a multipurpose 16-bit analog-to-digital converter
and includes circuitry which performs an input sample/hold
function, ground sense, and autocalibration. These functions
are segmented onto two monolithic chips—an analog signal pro-
cessor and a digital controller. Both chips are contained within
the AD677 package.
The AD677 employs a successive-approximation technique to
determine the value of the analog input voltage. However, in-
stead of the traditional laser-trimmed resistor-ladder approach,
this device uses a capacitor-array, charge redistribution tech-
nique. Binary-weighted capacitors subdivide the input sample to
perform the actual analog-to-digital conversion. The capacitor
array eliminates variation in the linearity of the device due to
temperature-induced mismatches of resistor values. Since a
capacitor array is used to perform the data conversions, the
sample/hold function is included without the need for additional
external circuitry.
Initial errors in capacitor matching are eliminated by an
autocalibration circuit within the AD677. This circuit employs
an on-chip microcontroller and a calibration DAC to measure
and compensate capacitor mismatch errors. As each error is
determined, its value is stored in on-chip memory (RAM).
Subsequent conversions use these RAM values to improve con-
version accuracy. The autocalibration routine may be invoked
at any time. Autocalibration insures high performance while
eliminating the need for any user adjustments and is described
in detail below.
The microcontroller controls all of the various functions within
the AD677. These include the actual successive approximation
algorithm, the autocalibration routine, the sample/hold opera-
tion, and the internal output data latch.
AUTO CALIBRATIONThe AD677 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense cir-
cuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then transferred to a capacitor of equal size (composed
of the sum of the remaining lower weight bits). The voltage that
results represents the amount of capacitor mismatch. A calibra-
tion digital-to-analog converter (DAC) adds an appropriate
value of error correction voltage to cancel this mismatch. This
correction factor is also stored in RAM. This process is repeated
for each of the eight remaining capacitors representing the top
nine bits. The accumulated values in RAM are then used during
subsequent conversions to adjust conversion results accordingly.
As shown in Figure 1, when CAL is taken HIGH the AD677
internal circuitry is reset, the BUSY pin is driven HIGH, and
the ADC prepares for calibration. This is an asynchronous hard-
ware reset and will interrupt any conversion or calibration cur-
rently in progress. Actual calibration begins when CAL is taken
In most applications, it is sufficient to calibrate the AD677 only
upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first. If
calibration is not performed, the AD677 may come up in an un-
known state, or performance could degrade to as low as 10 bits.
CONVERSION CONTROLThe AD677 is controlled by two signals: SAMPLE and CLK,
as shown in Figure 2. It is assumed that the part has been cali-
brated and the digital I/O pins have the levels shown at the start
of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which execute the 16-bit internal successive ap-
proximation routine. The analog input is acquired by taking the
SAMPLE line HIGH for a minimum sampling time of tS. The
actual sample taken is the voltage present on VIN one aperture
delay after the SAMPLE line is brought LOW, assuming the
previous conversion has completed (signified by BUSY going
LOW). Care should be taken to ensure that this negative edge is
well defined and jitter free in ac applications to reduce the un-
certainty (noise) in signal acquisition. With SAMPLE going
LOW, the AD677 commits itself to the conversion—the input
at VIN is disconnected from the internal capacitor array, BUSY
goes HIGH, and the SAMPLE input will be ignored until the
conversion is completed (when BUSY goes LOW). SAMPLE
must be held LOW for a minimum period of time tSL. A period
of time tFCD after bringing SAMPLE LOW, the 17 CLK cycles
are applied; CLK pulses that start before this period of time are
ignored. BUSY goes HIGH tSB after SAMPLE goes LOW, sig-
nifying that a conversion is in process, and remains HIGH until
the conversion is completed. As indicated in Figure 2, the twos
complement output data is presented MSB first. This data may
be captured with the rising edge of SCLK or the falling edge of
CLK, beginning with pulse #2. The AD677 will ignore CLK
after BUSY has gone LOW and SDATA or SCLK will not
change until a new sample is acquired.
CONTINUOUS CONVERSIONFor maximum throughput rate, the AD677 can be operated in a
continuous convert mode. This is accomplished by utilizing the
fact that SAMPLE will no longer be ignored after BUSY goes
LOW, so an acquisition may be initiated even during the HIGH
time of the 17th CLK pulse for maximum throughput rate
while enabling full settling of the sample/hold circuitry. If
SAMPLE is already HIGH during the rising edge of the 17th
CLK, then an acquisition is immediately initiated approxi-
mately 100 ns after the rising edge of the 17th clock pulse.
Care must be taken to adhere to the minimum/maximum tim-
ing requirements in order to preserve conversion accuracy.
GENERAL CONVERSION GUIDELINESDuring signal acquisition and conversion, care should be taken
with the logic inputs to avoid digital feedthrough noise. It is
possible to run CLK continuously, even during the sample
period. However, CLK edges during the sampling period, and
especially when SAMPLE goes LOW, may inject noise into the
sampling process. The AD677 is tested with no CLK cycles
