AD676KN ,0.3-26.4V; 16-bit 100 kSPS sampling ADCSPECIFICATIONSMIN MAX CC EE DDAD676J/A AD676K/BParameter Min Typ Max Min Typ Max UnitsTEMPERATURE R ..
AD677 ,16-Bit, Serial, 100 kSPS Sampling ADC.SPECIFICATIONS (T to T , V = +12 V 6 5%, V = –12 V 6 5%, V = +5 V 6 1O%)MIN MAX CC EE DDAD677J/A AD ..
AD677AD ,16-Bit 100 kSPS Sampling ADCSPECIFICATIONS (T to T , V = +12 V 6 5%, V = –12 V 6 5%, V = +5 V 6 1O%)MIN MAX CC EE DDAD677J/A AD ..
AD677BD ,16-Bit 100 kSPS Sampling ADCSPECIFICATIONS (T to T , V = +12 V 6 5%, V = –12 V 6 5%, V = +5 V 6 1O%)MIN MAX CC EE DDAD677J/A AD ..
AD677JD ,16-Bit 100 kSPS Sampling ADCFEATURESAutocalibratingOn-Chip Sample-Hold FunctionA CHIPV 10Serial OutputIN16-BITCOMP9 DACAGND SEN ..
AD677JN ,16-Bit 100 kSPS Sampling ADCFEATURESAutocalibratingOn-Chip Sample-Hold FunctionA CHIPV 10Serial OutputIN16-BITCOMP9 DACAGND SEN ..
ADC084S051CIMM , ADC084S051 4 Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter
ADC084S051CIMM , ADC084S051 4 Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter
ADC084S051CIMMX , ADC084S051 4 Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter
ADC0852CCN ,Multiplexed Comparator with 8-Bit Reference DividerADC0852/ADC0854MultiplexedComparatorwith8-BitReferenceDividerApril1995ADC0852/ADC0854MultiplexedCom ..
ADC0858CIN ,8-Bit Analog Data Acquisition and Monitoring Systemsapplications softwarecrossed which limits.Y2 (ADC0851) or 8 (ADC0858) analog input channelsThe adva ..
ADC0882CCN ,8-Bit 20 MSPS Flash A/D ConverterBlock Diagram
NMINV
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AD676KN
0.3-26.4V; 16-bit 100 kSPS sampling ADC
FUNCTIONAL BLOCK DIAGRAMREV. A
16-Bit 100 kSPS
Sampling ADC
FEATURES
Autocalibrating
On-Chip Sample-Hold Function
Parallel Output Format
16 Bits No Missing Codes61 LSB INL
–97 dB THD
90 dB S/(N+D)
1 MHz Full Power Bandwidth
PRODUCT DESCRIPTIONThe AD676 is a multipurpose 16-bit parallel output analog-to-
digital converter which utilizes a switched-capacitor/charge
redistribution architecture to achieve a 100 kSPS conversion
rate (10 μs total conversion time). Overall performance is opti-
mized by digitally correcting internal nonlinearities through
on-chip autocalibration.
The AD676 circuitry is segmented onto two monolithic chips—
a digital control chip fabricated on Analog Devices DSP CMOS
process and an analog ADC chip fabricated on our BiMOS II
process. Both chips are contained in a single package.
The AD676 is specified for ac (or “dynamic”) parameters such
as S/(N+D) Ratio, THD and IMD which are important in sig-
nal processing applications. In addition, dc parameters are
specified which are important in measurement applications.
The AD676 operates from +5 V and ±12 V supplies and typi-
cally consumes 360 mW during conversion. The digital supply
(VDD) is separated from the analog supplies (VCC, VEE) for re-
duced digital crosstalk. An analog ground sense is provided for
the analog input. Separate analog and digital grounds are also
provided.
The AD676 is available in a 28-pin plastic DIP or 28-pin side-
brazed ceramic package. A serial-output version, the AD677, is
available in a 16-pin 300 mil wide ceramic or plastic package.
AD676–SPECIFICATIONS
AC SPECIFICATIONSFull Power Bandwidth
DIGITAL SPECIFICATIONSIIH
LOGIC OUTPUTS
VOH
NOTESVREF = 10.0 V, (Conversion Rate (fs) = 83 kSPS, fIN = 1.0 kHz, VIN = –0.05 dB, Bandwidth = fs/2 unless otherwise indicated. All measurements referred to a 0 dB
(20 V p-p) input signal. Values are post-calibration.For other input amplitudes, refer to Figure 13.For other input ranges/voltages reference values see Figure 12.fa = 1008 Hz. fb = 1055 Hz. See Definition of Specifications section and Figure 15.
Specifications subject to change without notice.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)1
(for all grades TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%)
DC SPECIFICATIONSACCURACY
ANALOG INPUT
POWER SUPPLIES
NOTESVREF = 5.0 V, Conversion Rate = 83 kSPS unless otherwise noted. Values are post-calibration.Values shown apply to any temperature from TMIN to TMAX after calibration at that temperature.Values shown are based upon calibration at +25°C with no additional calibration at temperature. Values shown are the worst case variation from the value at +25°C.See “APPLICATIONS” section for recommended voltage reference circuit, and Figure 12 for dynamic performance with other reference voltage values.See “APPLICATIONS” section for recommended input buffer circuit.
*For explanation of input characteristics, see “ANALOG INPUT” section.
Specifications subject to change without notice.
(TMIN to TMAX, VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 1O%)1
AD676
AD676
TIMING SPECIFICATIONSNOTESSee the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion time is specified to account for the droop of the
internal sample/hold function. Longer conversion times may degrade performance. See “General Conversion Guidelines” for additional explanation of maximum con-
version time.580 ns is recommended for optimal accuracy over temperature.tCH + tCL = tCLK and must be greater than 480 ns.
CAL
BUSY
CLK
tCH
tCL
tCLK
tCALB
tOD
tCT
CALHtFigure 1.Calibration Timing
Figure 2a.General Conversion Timing
(TMIN to TMAX VCC = +12 V 6 5%, VEE = –12 V 6 5%, VDD = +5 V 6 10%, VREF = 10.0 V)1
ORDERING GUIDENOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to the AD676/883 data sheet.D = Ceramic DIP.
ABSOLUTE MAXIMUM RATINGS*VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +26.4 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . –18 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Digital Inputs to DGND . . . . . . . . . . . . . . . . . . 0 V to +5.5 V
Analog Inputs, VREF to AGND
. . . . . . . . . . . . . . . . . . . . . . . (VCC + 0.3 V) to (VEE – 0.3 V)
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTIONThe AD676 features input protection circuitry consisting of large “distributed” diodes and
polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast,
low energy pulses (Charged Device Model). Per Method 3015.2 of MIL-STD-883C, the AD676
has been classified as a Category 1 Device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment, and discharge without detection. Unused devices must be stored in conductive foam
or shunts, and the foam discharged to the destination socket before devices are removed. For further
information on ESD Precaution. Refer to Analog Devices’ ESD Prevention Manual.
AD676
PIN DESCRIPTIONType: AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
Package Pinout
NYQUIST FREQUENCYAn implication of the Nyquist sampling theorem, the “Nyquist
frequency” of a converter is that input frequency which is one
half the sampling frequency of the converter.
TOTAL HARMONIC DISTORTIONTotal harmonic distortion (THD) is the ratio of the rms sum of
the harmonic components to the rms value of a full-scale input
signal and is expressed in percent (%) or decibels (dB). For in-
put signals or harmonics that are above the Nyquist frequency,
the aliased components are used.
SIGNAL-TO-NOISE PLUS DISTORTION RATIOSignal-to-noise plus distortion is defined to be the ratio of the
rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, includ-
ing harmonics but excluding dc.
GAIN ERRORThe last transition should occur at an analog value 1.5 LSB be-
low the nominal full scale (4.99977 volts for a ±5 V range). The
gain error is the deviation of the actual difference between the
first and last code transition from the ideal difference between
the first and last code transition.
BIPOLAR ZERO ERRORBipolar zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
DIFFERENTIAL NONLINEARITY (DNL)In an ideal ADC, code transitions are one LSB apart. Differen-
tial nonlinearity is the maximum deviation from this ideal value.
It is often specified in terms of resolution for which no missing
codes are guaranteed.
INTEGRAL NONLINEARITY (INL)The ideal transfer function for an ADC is a straight line bisect-
ing the center of each code drawn between “zero” and “full
scale.” The point used as “zero” occurs 1/2 LSB before the
most negative code transition. “Full scale” is defined as a level
1.5 LSB beyond the most positive code transition. Integral
nonlinearity is the worst-case deviation of a code center average
from the straight line.
BANDWIDTHThe full-power bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by 3 dB
for a full-scale input.
INTERMODULATION DISTORTION (IMD)With inputs consisting of sine waves at two frequencies, fa and
fb, any device with nonlinearities will create distortion products,
of order (m+n), at sum and difference frequencies of mfa ± nfb,
where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for
which m or n is not equal to zero. For example, the second or-
der terms are (fa + fb) and (fa – fb), and the third order terms
are (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb). The IMD
products are expressed as the decibel ratio of the rms sum of the
measured input signals to the rms sum of the distortion terms.
The two signals applied to the converter are of equal amplitude,
and the peak value of their sum is –0.5 dB from full scale. The
IMD products are normalized to a 0 dB input signal.
APERTURE DELAYAperture delay is the time required after SAMPLE pin is taken
LOW for the internal sample-hold of the AD676 to open, thus
holding the value of VlN.
APERTURE JITTERAperture jitter is the variation in the aperture delay from sample
to sample.
POWER SUPPLY REJECTIONDC variations in the power supply voltage will affect the overall
transfer function of the ADC, resulting in zero error and gain er-
ror changes. Power supply rejection is the maximum change in
either the bipolar zero error or gain error value. Additionally,
there is another power supply variation to consider. AC ripple
on the power supplies can couple noise into the ADC, resulting
in degradation of dynamic performance. This is displayed in
Figure 16.
INPUT SETTLING TIMESettling time is a function of the SHA’s ability to track fast
slewing signals. This is specified as the maximum time required
in track mode after a full-scale step input to guarantee rated
conversion accuracy.
AD676
FUNCTIONAL DESCRIPTIONThe AD676 is a multipurpose 16-bit analog-to-digital converter
and includes circuitry which performs an input sample/hold
function, ground sense, and autocalibration. These functions
are segmented onto two monolithic chips—an analog signal pro-
cessor and a digital controller. Both chips are contained within
the AD676 package.
The AD676 employs a successive-approximation technique to
determine the value of the analog input voltage. However, in-
stead of the traditional laser-trimmed resistor-ladder approach,
this device uses a capacitor-array, charge redistribution tech-
nique. Binary-weighted capacitors subdivide the input sample to
perform the actual analog-to-digital conversion. The capacitor
array eliminates variation in the linearity of the device due to
temperature-induced mismatches of resistor values. Since a ca-
pacitor array is used to perform the data conversions, the
sample/hold function is included without the need for additional
external circuitry.
Initial errors in capacitor matching are eliminated by an auto-
calibration circuit within the AD676. This circuit employs an
on-chip microcontroller and a calibration DAC to measure and
compensate capacitor mismatch errors. As each error is deter-
mined, its value is stored in on-chip memory (RAM). Subse-
quent conversions use these RAM values to improve conversion
accuracy. The autocalibration routine may be invoked at any
time. Autocalibration insures high performance while eliminat-
ing the need for any user adjustments and is described in detail
below.
The microcontroller controls all of the various functions within
the AD676. These include the actual successive approximation
algorithm, the autocalibration routine, the sample/hold opera-
tion, and the internal output data latch.
AUTOCALIBRATIONThe AD676 achieves rated performance without the need for
user trims or adjustments. This is accomplished through the use
of on-chip autocalibration.
In the autocalibration sequence, sample/hold offset is nulled by
internally connecting the input circuit to the ground sense cir-
cuit. The resulting offset voltage is measured and stored in
RAM for later use. Next, the capacitor representing the most
significant bit (MSB) is charged to the reference voltage. This
charge is then transferred to a capacitor of equal size (composed
of the sum of the remaining lower weight bits). The difference
in the voltage that results and the reference voltage represents
the amount of capacitor mismatch. A calibration digital-to-ana-
log converter (DAC) adds an appropriate value of error correc-
tion voltage to cancel this mismatch. This correction factor is
also stored in RAM. This process is repeated for each of the
capacitors representing the remaining top eight bits. The accu-
mulated values in RAM are then used during subsequent con-
versions to adjust conversion results accordingly.
As shown in Figure 1, when CAL is taken HIGH the AD676 in-
ternal circuitry is reset, the BUSY pin is driven HIGH, and the
ADC prepares for calibration. This is an asynchronous hard-
ware reset and will interrupt any conversion or calibration cur-
LOW and completes in 85,530 clock cycles, indicated by BUSY
going LOW. During calibration, it is preferable for SAMPLE to
be held LOW. If SAMPLE is HIGH, diagnostic data will appear
on Pins 5 and 6. This data is of no value to the user.
The AD676 requires one clock cycle after BUSY goes LOW to
complete the calibration cycle. If this clock cycle is not pro-
vided, it will be taken from the first conversion, likely resulting
in first conversion error.
In most applications, it is sufficient to calibrate the AD676 only
upon power-up, in which case care should be taken that the
power supplies and voltage reference have stabilized first. If not
calibrated, the AD676 accuracy may be as low as 10 bits.
CONVERSION CONTROLThe AD676 is controlled by two signals: SAMPLE and CLK, as
shown in Figures 2a and 2b. It is assumed that the part has been
calibrated and the digital I/O pins have the levels shown at the
start of the timing diagram.
A conversion consists of an input acquisition followed by 17
clock pulses which execute the 16-bit internal successive ap-
proximation routine. The analog input is acquired by taking the
SAMPLE line HIGH for a minimum sampling time of tS. The
actual sample taken is the voltage present on VIN one aperture
delay after the SAMPLE line is brought LOW, assuming the
previous conversion has completed (signified by BUSY going
LOW). Care should he taken to ensure that this negative edge is
well defined and jitter free in ac applications to reduce the un-
certainty (noise) in signal acquisition. With SAMPLE going
LOW, the AD676 commits itself to the conversion—the input at
VIN is disconnected from the internal capacitor array, BUSY
goes HIGH, and the SAMPLE input will be ignored until the
conversion is completed (when BUSY goes LOW). SAMPLE
must be held LOW for a minimum period of time tSL. A period
of time tSC after bringing SAMPLE LOW, the 17 CLK cycles
are applied; CLK pulses that start before this period of time are
ignored. BUSY goes HIGH tSB after SAMPLE goes LOW, sig-
nifying that a conversion is in process, and remains HIGH until
the conversion is completed. BUSY goes LOW during the 17th
CLK cycle at the point where the data outputs have changed
and are valid. The AD676 will ignore CLK after BUSY has
gone LOW and the output data will remain constant until a new
conversion is completed. The data can, therefore, be read any
time after BUSY goes LOW and before the 17th CLK of the
next conversion (see Figures 2a and 2b). The section on Micro-
processor Interfacing discusses how the AD676 can be inter-
faced to a 16-bit databus.
Typically BUSY would be used to latch the AD676 output data
into buffers or to interrupt microprocessors or DSPs. It is rec-
ommended that the capacitive load on BUSY be minimized by
driving no more than a single logic input. Higher capacitive
loads such as cables or multiple gates may degrade conversion
quality unless BUSY is buffered.
