AD671JD-750-AD671KD-500 Fast Delivery |IC PHOENIX CO.,LIMITED

AD671JD-750 ,Monolithic 12-Bit 2 MHz A/D ConverterSPECIFICATIONS unless otherwise noted)AD671J/S-750 AD671K-750Parameter Min Typ Max Min ..
AD671KD-500 ,Monolithic 12-Bit 2 MHz A/D ConverterFEATURES12-Bit ResolutionAIN BPO/UPO ENCODE REF IN ACOM DCO ..
AD673JD ,8-Bit A/D Converterspecifications.from –55°C to +125°C.Two package configurations are offered. All versions are also o ..
AD673JN ,8-Bit A/D ConverterSPECIFICATIONSAD673J AD673SModel Min Typ Max Min Typ Max UnitsRESOLUTION 8 8 BitslRELATIVE ACCURACY ..
AD673SD ,8-Bit A/D ConverterFEATURESComplete 8-Bit A/D Converter with Reference, Clockand Comparator DIGITALV VCC SS COMMON CON ..
AD674BAD ,Complete 12-Bit A/D ConvertersSpecifications subject to change without notice.
ADC0838CCN ,Serial I/O 8-Bit A/D Converters with Multiplexer OptionsGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC0838CCN/NOPB ,8-Bit Serial I/O A/D Converter with Multiplexer Option 20-PDIP -40 to 85FEATURES KEY SPECIFICATIONS2• TI MICROWIRE Compatible—Direct Interface to • Resolution: 8 BitsCOPS ..
ADC0838CCV ,Serial I/O 8-Bit A/D Converters with Multiplexer OptionsGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC0838CCWM ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC0838CCWM/NOPB ,8-Bit Serial I/O A/D Converter with Multiplexer Option 20-SOIC -40 to 85Electrical CharacteristicsThe following specifications apply for V = V+ = V = 5V, V≤ V +0.1V, T = T ..
ADC0838CCWMX ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..

AD671JD-750-AD671KD-500
Monolithic 12-Bit 2 MHz A/D Converter
FUNCTIONAL BLOCK DIAGRAM
REV.BMonolithic 12-Bit
2 MHz A/D Converter
FEATURES
12-Bit Resolution
24-Pin “Skinny DIP” Package
Conversion Time: 500 ns max—AD671J/K/S-500
Conversion Time: 750 ns max—AD671J/K/S-750
Low Power: 475 mW
Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input
Ranges (65 V)
Twos Complement or Offset Binary Output Data
Out-of-Range Indicator
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
The AD671 is a high speed monolithic 12-bit A/D converter
offering conversion rates of up to 2 MHz (500 ns conversion
time). The combination of a merged high speed bipolar/CMOS
process and a novel architecture results in a combination of
speed and power consumption far superior to previously avail-
able hybrid implementations. Additionally, the greater reliability
of monolithic construction offers improved system reliability
and lower costs than hybrid designs.
The AD671 uses a subranging flash conversion technique, with
digital error correction for possible errors introduced in the first
part of the conversion cycle. An on-chip timing generator pro-
vides strobe pulses for each of the four internal flash cycles and
assures adequate settling time for the interflash residue ampli-
fier. A single ENCODE pulse is used to control the converter.
The performance of the AD671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.
The AD671 is available in two conversion speeds and perfor-
mance grades. The AD671J and K grades are specified for op-
eration over the 0°C to +70°C temperature range. The AD671S
grades are specified for operation over the –55°C to +125°C
temperature range. All grades are available in a 0.300 inch wide
24-pin ceramic DIP. The J and K grades are also available in a
24-pin plastic DIP.
PRODUCT HIGHLIGHTS
1. The AD671 offers a single chip 2 MHz analog-to-digital
2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipo-
3. The external +5 V reference can be chosen to suit the dc ac-
4. Output data is available in unipolar, bipolar offset or bipolar
5. An OUT OF RANGE output bit indicates when the input
6. The AD671 is available in versions compliant with the MIL-
AD671–SPECIFICATIONS
DC SPECIFICATIONS
(TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 610%, VEE = –5 V 6 5%, VREF = +5.000 V,
unless otherwise noted)
POWER SUPPLIES
NOTESAdjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information.Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges.25°C to TMIN and 25°C to TMAX.Change in gain error as a function of the dc supply voltage.Tested under static conditions. See Figure 12 for typical curves of ILOGIC vs. Conversion Rate and Output Loading.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25°C and +70°C. Results from those tests are
used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested.
NOTESAdjustable to zero with external potentiometers. See Offset/Gain Calibration section for additional information.Full-scale range (FSR) is 5 V for the 0 V to 5 V range and 10 V for the 0 V to 10 V and –5 V to +5 V ranges.25°C to TMIN and 25°C to TMAX.Change in gain error as a function of the dc supply voltage.Tested under static conditions. See Figure 12 for typical curves of ILOGIC vs. Conversion Rate and Output Loading.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test with worst case supply voltages at 0, +25°C and +70°C. Results from those tests are
AD671
DC SPECIFICATIONS
(TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V 6 5%, VREF = +5.000 V,
unless otherwise noted)
AD671–SPECIFICATIONS
DIGITAL SPECIFICATIONS
(For all grades TMIN to TMAX, with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V
6 5%, VREF = +5.000 V, unless otherwise noted)
Specifications shown in boldface are tested on all devices at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max
specifications are guaranteed, although only those shown in boldface are tested.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
NOTEStDD is measured from when the falling edge of DAV crosses 0.8 V to when the output crosses 0.4 V or 2.4 V with a 25 pF load capacitor on each output pin.tSS is measured from when the outputs cross 0.4 V or 2.4 V to when the rising edge of DAV crosses 2.4 V with a 25 pF load capacitor on each output pin.
(For all grades TMIN to TMAX with VCC = +5 V 6 5%, VLOGIC = +5 V 6 10%, VEE = –5 V
6 5%, VIL = 0.8 V, VIH = 2.0 V, VOL = 0.4 V and VOH = 2.4 V)
Figure 1.AD671 Timing Diagrams
a. Encode Pulse HIGH b. Encode Pulse LOW
ORDERING GUIDE
NOTESFor details on grade and package offerings screened in accordance with
MIL-STD-883, refer to the Analog Devices Military Products Databook or
current AD671/883 data sheet.D = Ceramic DIP.
ABSOLUTE MAXIMUM RATINGS*
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum ratings for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD671 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD671
AD671 PIN DESCRIPTION
VEE
TYPE:
AI = Analog Input
DI = Digital Input
DO = Digital Output
P = Power
CONNECTION DIAGRAM
PINOUT
BIT12 (LSB)
BIT11
BIT10
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1 (MSB)MSB
OTR
DAV
ENCODE
DCOM
REF IN
AIN
BPO/UPO
ACOM
VCC
VEE
VLOGIC
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB (1.22 mV for a 10 V span)
before the first code transition (all zeros to only the LSB on).
“Full scale” is defined as a level 1 1/2 LSB beyond the last code
transition (to all ones). The deviation is measured from the low
side transition of each particular code to the true straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. Guaranteed no missing codes to
10-bit resolution indicates that all 1024 codes represented by
Bits 1–10 must be present over all operating ranges. Guaranteed
no missing codes to 11- or 12-bit resolution indicates that all
2048 and 4096 codes, respectively, must be present over all op-
erating ranges.
UNIPOLAR OFFSET
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the ac-
tual from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature, with
or without external adjustments.
BIPOLAR ZERO
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
GAIN ERROR
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 volts for 10.000 volts full scale). The gain er-
ror is the deviation of the actual level at the last transition from
the ideal level. The gain error can be adjusted to zero as shown
in Figures 7, 8 and 9.
TEMPERATURE COEFFICIENTS
The temperature coefficients for unipolar offset, bipolar zero
and gain error specify the maximum change from the initial
(+25°C) value to the value at TMIN or TMAX.
POWER SUPPLY REJECTION
The only effect of power supply error on the performance of the
device will be a small change in gain. The specifications show
the maximum full-scale change from the initial value with the
supplies at the various limits.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components, including har-
monics but excluding dc. The value for S/N+D is expressed in
decibels.
EFFECTIVE NUMBER OF BITS (ENOB)
ENOB is calculated from the expression SNR = 6.02N +
1.8 dB, where N is equal to the effective number of bits.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is ex-
pressed as a percentage or in decibels.
PEAK SPURIOUS OR PEAK HARMONIC COMPONENT
The peak spurious or peak harmonic component is the largest
spectral component excluding the input signal and dc. This
value is expressed in decibels relative to the rms value of a full-
scale input signal.
Theory of Operation
The AD671 uses a successive subranging architecture. The ana-
log to digital conversion takes place in four independent steps or
flashes. The analog input signal is subranged to an intermediate
residue voltage for the final 12-bit result by utilizing multiple
flashes with subtraction DACs (see the AD671 functional block
diagram).
The AD671 can be configured to operate with unipolar (0 V to
+5 V, 0 V to +10 V) or bipolar (±5 V) inputs by connecting
AIN (Pin 20), REFIN (Pin 19) and BPO/UPO (Pin 21) as
shown in Figure 2.
The AD671 conversion cycle begins by simply providing an ac-
tive HIGH pulse on the ENCODE pin (Pin 16). The rising
edge of the ENCODE pulse starts the conversion. The falling
(AD671-500) and less than 50 ns after the falling edge of
ENCODE (AD671–750) or after the falling edge of DAV. The
time window prevents digitally coupled noise from being intro-
duced during the final stages of conversion. An internal timing
generator circuit accurately controls all internal timing.
AD671
Upon receipt of an ENCODE command, the first 3-bit flash
converts the analog input voltage. The 3-bit result is passed to a
correction logic register and a segmented current output DAC.
The DAC output is connected through a resistor (within the
Range/Span Select Block) to AIN. A residue voltage is created
by subtracting the DAC output from AIN, which is less than
one eighth of the full-scale analog input. The second flash has
an input range that is configured with one bit of overlap with the
previous DAC. The overlap allows for errors during the flash
conversion. The first residue voltage is connected to the second
3-bit flash and to the noninverting input of a high speed, differ-
ential, gain-of-four amplifier. The second flash result is passed
to the correction logic register and to the second segmented cur-
rent output DAC. The output of the second DAC is connected
to the inverting input of the differential amplifier. The differen-
tial amplifier output is connected to a two step backend 8-bit
flash. This 8-bit flash consists of coarse and fine flash convert-
ers. The result of the coarse 4-bit flash converter, also config-
ured to overlap one bit of DAC 2, is connected to the correction
logic register and selects one of 16 resistors from which the fine
4-bit flash will establish its span voltage. The fine 4-bit flash is
connected directly to the output latches.
The AD671 will flag an out-of-range condition when the input
voltage exceeds the analog input range. OTR (Pin 14) is active
HIGH when an out of range high or low condition exists. Bits
1–12 are HIGH when the analog input voltage is greater than
the selected input range and LOW when the analog input is less
than the selected input range.
APPLYING THE AD671
DRIVING THE AD671 ANALOG INPUT
The AD671 uses a very high speed current output DAC to sub-
tract a known voltage from the analog input. This results in very
fast steps of current at the analog input. It is important to recog-
nize that the signal source driving the analog input of the
AD671 must be capable of maintaining the input voltage under
dynamically-changing load conditions. When the AD671 starts
its conversion cycle, the subtraction DAC will sink up to 5 mA
(see Figure 3) from the source driving the analog input. The
source must respond to this current step by settling the input
voltage back to a fraction of an LSB before the AD671 makes its
final 12-bit decision.
Figure 3.Driving the Analog Input
Unlike successive approximation A/Ds, where the input voltage
must settle to a fraction of a 12-bit LSB before each successive
bit decision is made, the AD671 requires the analog input volt-
age settle to within 12 bits before the third flash conversion,
approximately 200 ns. This “free” 200 ns is useful in applica-
INPUT BUFFER AMPLIFIER
The closed-loop output impedance of an op amp is equal to the
open loop output impedance (usually a few hundred ohms) di-
vided by the loop gain at the frequency of interest. It is often
assumed that loop gain of a follower-connected op amp is suffi-
ciently high to reduce the closed-loop output impedance to a
negligibly small value, particularly if the input signal is low
frequency. At higher frequencies the open-loop gain is lower,
increasing the output impedance which decreases the instanta-
neous analog input voltage and produces an error.
The recommended wideband, fast settling input amplifiers for
use with the AD671 are the AD841, AD843, AD845 or the
AD847. The AD841 is unity gain stable and recommended as a
follower connected op amp. The AD843 and AD845 FET in-
puts make them ideal for high speed sample-and-hold amplifiers
and the AD847 can be used as a low power, high speed buffer.
Figure 4 shows the AD841 driving the AD671. As shown in the
figure the analog input voltage should be produced with respect
to the ACOM pin.
Figure 4.Input Buffer Amplifier
REFERENCE INPUT
The AD671 uses a standard +5 volt reference. The initial accu-
racy and temperature stability of the reference can be selected to
meet specific system requirements. Like the analog input, fast
switching input-dependent currents are modulated at the refer-
ence input pin (REF IN–Pin 19). However, unlike the analog
input the reference input is held at a constant +5 volts with the
use of capacitor. The recommended reference is the AD586, a
+5 V precision reference with an output buffer amplifier. Fig-
ure 5 shows the AD671 configured in the ±5 V input range.
The 6.8 μF capacitor maintains a constant +5 volts under the
dynamically changing load conditions. An optional 1 μF noise
reduction capacitor can be connected to the AD586, further re-
ducing broadband output noise. To minimize ground voltage
drops the AD586’s ground pin should be tied as close as pos-
sible to the AD671’s ACOM pin. See Figures 20, 21 and 22 for
PCB layout recommendations.

Partno	Mfg	Dc	Qty	Available	Descript
AD671JD-750 \|AD671JD750	AD	N/a	4	avai	Monolithic 12-Bit 2 MHz A/D Converter
AD671KD-500 \|AD671KD500		N/a	1	avai	Monolithic 12-Bit 2 MHz A/D Converter