AD669AN ,Monolithic 16-Bit DACPORTCHARACTERISTICSOutput Voltage RangeUnipolar Configuration 0 +10 * * * * VoltsBipolar Configuration ..
AD669AN ,Monolithic 16-Bit DACPORTGENERAL DESCRIPTION PRODUCT HIGHLIGHTS®The AD669 DACPORT is a complete 16-bit monolithic D/A 1. The ..
AD669ANZ , Monolithic 16-Bit DACPORT
AD669AR ,Monolithic 16-Bit DACPORTapplications.while differential nonlinearity is ±0.003% max. The on-chip4. The double-buffered latc ..
AD669AR ,Monolithic 16-Bit DACPORTspecifications and test conditions.DACPORT is a registered trademark of .REV. AInformation furnishe ..
AD669BN ,Monolithic 16-Bit DACPORTFEATURESComplete 16-Bit D/A FunctionOn-Chip Output Amplifier (MSB) (LSB)DB15 DB0High Stability Buri ..
ADC0834CCWMX ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC0834CIWM ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC08351CILQ ,8-Bit, 42 MSPS, 40 mW A/D ConverterGeneral Descriptionn Power Down FeatureTheADC08351 is an easy to use low power, low cost, smalln TR ..
ADC08351CILQX/NOPB ,8-bit, 42 MSPS, 40 mW A/D Converter 24-WQFN -20 to 85 SNAS026E –JUNE 2000–REVISED MARCH 2013(1)PIN DESCRIPTIONS AND EQUIVALENT CIRCUITSPinSymbol Equival ..
ADC08351CIMTC ,8-Bit, 42 MSPS, 40 mW A/D ConverterPin Descriptions and Equivalent Circuits (LLP pins in parentheses)PinSymbol Equivalent Circuit Desc ..
ADC08351CIMTCX ,8-Bit/ 42 MSPS/ 40 mW A/D ConverterPin Descriptions and Equivalent CircuitsPinSymbol Equivalent Circuit DescriptionNo.Analog signal in ..
AD669AN-AD669AR-AD669BN-AD669BR-AD669SQ
Monolithic 16-Bit DACPORT
FUNCTIONAL BLOCK DIAGRAMREV.A
Monolithic 16-Bit
DACPORT
FEATURES
Complete 16-Bit D/A Function
On-Chip Output Amplifier
High Stability Buried Zener Reference
Monolithic BiMOS II Construction61 LSB Integral Linearity Error
15-Bit Monotonic over Temperature
Microprocessor Compatible
16-Bit Parallel Input
Double-Buffered Latches
Fast 40 ns Write Pulse
Unipolar or Bipolar Output
Low Glitch: 15 nV-s
Low THD+N: 0.009%
MIL-STD-883 Compliant Versions Available
GENERAL DESCRIPTIONThe AD669 DACPORT® is a complete 16-bit monolithic D/A
converter with an on-board reference and output amplifier. It is
manufactured on Analog Devices’ BiMOS II process. This pro-
cess allows the fabrication of low power CMOS logic functions
on the same chip as high precision bipolar linear circuitry. The
AD669 chip includes current switches, decoding logic, an output
amplifier, a buried Zener reference and double-buffered latches.
The AD669’s architecture insures 15-bit monotonicity over
temperature. Integral nonlinearity is maintained at ±0.003%,
while differential nonlinearity is ±0.003% max. The on-chip
output amplifier provides a voltage output settling time of 10 μs
to within 1/2 LSB for a full-scale step.
Data is loaded into the AD669 in a parallel 16-bit format. The
double-buffered latch structure eliminates data skew errors and
provides for simultaneous updating of DACs in a multi-DAC
system. Three TTL/LSTTL/5 V CMOS compatible signals con-
trol the latches: CS, L1 and LDAC.
The output range of the AD669 is pin programmable and can
be set to provide a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V.
The AD669 is available in seven grades: AN and BN versions
are specified from –40°C to +85°C and are packaged in a 28-pin
plastic DIP. The AR and BR versions are specified for –40°C to
+85°C operation and are packaged in a 28-pin SOIC. The SQ
version is specified from –55°C to +125°C and is packaged in a
hermetic 28-pin cerdip package. The AD669 is also available
compliant to MIL-STD-883. Refer to the AD669/883B data
sheet for specifications and test conditions.
DACPORT is a registered trademark of Analog Devices, Inc.
PRODUCT HIGHLIGHTS1. The AD669 is a complete voltage output 16-bit DAC with
voltage reference and digital latches on a single IC chip.
2. The internal buried Zener reference is laser trimmed to
10.000 volts with a ±0.2% maximum error. The reference
voltage is also available for external applications.
3. The AD669 is both dc and ac specified. DC specs include
±1 LSB INL error and ±1 LSB DNL error. AC specs include
0.009% THD+ N and 83 dB SNR. The ac specifications
make the AD669 suitable for signal generation applications.
4. The double-buffered latches on the AD669 eliminate data
skew errors while allowing simultaneous updating of DACs in
multi-DAC systems.
5. The output range is a pin-programmable unipolar 0 V to
+10 V or bipolar –10 V to +10 V output. No external compo-
nents are necessary to set the desired output range.
6. The AD669 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD669/883B data sheet for detailed
specifications.
AD669–SPECIFICATIONSTRANSFER FUNCTION CHARACTERISTICS
NOTESFor 16-bit resolution, 1 LSB = 0.0015% of FSR = 15 ppm of FSR. For 15-bit resolution, 1 LSB = 0.003% of FSR = 30 ppm of FSR. For 14-bit resolution
1 LSB = 0.006% of FSR = 60 ppm of FSR. FSR stands for Full-Scale Range and is 10 V for a 0 V to + 10 V span and 20 V for a –10 V to +10 V span.Gain error and gain drift measured using the internal reference. Gain drift is primarily reference related. See the Using the AD669 with the AD688 Reference section
for further information.External current is defined as the current available in addition to that supplied to REF IN and SPAN/BIPOLAR OFFSET on the AD669.Operation on ±12 V supplies is possible using an external reference like the AD586 and reducing the output range. Refer to the Internal/External Reference Use section.Measured with fixed 50 Ω resistors. Eliminating these resistors increases the gain error by 0.25% of FSR (Unipolar mode) or 0.50% of FSR (Bipolar mode). Refer to
the Analog Circuit Connections section.
(@ TA = +258C, VCC = +15 V, VEE = –15 V, VLL = +5 V, unless otherwise noted)
TIMING CHARACTERISTICS
VCC = +15 V, VEE = –15 V, VLL = +5 V, VHI = 2.4 V, VLO = 0.4 V(Figure la)
tCS
tLI
tDS
tDH
tLH
(Figure lb)
tLOW
tHIGH
tDS
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical
test. Results from those tests are used to calculate outgoing quality levels. All
min and max specifications are guaranteed. Those shown in boldface are tested
on all production units.
AC PERFORMANCE CHARACTERISTICSOutput Noise Voltage
Specifications subject to change without notice.
Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed. Those shown in boldface are tested on all production units.
(With the exception of Total Harmonic Distortion + Noise and Signal-to-Noise
Ratio, these characteristics are included for design guidance only and are not subject to test. THD+N and SNR are 100% tested.
TMIN ≤ TA ≤ TMAX, VCC = +15 V, VEE = –15 V, VLL = +5 V except where noted.)
AD669
ORDERING GUIDE**N = Plastic DIP; Q = Cerdip; R = SOIC.
**Refer to AD669/883B military data sheet.
ESD SENSITIVITYThe AD669 features input protection circuitry consisting of large transistors and polysilicon series
resistors to dissipate both high-energy discharges (Human Body Model) and fast, low-energy pulses
(Charged Device Model). Per Method 3015.2 of MIL-STD-883: C, the AD669 has been classified
as a Class 2 device.
Proper ESD precautions are strongly recommended to avoid functional damage or performance
degradation. Charges as high as 4000 volts readily accumulate on the human body and test
equipment and discharge without detection. Unused devices must be stored in conductive foam or
shunts, and the foam should be discharged to the destination socket before devices are removed.
For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual.
ABSOLUTE MAXIMUM RATINGS*VCC to AGND . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +17.0 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17.0 V
VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±1 V
Digital Inputs (Pins 5 through 23) to DGND . . . . . .–1.0 V to
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0 V
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10.5 V
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . .±10.5 V
REF OUT, VOUT . . . . . .Indefinite Short To AGND, DGND,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC, VEE, and VLL
Power Dissipation (Any Package)
To +60°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 mW
Derates above +60°C . . . . . . . . . . . . . . . . . . . . . .8.7 mW/°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .+300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DEFINITIONS OF SPECIFICATIONSINTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS–1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be within ±1 LSB over the temperature range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD669 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/°C, is calculated by
measuring the parameter at TMIN, 25°C and TMAX and dividing
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing upon the amplitude of the output signal. Therefore, to be
the most useful, THD+N should be specified for both large and
small signal amplitudes.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
THEORY OF OPERATIONThe AD669 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 mA to 2 mA. A seg-
mented architecture is used, where the most significant four
data bits are thermometer decoded to drive 15 equal current
sources. The lesser bits are scaled using a R-2R ladder, then ap-
plied together with the segmented sources to the summing node
of the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to +10 V
span, or it can be connected to the reference input to provide a
–10 V to +10 V span.
ANALOG CIRCUIT CONNECTIONSInternal scaling resistors provided in the AD669 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD669 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATIONThe configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50 Ω resistors are tied
between the span/bipolar offset terminal (Pin 26) and VOUT (Pin
25), and between REF OUT (Pin 28) and REF IN (Pin 27). It
is possible to use the AD669 without any external components
by tying Pin 28 directly to Pin 27 and Pin 26 directly to Pin 25.
Eliminating these resistors will increase the gain error by 0.25%
of FSR.
AD669If it is desired to adjust the gain and offset errors to zero, this
can be accomplished using the circuit shown in Figure 3b. The
adjustment procedure is as follows:
STEP1 . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R4, until the output
reads 0.000000 volts (1 LSB = 153 μV).
STEP 2 . . . GAIN ADJUST
Turn all bits ON and adjust gain trimmer, R1, until the output
is 9.999847 volts. (Full scale is adjusted to 1 LSB less than the
nominal full scale of 10.000000 volts).
OUTPUT
GND
LDAC
DB15
(MSB)(LSB)
DB0143
50V
16kVR4
10kV
+15V
–15V
100V
–VEE+VCC+VLLFigure 3b.0 V to +10 V Unipolar Voltage Output with
Gain and Offset Adjustment
BIPOLAR CONFIGURATIONThe circuit shown in Figure 4a will provide a bipolar output
voltage from –10.000000 V to +9.999694 V with positive full
scale occurring with all bits ON. As in the unipolar mode, resis-
tors R1 and R2 may be eliminated altogether to provide AD669
bipolar operation without any external components. Eliminating
these resistors will increase the gain error by 0.50% of FSR in
the bipolar mode.
50VOUTPUT
GND
LDAC
DB15
(MSB)(LSB)
DB0
10kV
AMP
AD6697143
10kV
10.05kV25
50V
–VEE+VCC+VLLFigure 4a.±10 V Bipolar Voltage Output
Gain offset and bipolar zero errors can be adjusted to zero using
the circuit shown in Figure 4b as follows:
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust trimmer R2 to give –10.000000 volts
output.
STEP II . . . GAIN ADJUST
STEP III . . . BIPOLAR ZERO ADJUST
(Optional) In applications where an accurate zero output is re-
quired, set the MSB ON, all other bits OFF, and readjust R2
for zero volts output.
100V
OUTPUT
GND
LDAC
DB15
(MSB)(LSB)
DB0
10kV
AMP
AD6697143
10kV
10.05kV25
100V
–VEE+VCC+VLLFigure 4b.±10 V Bipolar Voltage Output with Gain and
Offset Adjustment
It should be noted that using external resistors will introduce a
small temperature drift component beyond that inherent in the
AD669. The internal resistors are trimmed to ratio-match and
temperature-track other resistors on chip, even though their ab-
solute tolerances are ±20% and absolute temperature coeffi-
cients are approximately –50 ppm/°C. In the case that external
resistors are used, the temperature coefficient mismatch be-
tween internal and external resistors, multiplied by the sensitiv-
ity of the circuit to variations in the external resistor value, will
be the resultant additional temperature drift.
INTERNAL/EXTERNAL REFERENCE USEThe AD669 has an internal low noise buried Zener diode refer-
ence which is trimmed for absolute accuracy and temperature
coefficient. This reference is buffered and optimized for use in a
high speed DAC and will give long-term stability equal or supe-
rior to the best discrete Zener diode references. The perfor-
mance of the AD669 is specified with the internal reference
driving the DAC since all trimming and testing (especially for
gain and bipolar offset) is done in this configuration.
The internal reference has sufficient buffering to drive external
circuitry in addition to the reference currents required for the
DAC (typically 1 mA to REF IN and 1 mA to BIPOLAR OFF-
SET). A minimum of 2 mA is available for driving external
loads. The AD669 reference output should be buffered with an
external op amp if it is required to supply more than 4 mA total
current. The reference is tested and guaranteed to ±0.2% max
error. The temperature coefficient is comparable to that of the
gain TC for a particular grade.
If an external reference is used (10.000 V, for example), addi-
tional trim range should be provided, since the internal refer-
ence has a tolerance of ±20 mV, and the AD669 gain and
bipolar offset are both trimmed with the internal reference. The
optional gain and offset trim resistors in Figures 5 and 6 provide
