AD668JQ ,12-Bit Ultrahigh Speed Multiplying D/A ConverterSPECIFICATIONSA CC EE AD668J/A AD668K AD668SParameter Min Typ Max Min Typ Max Min ..
AD669AN ,Monolithic 16-Bit DACPORTCHARACTERISTICSOutput Voltage RangeUnipolar Configuration 0 +10 * * * * VoltsBipolar Configuration ..
AD669AN ,Monolithic 16-Bit DACPORTGENERAL DESCRIPTION PRODUCT HIGHLIGHTS®The AD669 DACPORT is a complete 16-bit monolithic D/A 1. The ..
AD669ANZ , Monolithic 16-Bit DACPORT
AD669AR ,Monolithic 16-Bit DACPORTapplications.while differential nonlinearity is ±0.003% max. The on-chip4. The double-buffered latc ..
AD669AR ,Monolithic 16-Bit DACPORTspecifications and test conditions.DACPORT is a registered trademark of .REV. AInformation furnishe ..
ADC0834CCWM ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC0834CCWMX ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC0834CIWM ,8-Bit Serial I/O A/D Converter with Multiplexer OptionGeneral Descriptionn No zero or full-scale adjust requiredTheADC0831seriesare8-bitsuccessiveapproxi ..
ADC08351CILQ ,8-Bit, 42 MSPS, 40 mW A/D ConverterGeneral Descriptionn Power Down FeatureTheADC08351 is an easy to use low power, low cost, smalln TR ..
ADC08351CILQX/NOPB ,8-bit, 42 MSPS, 40 mW A/D Converter 24-WQFN -20 to 85 SNAS026E –JUNE 2000–REVISED MARCH 2013(1)PIN DESCRIPTIONS AND EQUIVALENT CIRCUITSPinSymbol Equival ..
ADC08351CIMTC ,8-Bit, 42 MSPS, 40 mW A/D ConverterPin Descriptions and Equivalent Circuits (LLP pins in parentheses)PinSymbol Equivalent Circuit Desc ..
AD668AQ-AD668JQ
12-Bit Ultrahigh Speed Multiplying D/A Converter
FUNCTIONAL BLOCK DIAGRAMREV.A
12-Bit Ultrahigh Speed
Multiplying D/A Converter
FEATURES
Ultrahigh Speed: Current Settling to 1 LSB in 90 ns for
a Full-Scale Change in Digital Input. Voltage Settling
to 1 LSB in 120 ns for a Full-Scale Change in Analog
Input
15 MHz Reference Bandwidth
Monotonicity Guaranteed over Temperature
10.24 mA Current Output or 1.024 V Voltage Output
Integral and Differential Linearity Guaranteed over
Temperature
0.3" “Skinny DIP” Packaging
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTIONThe AD668 is an ultrahigh speed, 12-bit, multiplying digital-to-
analog converter, providing outstanding accuracy and speed per-
formance in responding to both analog and digital inputs. The
AD668 provides a level of performance and functionality in a
monolithic device that exceeds that of many contemporary hy-
brid devices. The part is fabricated using Analog Devices’
Complementary Bipolar (CB) Process, which features vertical
NPN and PNP devices on the same chip without the use of
dielectric isolation. The AD668’s design capitalizes on this pro-
prietary process in combination with standard low impedance
circuit techniques to provide its unique combination of speed
and accuracy in a monolithic part.
The wideband reference input is buffered by a high gain, closed
loop reference amplifier. The reference input is essentially a 1 V,
high impedance input, but trimmed resistive dividers are pro-
vided to readily accommodate 5 V and 1.25 V references. The
reference amplifier features an effective small signal bandwidth
of 15 MHz and an effective slew rate of 3% of full scale/ns.
Multiple matched current sources and thin film ladder tech-
niques are combined to produce bit weighting. The output range
can nominally be taken as a 10.24 mA current output or a 1.024 V
voltage output. Varying the analog input can provide modulation
of the DAC full scale from 10% to 120% of its nominal value.
Bipolar outputs can be realized through pin-strapping to provide
two-quadrant operation without additional external circuitry.
Laser wafer trimming insures full 12-bit linearity and excellent
gain accuracy. All grades of the AD668 are guaranteed mono-
tonic over their full operating temperature range. Furthermore,
the output resistance of the DAC is trimmed to 100 Ω ± 1.0%.
The AD668 is available in four performance grades. The
AD668JQ and KQ are specified for operation from 0°C to
+70°C, the AD668AQ is specified for operation from –40°C to
+85°C, and the AD668SQ specified for operation from –55°C
to +125°C. All grades are available in a 24-pin cerdip (0.3"
package.
PRODUCT HIGHLIGHTS1. The fast settling time of the AD668 provides suitable perfor-
mance for waveform generation, graphics display, and high
speed A/D conversion applications.
2. The high bandwidth reference channel allows high frequency
modulation between analog and digital inputs.
3. The AD668’s design is configured to allow wide variation of
the analog input, from 10% to 120% of its nominal value.
4. The AD668’s combination of high performance and tremen-
dous flexibility makes it an ideal building block for a variety
of high speed, high accuracy instrumentation applications.
5. The digital inputs are readily compatible with both TTL and
5 V CMOS logic families.
6. Skinny DIP (0.3") packaging minimizes board space require-
ments and eases layout considerations.
7. The AD668 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD668/883B data sheet for detailed
specifications.
AD668–SPECIFICATIONS(@ TA = +258C, VCC = +15 V, VEE = –15 V, unless otherwise noted)TEMPERATURE COEFFICIENTS
REFERENCE INPUT
FULL-SCALE TRANSITION
POWER REQUIREMENTS
TEMPERATURE RANGE
NOTES
*Same as AD668J/A.Measured in IOUT mode. Specified at nominal 5 V full-scale reference.Measured in VOUT mode, unless otherwise specified. Specified at nominal 5 V
full-scale reference.Total resistance. Refer to Figure 4.At the major carry, driven by HCMOS logic.VOUT = 1 V p-p, VIN = 10% to 110%, 100 kHz. Digital Input All 1s.VIN = 200 mV p-p, 1 MHz Sine Wave. Digital Input all 0s. See Figure 20.Measured at 15 V ± 10% and 12 V ±10%.
Specifications shown in boldface are tested on all producfion units at final elec-
trical test.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*VCC to REFCOM . . . . . . . . . . . . . . . . . . . . . . . .0 V to +18 V
VEE to REFCOM . . . . . . . . . . . . . . . . . . . . . . . . . .0 V to –18 V
REFCOM to LCOM . . . . . . . . . . . . . . . . . .+100 mV to –10 V
ACOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . .±100 mV
THCOM to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . .±500 mV
REFCOM to REFIN (1, 2) . . . . . . . . . . . . . . . . . . . . . . . .18 V
IBPO to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±5 V
IOUT to LCOM . . . . . . . . . . . . . . . . . . . . . . . . . . . .–5 V to VTH
Digital Inputs to THCOM . . . . . . . . . . . . .–500 mV to +7.0 V
REFIN1 to REFIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 V
VTH to THCOM . . . . . . . . . . . . . . . . . . . . . .–0.7 V to +1.4 V
Logic Threshold Control Input Current . . . . . . . . . . . . .5 mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .670 mW
Storage Temperature Range
Q (Cerdip) Package . . . . . . . . . . . . . . . . . .–65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Thermal Resistance
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+75°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25°C/W
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD668
AD668
ORDERING GUIDENOTESFor details on grade and package offerings screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook or current AD668/883B data sheet.Q = Cerdip.
DEFINITIONSLINEARITY ERROR (also called INTEGRAL NONLINEAR-
ITY OR INL): Analog Devices defines linearity error as the
maximum deviation of the actual analog output from the ideal
output (a straight line drawn from 0 to FS) for any bit combina-
tion expressed in multiples of 1 LSB. The AD668 is laser
trimmed to 1/4 LSB (0.006% of FS) maximum linearity error at
+25°C for the K version and 1/2 LSB for the J and S versions.
DIFFERENTIAL LINEARITY ERROR (also called DIFFER-
ENTIAL NONLINEARITY or DNL): DNL is the measure of
the variation in the analog output, normalized to fun scale, asso-
ciated with a 1 LSB change in digital input code.
MONOTONICITY: A DAC is said to be monotonic if the out-
put either increases or remains constant as the digital input in-
creases. Monotonic behavior requires that the differential
linearity error not exceed 1 LSB in the negative direction.
UNIPOLAR OFFSET ERROR (DAC OFFSET): The DAC
offset is the portion of the DAC output that is independent of
the digital input. The unipolar DAC offset error is measured as
the deviation of the analog output from the ideal (0 V or 0 mA)
when the analog input is set to 100% and the digital inputs are
set to all 0s.
BIPOLAR OFFSET ERROR: The deviation of the analog out-
put from the ideal (negative half-scale) when the DAC is con-
nected in the bipolar mode (Pin 16 connected to Pin 20), the
analog input is set to 100%, and the digital inputs are set to all
0s is called the bipolar offset error.
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal (0 V or 0 mA) for bipolar mode when only the
MSB is on (100 . . . 00) is called bipolar zero error.
COMPLIANCE VOLTAGE: The allowable voltage excursion
at the output node of a DAC which will not degrade the accu-
racy of the DAC output.
SETTLING TIME (DIGITAL CHANNEL): The time re-
quired for the output to reach and remain within a specified
error band about its final value, measured from the digital input
transition.
SETTLING TIME (ANALOG CHANNEL): The time re-
quired for the output to reach and remain within a specified er-
ror band about its final value, measured from the analog input’s
crossing of it’s 50% value.
GAIN ERROR: The difference between the ideal and actual
output span of FS – 1 LSB, expressed either in % of FS or LSB,
PIN CONFIGURATION
ANALOG OFFSET ERROR: The analog offset is defined as
the offset of the analog amplifier channel, referred to the analog
input. Ideally, this would be measured with the analog input at
0 V and the digital input at full scale. Since a 0 V analog input
voltage constitutes an undervoltage condition, this specification
is determined through linear extrapolation, as indicated in
Figure 1.
Figure 1.Derivation of Analog Offset Voltage
GLITCH IMPULSE: Asymmetrical switching times in a DAC
may give rise to undesired output transients which are quanti-
fied by their glitch impulse. It is specified as the net area of the
glitch in pV-sec.
Figure 2.AD668 Major Carry Glitch
FUNCTIONAL DESCRIPTIONThe AD668 is designed to combine excellent performance with
maximum flexibility. The functional block diagram and the
simple transfer functions provided below will provide the user
with a basic grasp of the AD668’s operation. Examples of typi-
cal circuit configurations are provided in the section APPLY-
ING THE AD668. Subsequent sections contain more detailed
information useful in optimizing DAC performance in high
speed, high resolution applications.
DAC Transfer FunctionThe AD668 may be used either in a current output mode (DAC
In current output mode:
Unipolar Mode OUT=VINNOMDACcode
4096×10.24mA
Bipolar Mode OUT=VINNOMDACcode
4096×10.24mA±VINNOM5.12mA
In voltage output mode:VOUT=IOUT×RLOAD
(for both unipolar and bipolar modes)
where:
VIN – the analog input voltage.
VNOM – the nominal full scale of the reference voltage: 1 V,
1.25 V, or 5 V, determined by the wiring configuration of Pins
21 and 22. (See APPLYING THE AD668.)
DAC code – the numerical representation of the DAC’s digital
inputs; a number between 0 and 4095.
RLOAD – the resistance of the DAC output node; the maximum
this can be is 200 Ω (the internal DAC ladder resistance). The
on-board load resistor (Pin 19) has been trimmed so that its
parallel combination with the DAC ladder resistance is 100 Ω
(±1%)
Bipolar mode – produces a bipolar analog output from the digital
input by offsetting the normal output current with a precision
current source. This offset is achieved by connecting Pin 16 to
the DAC output. In the unipolar mode, Pin 16 should be
grounded.
If the dc errors are included, the transfer function becomes
somewhat more complex:
IOUT=VIN
VNOM+OFFSETANALOG×DACcode
4096×(1+E)×10.24mA
+OFFSETDIGITAL×
VIN
VNOM×10.24mA
VIN
VNOM+OFFSETANALOG×(5.12mA+[OFFSETBIPOLAR×10.24mA])
(Last term is for use in bipolar mode; VOUT is still just IOUT ×
RLOAD)
where:
OFFSETANALOG = the analog offset error.
OFFSETDIGITAL = is the unipolar digital offset error.
OFFSETBIPOLAR = is the bipolar offset error.
E = the gain error, expressed fractionally.
Operating Limits:
AD668 0.1
0 < VIN/VNOM < 0.1 constitutes an undervoltage condition and
is subject to the specified recovery time.
1.2 < VIN/VNOM constitutes an overvoltage condition. This can
saturate the DAC transistors, resulting in decreased response
time and can, over extended time, damage the part through ex-
cessive power dissipation. Figure 3 indicates the specified re-
gions of operation in both the unipolar and bipolar cases.
The small signal 3 dB bandwidth of the VIN channel is 15 MHz.
The large signal 3 dB bandwidth is approximately 10 MHz.
VOUT is limited by the specified output compliance: –2 V to
+1.2 V.
Figure 3.Quadrant Plots of the AD668
CIRCUIT DESCRIPTION OF THE AD668
Successful design of high speed, high resolution systems de-
mands a designer’s solid working knowledge of the components
being used. The AD668 has been carefully configured to pro-
vide maximum functionality in a variety of applications. While it
is beyond the scope of this data sheet to exhaustively cover each
potential application topology, the detailed information that
follows is intended to provide the designer with a sufficiently
thorough understanding of the part’s inner workings to allow
selection of the circuit topology to best suit the application.
CURRENT OUTPUT VS. VOLTAGE-OUTPUT
As indicated in the FUNCTIONAL DESCRIPTION, the
AD668 output may be taken as either a voltage or a current,
depending on external circuit connections. In the current output
mode, the DAC output (Pin 20) is tied to a summing junction,
and the current flowing from the DAC into this summing junc-
tion is sensed. In this mode, the DAC output scale is insensitive
to whether the load resistor, RLOAD, is shorted (Pin 19 con-
nected to Pin 20), or grounded (Pin 19 connected to Pin 18).
However, the connection of this resistor does affect the output
impedance of the DAC and may have a significant impact on
the noise gain and stability of the external circuitry. Grounding
RLOAD will reduce the output impedance, thereby increasing the
noise gain and also enhancing the stability of a circuit using a
non-unity-gain-stable op amp (see Figure 10).
In the voltage output mode, the DAC’s output current flows
through its own internal impedance (perhaps in parallel with an
external impedance) to generate a voltage. In this case, the DAC
OUTPUT VOLTAGE COMPLIANCE
The AD668 has an output compliance range of –2.0 V to
+1.2 V (with respect to the LCOM pin). The current steering
output stages will be unaffected by changes in the output termi-
nal voltage over this range. However, as shown in Figure 4,
there is an equivalent output impedance of 200 Ω in parallel
with 15 pF at the output terminal, producing an equivalent er-
ror current if the voltage deviates from the ladder common.
This is a linear effect which does not change with input code.
Operation beyond the maximum compliance limits may cause
either output stage saturation or breakdown, resulting in non-
linear performance. The positive compliance limit is not af-
fected by the positive power supply, but is a function of the
output current and the logic threshold voltage at VTH, Pin 13.
Figure 4.Equivalent Output Circuit
ANALOG INPUT CONSIDERATIONS
The reference input buffer can be viewed as a resistive divider
connected to one terminal of an op amp, as shown in Figure 5.
A unit DAC current source drives a resistor to produce a voltage
that is fed back to the opposite terminal of the op amp. Resistor
RFEEDBACK is laser-trimmed to ensure that a 1 V input to node A of
the op amp will produce a 10.24 mA DAC output. REFIN1 and
REFIN2 may be configured in any way the user chooses to pro-
vide a nominal input full scale of 1 V at node A. R1 and R2 are
sized and trimmed to provide both a 5:1 voltage divider and a
parallel impedance that matches the impedance at node B,
thereby reducing the amplifier offset voltage due to bias current.
The resistive divider is trimmed with an external 50 Ω resistor in
series with the 4k leg (R2). This provides a gain trim range of ±1%
using a 100 Ω trim potentiometer (Figure 7). If trimming is not
desired, a 50 Ω resistor may be used in place of the potentiom-
eter to produce the specified gain accuracy, or the resistor may
be omitted altogether to produce a nominal gain error of +1%.
The variations in DAC settling and rise times can be attributed
to differences in rise time and current driving capabilities of the
various families. Differences in the glitch impulse are predomi-
nantly dependent upon the variation in data skew. Variations in
these specs occur not only between logic families, but also be-
tween different gates and latches within the same family. When
selecting a gate to drive the AD668 logic input, pay particular
attention to the propagation delay time specs: tPLH and tPHL.
Selecting the smallest delays possible will help to minimize the
settling time, while selection of gates where tPLH and tPHL are
closely matched to one another will minimize the glitch impulse
resulting from data skew. Of the common latches, the 74374
octal flip-flop provides the best performance in this area for
many of the logic families mentioned above.
PIN BY PIN CURRENT ACCOUNTING
The internal wiring and pinout of the AD668 are dictated in
large part by current management constraints. When using low
impedance, high current, high accuracy parts such as the
AD668, great care must be taken in the routing of not only sig-
nal lines, but ground and supply lines as well. The following ac-
counting provides a detailed description of the magnitudes and
signal dependencies of the currents associated with each of the
part’s pins. These descriptions are consistent with the functional
block diagram as well as the equivalent circuits provided in Fig-
ures 4, 5, and 6.
VCC – the current into this pin is drawn predominantly through
the DAC current sources and generally runs about 2.2 times the
DAC’s nominal full scale. By design, this current is independent
of the digital input code but is linearly dependent on analog in-
put variations.
REFCOM – this node provides the reference ground for the
reference amplifier’s current feedback loop (as illustrated in Fig-
ure 5) as well as providing the negative supply voltage for most
of the reference amplifier. The current consists of 1.2 mA of
analog input dependent current and another 3 mA of input in-
dependent current. Analog input voltages should always be pro-
duced with respect to this voltage.
REFIN1 – has a 1k series resistance to the reference amplifier
input and a 5k series resistance to REFIN2. REFIN1 may be
used in conjunction with REFIN2 to provide a 5:1 voltage di-
vider, or the two may be driven in parallel to provide a high
impedance input node (see Figure 5).
REFIN2 – the 4k side of the input resistive divider. Note also
that the combined impedance of these two resistors matches the
effective impedance at the other input of the reference amplifier,
thereby minimizing the offset due to bias currents. Circuits
which alter this effective impedance may suffer increased analog
offset and drift performance degradation as a result of the mis-
match in these impedances.
IOUT – the output current. In the current output mode with this
node tied to a virtual ground, a 10.24 mA nominal full scale
output current will flow from this pin. In the voltage output
mode, with RL grounded, half of the output current will flow
out of RL and the other half will flow out of LCOM. External
DIGITAL INPUT CONSIDERATIONS
The AD668 uses a standard positive true straight binary code
for unipolar outputs (all 1s full-scale output), and an offset bi-
nary code for bipolar output ranges. In the bipolar mode, with
all 0s on the inputs, the output will go to negative full scale;
with 111 . . . 11, the output will go to positive full scale less
1 LSB; and with 100 . . . 00 (only the MSB on), the output will
go to zero.
The threshold of the digital inputs is set at 1.4 V and does not
vary with supply voltage. This reference is provided by a band-
gap generator, which requires approximately 3 mA of bias
current achieved by tying RTH to any +VLOGIC supply where:
TH=+VLOGIC±1.4VmA
(see Figure 6). The digital bit inputs operate with small input
currents to easily interface to unbuffered CMOS logic. The digi-
tal input signals to the DAC should be isolated from the analog
input and output as much as possible. To minimize undershoot,
ringing, and digital feedthrough noise, the interconnect distance
to the DAC inputs should be kept as short as possible. Termina-
tion resistors may improve performance if the digital lines be-
come too long. The digital inputs should be free from large
glitches and ringing and have 10% to 90% rise and fall times on
the order of 5 ns.
Figure 6.Equivalent Digital Input
To realize the AD668’s specified ac performance, it is recom-
mended that high speed logic families such as Schottky TTL,
high speed CMOS, or the new lines of high speed TTL be used
exclusively. Table I shows how DAC performance, particularly
glitch, can vary depending on the driving logic used. As this
table indicates, STTL, HCMOS, and FAST* represent the
most viable families for driving the AD668.
Table I. DAC Performance vs. Drive Logic
Logic
NOTESAll values typical, taken in test fixture diagrammed in Figure 23.
AD668
RL – a 200 Ω resistor with one end internally wired to the out-
put pin. If a 200 Ω ±20% DAC output impedance is desired, RL
should be shorted to IOUT. Grounding RL will provide a DAC
output impedance of 100 Ω ±1%. As noted above, in voltage
output configurations, a large portion of the DAC output cur-
rent will flow through this pin.
ACOM - as indicated in Figure 4, the current flowing out of
this pin is effectively the complement of IOUT, varying with both
analog and digital inputs. Using this current as a signal output is
not generally advised, since it is untrimmed and its positive out-
put compliance is limited to the logic low voltage.
LCOM - the current in this node has been carefully configured
to be independent of digital code when the output is into a vir-
tual ground, thereby minimizing any detrimental effects of lad-
der ground resistance on linearity. However, the current in this
node is proportional to the analog input voltage and the ground
drop here is responsible for the dc analog feedthrough. The
nominal value of this current is approximately equal to the DAC
full scale.
IBPO - the bipolar offset current flows into this node, with volt-
age compliance to VEE + 3V. This is a high impedance current
source, and should be grounded if the offset current is not used.
VEE - this voltage may be set anywhere from –10.8 V to
–16.5 V. The current in this node consists of 1.2 times the bipo-
lar offset current plus 500 μA of bias current for the reference
amplifier’s front end. The negative supply current is indepen-
dent of digital input but is linearly dependent on analog input.
THCOM - is the ground point for the bandgap diode that gen-
erates the threshold voltage. The current coming out of this
node is the same as that flowing into VTH plus a code dependent
number of base currents (see Figure 6). It is possible to intro-
duce an offset between THCOM and the system common,
thereby offsetting the effective logic threshold and positive out-
put compliance voltage.
VTH - as indicated earlier, if given sufficient positive bias cur-
rent, this voltage will be 1.4 V above THCOM. The necessary
bias current can readily be provided by a suitable resistor to any
positive supply. As Figure 6 suggests, this node is directly
coupled to the DAC output through several base to collector
capacitances and hence, should be carefully decoupled to the
analog ground.
DIGITAL INPUTS - when a bit is in the high state, the input
current is the leakage current of a reverse biased diode. When
the bit is driven low, it must sink a base current to ground, and
this base current will be proportional to the analog input. Note
that the input current for Bit 2 will be twice that for Bits 3-12,
and Bit 1’s current will be 4 times Bit 3’s, but all the currents
will be below the value specified.
APPLYING THE AD668
The following are some typical circuit configurations for the
AD668. As Table II indicates, these represent only a sample of
the possible implementations.
5 V REFIN, 1 V UNIPOLAR, UNBUFFERED VOLTAGE
DAC output resistance that generates a 1.024 V output when
the DAC current is at its full scale of 10.24 mA. The presence
of low impedance loads will effect the output voltage swing di-
rectly: an external load of 300 Ω will yield a total output resis-
tance of 75 Ω, and a full scale output of 0.768 V. An external
100 Ω will reduce the total output resistance to 50 Ω and the
full-scale voltage swing will drop to 0.512 V. Since the bipolar
offset current is not used in this configuration, Pin 16 is con-
nected to the analog ground plane.
The input divider has been connected to produce a 5 V full
scale reference input by shorting REFIN1 to the analog ground
plane and using REFIN2 as the reference input. With a 5 V
nominal full scale, the 10% to 120% reference input range falls
between 0.5 V and 6 V. The effective input resistance in this
mode is 5 kΩ (±20%). The ratio of the input divider has been
intentionally skewed by 50 Ω to provide an optional external
fine trim for gain adjust. A trim range of ±1% is provided by the
100 Ω trimming potentiometer shown in Figure 7. If trimming
is not desired, a 50 Ω resistor may be used in place of the poten-
tiometer to produce the specified gain accuracy, or, if a +1%
nominal gain error is tolerable, the resistor may be omitted
altogether.
Figure 7.5 V REFIN/1 V Unbuffered Unipolar Output
1.25 V REFIN, 1 V BIPOLAR, UNBUFFERED VOLTAGE
OUTPUT
Figure 8 demonstrates another unbuffered voltage output topol-
ogy, this time implementing a bipolar output and a 1.25 V refer-
ence input. The bipolar output is accomplished simply by tying
Pin 16 to the output (Pin 20). Note that in this mode, when the
digital inputs are all zeros and the analog input is at 1.25 V,
–512 mV will be produced at the DAC output. Bipolar zero
(0 VOUT) will be produced when the MSB is ON with all other
bits OFF (100 . . . 00), and the full-scale voltage minus 1 LSB
(511.75 mV) will be generated when all bits are ON.
The input range of 1.25 V is generated by grounding REFIN2
(through an optional gain trim potentiometer or gain adjust
50 Ω resistor) and using REFIN1 as the reference input. The
