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AD6652BBC
12-Bit, 65 MSPS IF to Base Band Diversity Receiver
12-Bit, 65 MSPS
IF to Baseband Diversity Receiver
Rev. 0
FEATURES
SNR = 90 dB in 150 kHz bandwidth (to Nyquist
@ 61.44 MSPS)
Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
Integrated dual-channel ADC:
Sample rates up to 65 MSPS
IF sampling frequencies to 200 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range (1 V to 2 V p-p)
Differential analog inputs
ADC clock duty cycle stabilizer
85 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC):
Crossbar switched DDC inputs
Digital resampling for noninteger decimation
Programmable decimating FIR filters
Flexible control for multicarrier and phased array
Dual AGC stages for output level control
Dual 16-bit parallel or 8-bit link output ports
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,
IS95, IS136, CDMA2000, IMT-2000
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Instrumentation and test equipment
FUNCTIONAL BLOCK DIAGRAM //
LIA
LIA
LIB
LIB
OTRA
SYNCASYNCBSYNCCSYNCD
ACLK
VINA+
VINA–
VINB+
VINB–
VREF
SENSE
REFTA
REFBA
REFTB
REFBB
PDWN
SHRDREFDUTYEN
RCF OUTPUTSCHANNELS 0, 1, 2, 3
RCF OUTPUTSCHANNELS 0, 1, 2, 3
TO OUTPUT PORTS
TO OUTPUT PORTS
TO OUTPUT PORTS
TO OUTPUT
PORTS
DUAL-CHANNEL 12-BIT A/D FRONT ENDWIDEBAND DIGITAL DOWNCONVERTER (DDC)
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
+3.0AVDD+3.3VDDIO2.5VDDAGNDDGNDCLKDATACONTADD
*DATA INTERLEAVING AND INTERPOLATING HB FILTER3Figure 1.
TABLE OF CONTENTS Product Description.........................................................................4
Product Highlights.......................................................................4
Specifications.....................................................................................5
Recommended Operating Conditions......................................5
ADC DC Specifications...............................................................5
ADC Switching Specifications....................................................5
ADC AC Specifications...............................................................6
Electrical Characteristics.............................................................7
General Timing Characteristics.................................................8
Microprocessor Port Timing Characteristics...........................9
Absolute Maximum Ratings..........................................................10
Thermal Characteristics............................................................10
Test Level.....................................................................................10
ESD Caution................................................................................10
Pin Configuration and Function Descriptions...........................11
Typical Performance Characteristics...........................................14
DDC Timing Diagrams.................................................................17
Terminology....................................................................................23
ADC Equivalent Circuits...........................................................23
Theory of Operation......................................................................24
ADC Architecture......................................................................24
Digital Downconverter Architecture Overview.........................29
Data Input Matrix.......................................................................29
Numerically Controlled Oscillator...........................................29
Second-Order rCIC Filter.........................................................29
Fifth-Order CIC Filter...............................................................29
RAM Coefficient Filter..............................................................29
Interpolating Half-Band Filters and AGC...............................29
Control Register and Memory Map Address Notation.............31
DDC Input Matrix......................................................................31
Gain Switching............................................................................31
Numerically Controlled Oscillator...............................................33
Frequency Translation to Baseband.........................................33
NCO Shadow Register...............................................................33
NCO Frequency Hold-Off Register.........................................33
Phase Offset.................................................................................33
NCO Control Register...............................................................33
Second-Order rCIC Filter.............................................................35
rCIC2 Scale Factor.....................................................................35
rCIC2 Output Level...................................................................36
rCIC2 Rejection..........................................................................36
Decimation and Interpolation Registers.................................36
rCIC2 Scale Register..................................................................36
Fifth-Order CIC Filter...................................................................37
CIC5 Rejection...........................................................................37
RAM Coefficient Filter..................................................................38
RCF Decimation Register..........................................................38
RCF Decimation Phase..............................................................38
RCF Filter Length.......................................................................38
RCF Output Scale Factor and Control Register.....................39
Interpolating Half-Band Filters....................................................40
Automatic Gain Control................................................................41
AGC Loop...................................................................................41
Desired Signal Level Mode........................................................41
Synchronization..........................................................................44
User-Configurable Built-In Self-Test (BIST)..............................45
RAM BIST...................................................................................45
Channel BIST..............................................................................45
Channel/Chip Synchronization....................................................46
Start..............................................................................................46
Parallel Output Ports.......................................................................50
Channel Mode.............................................................................50
AGC Mode...................................................................................51
Master/Slave PCLK Modes........................................................52
Parallel Port Pin Functions........................................................52
Link Port...........................................................................................53
Link Port Data Format...............................................................53
Link Port Timing.........................................................................53
TigerSHARC Configuration......................................................54
External Memory Map...................................................................55
Access Control Register (ACR).................................................56
Channel Address Register (CAR).............................................56
Soft_Sync Control Register........................................................56
Pin_Sync Control Register.........................................................57
Sleep Control Register................................................................57
Data Address Registers...............................................................57
Channel Address Registers (CAR)............................................57
Input Port Control Registers.....................................................63
Output Port Control Registers..................................................64
Microport Control......................................................................71
Applications.....................................................................................73
AD6652 Receiver Applications..................................................73
Design Guidelines.......................................................................73
AD6652 Evaluation Board and Software.....................................75
Outline Dimensions........................................................................76
Ordering Guide...........................................................................76
REVISION HISTORY
7/04—Revision 0: Initial Version
PRODUCT DESCRIPTION The AD6652 is a mixed-signal IF to baseband receiver
consisting of dual 12-bit 65 MSPS ADCs and a wideband
multimode digital downconverter (DDC). The AD6652 is
designed to support communications applications where low
cost, small size, and versatility are desired. The AD6652 is also
suitable for other applications in imaging, medical ultrasound,
instrumentation, and test equipment.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Both
ADCs feature wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compen-
sate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
ADC data outputs are internally connected directly to the
receiver’s digital downconverter (DDC) input matrix, simplify-
ing layout and reducing interconnection parasitics. Overrange
bits are provided for each ADC channel to alert the user to
ADC clipping. Level indicator bits are also provided for each
DDC input port that can be used for external digital VGA
control.
The digital receiver has four reconfigurable channels and
provides extraordinary processing flexibility. The receiver input
matrix routes the ADC data to individual channels, or to all four
receive processing channels. Each receive channel has five
cascaded signal processing stages: a 32-bit frequency translator
(numerically controlled oscillator (NCO)), two fixed-coefficient
decimating filters (CIC), a programmable RAM coefficient
decimating FIR filter (RCF), and an interpolating half-band
filter/AGC stage. Following the CIC filters, one, several, or all
channels can be configured to use one, several, or all the RCF
filters. This permits the processing power of four 160-tap RCF
FIR filters to be combined or used individually.
After FIR filtering, data can be routed directly to the two
external 16-bit output ports. Alternatively, data can be routed
through two additional half-band interpolation stages, where up
to four channels can be combined (interleaved), interpolated,
and processed by an automatic gain control (AGC) circuit with
96 dB range. The outputs from the two AGC stages are also
routed directly to the two external 16-bit output ports. Each
output port has a 16-bit parallel output and an 8-bit link port to
permit seamless data interface with DSP devices such as the
TS-101 TigerSHARC® DSP. A multiplexer for each port selects
one of six data sources to appear on the device outputs pins.
The AD6652 is part of the Analog Devices SoftCell® multimode
and multicarrier transceiver chipset. The SoftCell receiver
digitizes a wide spectrum of IF frequencies and then down-
converts the desired signals to baseband using individual
channel NCOs. The AD6652 provides user-configurable digital
filters for removal of undesired baseband components, and the
data is then passed on to an external DSP, where demodulation
and other signal processing tasks are performed to complete the
information retrieval process. Each receive channel is independ-
ently configurable to provide simultaneous reception of the
carrier to which it is tuned. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications. The decimating
filters remove unwanted signals and noise from the channel of
interest. When the channel occupies less bandwidth than the
input signal, this rejection of out-of-band noise is referred to as
processing gain. By using large decimation factors, this process-
ing gain can improve the SNR of the ADC by 20 dB or more. In
addition, the programmable RAM coefficient filter allows
antialiasing, matched filtering, and static equalization functions
to be combined in a single, cost-effective filter.
Flexible power-down options allow significant power savings,
when desired.
PRODUCT HIGHLIGHTS Integrated dual 12-bit 65 MSPS ADC. Integrated wideband digital downconverter (DDC). Proprietary, differential SHA input maintains excellent
SNR performance for input frequencies up to 200 MHz. Crossbar-switched digital downconverter input ports. Digital resampling permits noninteger relationships
between the ADC clock and the digital output data rate. Energy-saving power-down modes. 32-bit NCOs with selectable amplitude and phase dithering
for better than −100 dBc spurious performance. CIC filters with user-programmable decimation and
interpolation factors. 160-tap RAM coefficient filter for each DDC channel. Dual 16-bit parallel output ports and dual 8-bit link ports. 8-bit microport for register programming, register read-
back, and coefficient memory programming.
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Table 1.
ADC DC SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 2.
ADC SWITCHING SPECIFICATIONS AVDD = 3.0 V, VDD = 2.5 V, VDDIO = 3.3 V, 61.44 MSPS, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted.
Table 3. Duty cycle stabilizer enabled.
2 Wake-up time is dependent on the value of decoupling capacitors, typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
