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AD6650BBC
Diversity IF to Baseband GSM/EDGE Narrowband Receiver
PrJ 02/27/03
Diversity IF to Baseband
GSM/EDGE Narrowband Receiver
FEATURES
Digital VGA I & Q Demodulators
Active Low Pass Filters Dual Wideband ADC
Programmable Decimation and Channel Filters Phase Locked Loop Circuitry
Serial Data Output Ports IF Frequencies 70-300MHz
10 dB Noise Figure +24 dBm Input IP2
-13 dBm Input IP3 3.3 Volt I/O and CMOS Core 2C and Microprocessor Interface JTAG Boundary Scan
APPLICATIONS
GSM/EDGE Single Carrier and Diversity Receivers
Micro and Pico Cell Systems Wireless Local Loop
Smart Antenna Systems Software Radios
In Building Wireless Telephony
PRODUCT DESCRIPTION The AD6650 is a diversity, IF to baseband receiver for GSM/EDGE. This narrow band receiver consists of an
integrated DVGA, IF-to-baseband I&Q demodulators, low-pass filtering, and a dual wideband ADC. The chip can
accommodate IF input frequencies from 70 MHz to 300 MHz. This receiver architecture is designed such that only one
external SAW filter(one for main and one for diversity) is required in the entire Rx signal path to meet GSM/EDGE
blocking requirements.
Digital decimation and filtering circuitry is embedded on chip
to generate serial output I&Q data streams. The decimating
filters remove unwanted signals and noise outside the channel of interest. In addition, programmable RAM Coefficient
filters allow anti-aliasing, matched filtering, and static equalization functions to be combined in a single, cost-
effective filter. The AD6650 is part of a complete GSM/EDGE receive and transmit chipset. Other components in this chipset are: RF to
IF amplifier/mixers, receive and transmit frequency hopping synthesizers, and a baseband to IF transmit modulator and
ramping chip.
Figure 1. AD6650 Functional Block Diagram
Preliminary Technical Data AD6650
TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .xx
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . .. .xx SPECIFICATIONS/CHARACTERISTICS . . . . . .. . . . . . xx
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .xx
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . xx ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xx
EXAMPLE FILTER RESPONSE . . . . . . . . . . . . . . . . . . .xx AGC LOOP.......................................................................xx
DC CORRECTION...........................................................xx FOURTH ORDER CASCADED INTEGRATOR COMB
FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx CIC4 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
INFINITE IMPULSE RESPONSE xx RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . .xx
RCF Decimation Register . . . . . . .. . . . . .. . . . . xx RCF Decimation Phase . . . . .. . . . . . . . . . . . . . xx
RCF Filter Length . . . . . .. . . . . . . . . . . . . . . . . .xx RCF Output Scale Factor and Control Register . xx
USER-CONFIGURABLE BUILT-IN SELF-TEST CHANNEL BIST...........................................xx
CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . .xx Start . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . xx
SERIAL OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . .xx Serial Output Data Format . . . . . . . . . . . . . . . . . xx
Serial Data Frame (Serial Bus Master) .. . . . . . . . xx Serial Data Frame (Serial Cascade) . . . . . . . . . xx
Configuring the Serial Ports . . . . . . . .. . . . . . . xx Serial Port Data Rate . . . . . . . . . .. . . . . . . . . . . . xx
Serial Slave Operation . . . . . . . . . .. . . . . . . . . . . xx Serial Ports Cascaded . . . . . . . .. . . . . . . . . . . . . . xx
Serial Output Frame Timing (Master and Slave) xx Serial Port Timing Specifications . . . . . . ... . . . . xx
SCLK . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . xx SDO0 . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . xx
SDO1 . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . xx SDFS . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . xx
Serial Word Length . . . . . .. . . . . . . . . . . . . . . . . xx SDFS Mode . . . . . . . . . . . . .. . . . . . . . . . . . . . . . xx
Mapping RCF Data to the BIST Registers . . . .. . xx 0x00: Clock Divider Control . .. . .xx
0x01-0x05: PLL Register[4:0] . . . . . . .. . . . . .. . xx 0x06: Clamp Control............................................xx
0x07: Aux DAC A ...............................................xx 0x08: Aux DAC B ................................................xx
0x09: Aux DAC Control.......................................xx 0x0A: ADC Dither Control.................................xx
0x0B: DC Correction BW.....................................xx 0x0C: DC Correction Control...............................xx
0x0D-0x14: AGC Control[7:0]............................xx 0x15: Start Hold-Off Counter...............................xx
0x16: CIC4 Decimation.......................................xx 0x17: CIC4 Scale.................................................xx
0x18: IIR Control Register...................................xx 0x19: RCF Decimation Register..........................xx
0x1A: RCF Decimation Phase..............................xx 0x1B: RCF Coefficient Offset..............................xx
0x1C: RCF Taps....................................................xx 0x1D: RCF Scale Register...................................xx
0x1E-0x1F: BIST For A-I/Q.................................xx 0x20-0x21: BIST for B-I/Q..................................xx
0x22: Serial Control Register...............................xx 0x23-0x29: Reserved............................................xx
0x30-0x5F: Coefficient Memory.........................xx 0x60-0xFF: Reserved...........................................xx
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . xx External Memory Map . . . . . .. . . . . . . . . . . . . . . xx
Access Control Register (ACR) . . . . .. . . . . . . . . xx External Memory Map . . . . . . ... . . . . . . . . . . . . xx
Channel Address Register (CAR) . .. . . . . . . . . . xx SOFT_SYNC Control Register . .. . . . . . . . . . xx
PIN_SYNC Control Register . . . ... . . . . . . . . . xx SLEEP Control Register . . . . . . .. . . . . . . . . . . . xx
Data Address Registers . . . . . . .. . . . . . . . . . . . . xx Write Sequencing . . . . . . . .. . . . . . . . . . . . . . . . . xx
Read Sequencing . . . . . . . .. . . . . . . . . . . . . . . . . xx Read/Write Chaining . . . . .. . . . . . . . . . . . . . . . . xx
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . xx Motorola Nonmultiplexed Mode (MNM) ... . . . . xx 2C PORT CONTROL JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . .xx
INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . .. . . . .xx Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xx
INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . xx Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . xx
OUTLINE DIMENSIONS . . . . . . . . . . . . . .. . . . . xx
Preliminary Technical Data AD6650
AC Specifications
Preliminary Technical Data AD66501This Measurement applies in Maximum Gain (+36 dB)
Preliminary Technical Data AD6650 DIGITAL SPECIFICATIONS
(TMIN to TMAX, AVDD, CLKVDD, DVDD = +3.3v, unless otherwise noted)
AD6650BBC
Typ 3.3 3.3 3.3 +25
ELECTRICAL CHARACTERISTICS AD6650BBC Typ 3.3V CMOS V V µA µA 5 pF 3.3VCMOS/TTL VDD-0.2 0.2 1.2
Preliminary Technical Data AD6650
GENERAL TIMING CHARACTERISTICS AD6650 Typ ns 0.5 x tCLK ns 0.5 x tCLK ns
/RESET Timing Requirements: tRESL
SYNC Timing Requirements:
tSS
tHS
Master Mode Serial Port Timing Requirements (SBM=1): Switching Characteristics
tDSCLK1
tDSCLKH
tDSCLKL
tDSCLKLL
tDSDFS 3.02
tDSDO 2.7
tDSD1 2.6
tDSDR 2.7
Slave Mode Serial Port Timing Requirements (SBM=0):
Switching Characteristics
tSCLK
tSCLKL tSCLKH
tDSDO 6.8
tDSD1 6.8
t DSDR 6.9 tSSF 2.6
tHSF -1.15 All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V. 2The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1). The Slave serial port’s (SCLK) operating frequency is limited to 52 MHz. 3Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS 4(CLOAD=40pF on all outputs unless otherwise specified)
Preliminary Technical Data AD6650
MICROPROCESSOR PORT TIMING CHARACTERISTICS1 AD6650 Typ
MODE INM Read Timing:
tSC tHC
tSAM
tHAM tZD
tDD tDRDY
tACC AD6650
Typ
MODE MNM Read Timing: tSC
tHC tHDS
tSAM
tHAM tZD
tDD tDDTACK
tACC
MODE I2C Timing: tDSCL 61
tDSDA 57
tSSCL5 5 1All Timing Specifications valid over VDD range of 3.0V to 3.6V and VDDIO range of 3.0V to 3.6V. 2The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both channels (0, 1) 3Specification pertains to control signals: RW, (/WR), /DS, (/RD), /CS 4(CLOAD=40pF on all outputs unless otherwise specified) There is no hold time for SDA because as this waits for a negative transition (↓) on SCL to transition.
Preliminary Technical Data AD6650 TIMING DIAGRAMS
RESET Figure x. Reset Timing Requirements
SCLK
CLKFigure x. SCLK Switching Characteristics (Divide by 1)
SCLK
CLKFigure x. SCLK Switching Characteristics (Divide by 2 or EVEN integer)
SCLK
CLKFigure x. SCLK Switching Characteristics (Divide by 3 or ODD integer)
Preliminary Technical Data AD6650
TIMING DIAGRAMS
SDI
SDFS
SCLKFigure x. Serial Port Switching Characteristics
CLKFigure x. CLK, DR Switching Characteristics
SCLKFigure x. SCLK, DR Switching Characteristics
SCLK
SDFS Figure x. SDFS Timing Requirements (SBM=0)
Preliminary Technical Data AD6650
TIMING DIAGRAMS
SYNC
CLK
Figure x. SYNC Timing Inputs
TIMING DIAGRAMS – INM Microport Mode
/RD (/DS)
/WR (RW)
/CS
A[2:0]
D[7:0]
RDY
(/DTACK)
Notes:
1. tACC Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY.
tACC requires a maximum of 9 CLK periods
CLK Figure 16. INM Microport Write Timing Requirements.
/RD (/DS)
/WR (RW)
/CS
A[2:0]
D[7:0]
RDY
(/DTACK)
Notes:
1. tACC Access time depends on the Address accessed. Access time is measured from FE of /WR to RE of RDY.
tACC requires a maximum of 13 CLK periods and applies to A[2:0]=7,6,5,3,2,1
CLK
Preliminary Technical Data AD6650 TIMING DIAGRAMS – MNM Microport Mode
/DS (/RD)
RW (/WR)
/CS
A[2:0]
D[7:0]
/DTACK
(RDY)
Notes:
1. tACC Access time depends on the Address accessed. Access time is measured from the FE of /DS to the FE of /DTACK.
tACC requires a maximum of 9 CLK periods
CLK Figure x. MNM Microport Write Timing Requirements.
/DS (/RD)
RW (/WR)
/CS
A[2:0]
D[7:0]
/DTACK
(RDY)
Notes:
1. tACC Access time depends on the Address accessed. Access time is measured from the FE of /DS to the FE of /DTACK.
tACC requires a maximum of 13 CLK periods
CLK Figure x. MNM Microport Read Timing Requirements.
Preliminary Technical Data AD6650 ABSOLUTE MAXIMUM RATINGS1
Supply Voltage…………….…………….....-0.3V to 3.3v
Input Voltage………..……….........................-0.3 to 3.6V Output Voltage Swing…………..-0.3V to VDDIO +0.3V
Load Capacitance…………………..…………….200pF
Junction Temperature Under Bias…..….……….+125°C
Storage Temperature Range……….......-65°C to +150°C
Lead Temperature (5 sec)…………..……….…..+280°C Notes Stresses greater than those listed above may cause permanent damage to the device These are stress ratings only; functional operation of the devices at these or any
other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Thermal Characteristics
121-Pin Ball Grid Array:
θJA=28.1°C /Watt, no airflow
θJA=XX°C/Watt, 200-lfpm airflow
Thermal measurements made in the horizontal position on a 4-layer board. EXPLANATION OF TEST LEVELS 100% Production Tested.
II 100% Production Tested at 25°C, and Sampled Tested at Specified Temperatures. III Sample Tested Only
IV Parameter Guaranteed by Design and Analysis V Parameter is Typical Value Only
VI 100% Production Tested at 25°C, and Sampled Tested at Temperature Extremes
ORDERING GUIDE
Notes 1X-Grade Material is Pre-Production material, normally shipped during product characterization and qualification.
ESD SENSITIVITY
The AD6650 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6650 features proprietary ESD
protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Preliminary Technical Data AD6650
Pin Configuration
Pin Function Descriptions
Preliminary Technical Data AD6650
