AD664BD-UNI ,Monolithic 12-Bit Quad DACSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
AD664BD-UNI ,Monolithic 12-Bit Quad DACSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
AD664BE ,Monolithic 12-Bit Quad DACSPECIFICATIONSModel JN/JP/AD/AJ/SD KN/KP/BD/BJ/BE/TD/TEMin Typ Max Min Typ Max UnitsRESOLUTION 12 1 ..
AD664BJ ,Monolithic 12-Bit Quad DACSpecifications subject to change without notice.
AD664JN-UNI ,Monolithic 12-Bit Quad DACSpecifications same as JN/JP/AD/AJ/SD.
AD664JP ,Monolithic 12-Bit Quad DACAPPLICATIONSAutomatic Test EquipmentRoboticsProcess ControlDisk DrivesInstrumentationAvionicsPRODUC ..
ADC0820CCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionGeneral Description
The ADC0820 is a high speed, microprocessor com-
patible, 8 bit analog-to-d ..
ADC0820CCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold Function19-0889,' Fiev 1; 7/96
ADC0820CCM+ ,CMOS High-Speed 8-Bit A/D Converter with Track/Hold FunctionFeatures
The AD0082O is a high speed, microprocessor corn»
. Fast Conversion Time: 1.Os Max.
p ..
ADC0820CCMSA ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed μP Compatible A/D Converter with Track/Hold FunctionJune 1999ADC08208-Bit ..
ADC0820CCMSAX ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed μP Compatible A/D Converter with Track/Hold FunctionJune 1999ADC08208-Bit ..
ADC0820CCN ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
AD664AD-BIP-AD664BD-BIP-AD664BD-UNI-AD664BE-AD664BJ-AD664JN-UNI-AD664JP-AD664KN-BIP-AD664KP
Monolithic 12-Bit Quad DAC
PIN CONFIGURATIONS
44-Pin Package
28-Pin DIP PackageREV. C
Monolithic
12-Bit Quad DAC
FEATURES
Four Complete Voltage Output DACs
Data Register Readback Feature
“Reset to Zero” Override
Multiplying Operation
Double-Buffered Latches
Surface Mount and DIP Packages
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Automatic Test Equipment
Robotics
Process Control
Disk Drives
Instrumentation
Avionics
PRODUCT DESCRIPTIONThe AD664 is four complete 12-bit, voltage-output DACs on
one monolithic IC chip. Each DAC has a double-buffered input
latch structure and a data readback function. All DAC read and
write operations occur through a single microprocessor-compatible
I/O port.
The I/O port accommodates 4-, 8- or 12-bit parallel words al-
lowing simple interfacing with a wide variety of microprocessors.
A reset to zero control pin is provided to allow a user to simulta-
neously reset all DAC outputs to zero, regardless of the contents
of the input latch. Any one or all of the DACs may be placed in
a transparent mode allowing immediate response by the outputs
to the input data.
The analog portion of the AD664 consists of four DAC cells,
four output amplifiers, a control amplifier and switches. Each
DAC cell is an inverting R-2R type. The output current from
each DAC is switched to the on-board application resistors and
output amplifier. The output range of each DAC cell is pro-
grammed through the digital I/O port and may be set to unipo-
lar or bipolar range, with a gain of one or two times the reference
voltage. All DACs are operated from a single external reference.
The functional completeness of the AD664 results from the
combination of Analog Devices’ BiMOS II process, laser-trimmed
thin-film resistors and double-level metal interconnects.
PRODUCT HIGHLIGHTSThe AD664 provides four voltage-output DACs on one chip
offering the highest density 12-bit D/A function available.The output range of each DAC is fully and independently
programmable.Readback capability allows verification of contents of the in-
ternal data registers.The asynchronous RESET control returns all D/A outputs
to zero volts.DAC-to-DAC matching performance is specified and tested.Linearity error is specified to be 1/2 LSB at room tempera-
ture and 3/4 LSB maximum for the K, B and T grades.DAC performance is guaranteed to be monotonic over the
full operating temperature range.Readback buffers have tristate outputs.Multiplying-mode operation allows use with fixed or vari-
able, positive or negative external references.
10.The AD664 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD664/883B data sheet for detailed
specifications.
AD664–SPECIFICATIONS
(VLL = +5 V, VCC = +15 V, VEE = –15 V, VREF = +10 V, TA = +258C
unless otherwise noted)
AD664DIGITAL INPUTS
NOTESA minimum power supply of ±12.0 V is required for 0 V to +10 V and ±10 V operation. A minimum power supply of ±11.4V is required for –5 V to +5 V operation.For VCC < +12 V and VEE > –12 V. Voltage not to exeeed 10 V maximum.Bipolar zero error is the difference from the ideal output (0 volts) and the actual output voltage with code 100 000 000 000 applied to the inputs.Linearity error is defined as the maximum deviation of the actual DAC output from the ideal output (a straight line drawn from 0 to F.S. – 1 LSB).FSR means Full-Scale Range and is 20 V for ±10 V range and 10 V for ±5 V range.A minimum power supply of ±12.0 V is required for a 10 V reference voltage.Analog Ground Current is input code dependent.Gain error matching is the largest difference in gain error between any two DACs in one package.Offset error matching is the largest difference in offset error between any two DACs in one package.Bipolar zero error matching is the largest difference in bipolar zero error between any two DACs in one package.Linearity error matching is the difference in the worst ease linearity error between any two DACs in one package.44-pin versions only.
*Specifications same as JN/JP/AD/AJ/SD.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
ABSOLUTE MAXIMUM RATINGS*VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V to 0 V
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C, 10 sec
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –1 V to +1 V
Reference Input . . . . . . . . . . . . . . . . . . VREF ≤ ±10 V and VREF
≤ (VCC – 2 V, VEE + 2 V)
VCC to VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +36 V
CAUTIONESD (electrostatic discharge) sensitive device. Unused devices must be stored in conductive foam
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Outputs . . . . . . . . . . . . . . . . . . . . . Indefinite Shorts to
VCC, VLL, VEE and GND
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device.This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied.Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
AD664Figure 1a.44-Pin Block Diagram
FUNCTIONAL DESCRIPTIONThe AD664 combines four complete 12-bit voltage output D/A
converters with a fast, flexible digital input/output port on one
monolithic chip. It is available in two forms, a 44-pin version
shown in Figure 1a and a 28-pin version shown in Figure 1b.
44-Pin VersionsEach DAC offers flexibility, accuracy and good dynamic perfor-
mance. The R-2R structure is fabricated from thin-film resistors
which are laser-trimmed to achieve 1/2 LSB linearity and guar-
anteed monotonicity. The output amplifier combines the best
features of the bipolar and MOS devices to achieve good dy-
namic performance and low offset. Settling time is under 10 μs
and each output can drive a 5 mA, 500 pF load. Short-circuit
protection allows indefinite shorts to VLL, VCC, VEE and GND.
The output and span resistor pins are available separately. This
feature allows a user to insert current-boosting elements to in-
crease the drive capability of the system, as well as to overcome
parasitics.
Digital circuitry is implemented in CMOS logic. The fast, low
power, digital interface allows the AD664 to be interfaced with
most microprocessors. Through this interface, the wide variety
of features on each chip may be accessed. For example, the in-
put data for each DAC is programmed by way of 4-, 8-, 12- or
16-bit words. The double-buffered input structure of this latch
allows all four DACs to be updated simultaneously. A readback
feature allows the internal registers to be read back through the
same digital port, as either 4-, 8- or 12-bit words. When dis-
abled, the readback drivers are placed in a high impedance
(tristate) mode. A TRANSPARENT mode allows the input data
to pass straight through both ranks of input registers and appear
at the DAC with a minimum of delay. One D/A may be placed
in the transparent mode at a time, or all four may be made
transparent at once. The MODE SELECT feature allows the
output range and mode of the DACs to be selected via the data
tions. This register may also be read back to check its contents.
A RESET-TO-ZERO feature allows all DACs to be reset to 0
volts out by strobing a single pin.
Figure 1b.28-Pin Block Diagram
28-Pin VersionsThe 28-pin versions are dedicated versions of the 44-pin
AD664. Each offers a reduced set of features from those offered
in the 44-pin version. This accommodates the reduced number
of package pins available. Data is written and read with 12-bit
words only. Output range and mode select functions are also
not available in 28-pin versions. As an alternative, users specify
either the UNI (unipolar, 0 to VREF) models or the BIP (bipolar,
–VREF to VREF) models depending on the application require-
ments. Finally, the transparent mode is not available on the
Table I.Transfer FunctionsGain = 1
DEFINITIONS OF SPECIFICATIONSLINEARITY ERROR:Analog Devices defines linearity error as
the maximum deviation of the actual, adjusted DAC output
from the ideal analog output (a straight line drawn from 0 to FS
– 1 LSB) for any bit combination. This is also referred to as
relative accuracy. The AD664 is laser-trimmed to typically
maintain linearity errors at less than ±1/4 LSB.
MONOTONICITY:A DAC is said to be monotonic if the out-
put either increases or remains constant for increasing digital
inputs such that the output will always be a nondecreasing func-
tion of input. All versions of the AD664 are monotonic over
their full operating temperature range.
DIFFERENTIAL LINEARITY:Monotonic behavior requires
that the differential linearity error be less than 1 LSB both at
25°C as well as over the temperature range of interest. Differen-
tial nonlinearity is the measure of the variation in analog value,
normalized to full scale, associated with a 1 LSB change in digi-
tal input code. For example, for a 10 V full-scale output, a
change of 1 LSB in digital input code should result in a
2.44 mV change in the analog output (VREF = 10 V, Gain = 1,
1 LSB = 10 V × 1/4096 = 2.44 mV). If in actual use, however, a
1 LSB change in the input code results in a change of only
0.61 mV (1/4 LSB) in analog output, the differential non-
linearity error would be –1.83 mV, or –3/4 LSB.
GAIN ERROR:DAC gain error is a measure of the difference
between the output span of an ideal DAC and an actual device.
UNIPOLAR OFFSET ERROR:Unipolar offset error is the dif-
ference between the ideal output (0 V) and the actual output of
a DAC when the input is loaded with all “0s” and the MODE is
unipolar.
BIPOLAR ZERO ERROR:Bipolar zero error is the difference
between the ideal output (0 V) and the actual output of a DAC
when the input code is loaded with the MSB = “1” and the rest
of the bits = “0” and the MODE is bipolar.
SETTLING TIME:Settling time is the time required for the
output to reach and remain within a specified error band about
its final value, measured from the digital input transition.
CROSSTALK:Crosstalk is the change in an output caused by
a change in one or more of the other outputs. It is due to
capacitive and thermal coupling between outputs.
REFERENCE FEEDTHROUGH:The portion of an ac refer-
ence signal that appears at an output when all input bits are low.
Feedthrough is due to capacitive coupling between the reference
input and the output. It is specified in decibels at a particular
frequency.
REFERENCE 3 dB BANDWIDTH:The frequency of the ac
reference input signal at which the amplitude of the full-scale
output response falls 3 dB from the ideal response.
GLITCH IMPULSE:Glitch impulse is an undesired output
voltage transient caused by asymmetrical switching times in the
switches of a DAC. These transients are specified by their net
area (in nV-sec) of the voltage vs. time characteristic.
PIN CONFIGURATIONS
28-Pin DIP Package44-Pin Package
AD664
ANALOG CIRCUIT CONSIDERATIONS
Grounding RecommendationsThe AD664 has two pins, designated ANALOG and DIGITAL
ground. The analog ground pin is the “high quality” ground ref-
erence point for the device. A unique internal design has
resulted in low analog ground current. This greatly simplifies
management of ground current and the associated induced volt-
age drops. The analog ground pin should be connected to the
analog ground point in the system. The external reference and
any external loads should also be returned to analog ground.
The digital ground pin should be connected to the digital
ground point in the circuit. This pin returns current from the
logic portions of the AD664 circuitry to ground.
Analog and digital grounds should be connected at one point in
the system. If there is a possibility that this connection be bro-
ken or otherwise disconnected, then two diodes should be con-
nected between the analog and digital ground pins of the
AD664 to limit the maximum ground voltage difference.
Power Supplies and DecouplingThe AD664 requires three power supplies for proper operation.
VLL powers the logic portions of the device and requires
+5 volts. VCC and VEE power the remaining portions of the cir-
cuitry and require +12 V to +15 V and –12 V to –15 V, respec-
tively. VCC and VEE must also be a minimum of two volts greater
then the maximum reference and output voltages anticipated.
Decoupling capacitors should be used on all power supply pins.
Good engineering practice dictates that the bypass capacitors be
located as near as possible to the package pins. VLL should be
bypassed to digital ground. VCC and VEE should be decoupled to
analog ground.
Driving the Reference InputThe reference input of the AD664 can have an impedance as
low as 1.3 kΩ. Therefore, the external reference voltage must be
able to source up to 7.7 mA of load current. Suitable choices
include the 5 V AD586, the 10 V AD587 and the 8.192 V
AD689.
The architecture of the AD664 derives an inverted version of
the reference voltage for some portions of the internal circuitry.
This means that the power supplies must be at least 2 V
greater than both the external reference and the inverted exter-
nal reference.
Output ConsiderationsEach DAC output can source or sink 5 mA of current to an
external load. Short-circuit protection limits load current to a
maximum load current of 40 mA. Load capacitance of up to
500 pF can be accommodated with no effect on stability.
Should an application require additional output current, a cur-
rent boosting element can be inserted into the output loop with
no sacrifice in accuracy. Figure 3 details this method.
Figure 3.Current-Boosting Scheme
AD664 output voltage settling time is 10μs maximum. Figure 4
shows the output voltage settling time with a fixed 10 V refer-
ence, gain = 1 and all bits switched from 1 to 0.
Figure 4.Settling Time; All Bits Switched from On to Off
Alternately, Figure 5 shows the settling characteristics when the
reference is switched and the input bits remain fixed. In this
case, all bits are “on,” the gain is 1 and the reference is switched
from –5 V to +5 V.
Multiplying Mode PerformanceFigure 6 illustrates the typical open-loop gain and phase perfor-
mance of the output amplifiers of the AD664.
GAIN – dB
+20
+15
+10
10k100k1M
+45
+90
PHASE MARGIN – Degrees
FREQUENCY – HzFigure 6.Gain and Phase Performance of AD664 Outputs
CrosstalkCrosstalk is a spurious signal on one DAC output caused by a
change in the output of one or more of the other DACs.
Crosstalk can be induced by capacitive, thermal or load current
induced feedthrough. Figure 7 shows typical crosstalk. DAC B
is set to output 0 volts. The outputs of DAC A, C and D switch
2 kΩ loads from 10 V to 0 V. The first disturbance in the output
of DAC B is caused by digital feedthrough from the input data
lows. The second disturbance is caused by analog feedthrough
from the other DAC outputs.
Figure 7.Output Crosstalk
Output NoiseWideband output noise is shown in Figure 8. This measurement
was made with a 7 MHz noise bandwidth, gain = 1 and all bits
on. The total rms noise is approximately one fifth the visual
peak-to-peak noise.
DIGITAL INTERFACEAs Table II shows, the AD664 makes a wide variety of operating
modes available to the user. These modes are accessed or pro-
grammed through the high speed digital port of the quad DAC.
the DAC operating mode data. All registers are double-buffered
to allow for simultaneous updating of all outputs. Register data
may be read back to verify the respective contents. The digital
port also allows transparent operation. Data from the input pins
can be sent directly through both ranks of latches to the DAC.
Figure 8. Typical Output Noise
Partial address decoding is performed by the DS0, DS1, QS0,
QS1 and QS2 address bits. QS0, QS1 and QS2 allow the 44-pin
versions of the AD664 to be addressed in 4-bit nibble, 8-bit byte
or 12-bit parallel words.
The RST pin provides a simple method to reset all output
voltages to zero. Its advantages are speed and low software
overhead.
INPUT DATAIn general, two types of data will be input to the registers of the
AD664, input code data and mode select data. Input code data
sets the DAC inputs while the mode select data sets the gain
and range of each DAC.
The versatile I/O port of the AD664 allows many different types
of data input schemes. For example, the input code for just one
of the DACs may be loaded and the output may or may not be
updated. Or, the input codes for all four DACs may be written,
and the outputs may or may not be updated.
The same applies for MODE SELECTION. The mode of just
one or many of the DACs may be rewritten and the user can
choose to immediately update the outputs or wait until a later
time to transfer the mode information to the outputs.
A user may also write both input code and mode information
into their respective first ranks and then update all second ranks
at once.
Finally, transparent operation allows data to be transferred from
the inputs to the outputs using a single control line. This feature
is useful, for example, in a situation where one of the DACs is
used in an A/D converter. The SAR register could be connected
directly to a DAC by using the transparent mode of operation.
Another use for this feature would be during system calibration
where the endpoints of the transfer function of each DAC would
be measured. For example, if the full-scale voltages of each
DAC were to be measured, then by making all four DACs
transparent and putting all “1s” on the input port, all four
DACs would be at full-scale. This requires far less software
AD664
Table II.AD664 Digital Truth TableLoad 1st Rank (data)
Mode Select
Update 2nd Rank
NOTES
X = Don’t Care.For 44-pin versions only.Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words.For MS, TR, LS = 0, a MS 1st write occurs.
Figure 9a.Update Output of a Single DAC
tDH
tLW
tCH
tAS
*FOR tLS > 0, THE WIDTH OF LS MUST BE
INCREASED BY THE SAME AMOUNT THAT
tLS IS GREATER THAN 0 ns.
The following sections detail the timing requirements for
various data loading schemes. All of the timing specifica-
tions shown assume VIH = 2.4 V, VIL = 0.4 V, VCC = +15 V,
VEE = –15 V and VLL = +5 V.
Load and Update One DAC OutputIn this first example, the object is simply to change the output of
one of the four DACs on the AD664 chip. The procedure is to
select the address bits that indicate the DAC to be programmed,
pull LATCH SELECT (LS) low, pull CHIP SELECT (CS)
low, release LS and then release CS. When CS goes low, data
enters the first rank of the input latch. As soon as LS goes high,
the data is transferred into the second rank and produces the
new output voltage. During this transfer, MS, TR, RD and RST
should be held high.
Preloading the First Rank of One DACIn this case, the object is to load new data into the first rank of
one of the DACs but not the output. As in the previous case, the
address and data inputs are placed on the appropriate pins. LS
is then brought to “0” and then CS is asserted. Note that in this
situation, however, CS goes high before LS goes high. The in-
put data is prevented from getting to the second rank and affect-
ing the output voltage.
Figure 10a.Preload First Rank of a DAC
tLH
tCW
tDS
tDH
tASFigure 10b.Preload First Rank of a DAC Timing
This allows the user to “preload” the data to a DAC and strobe
it into the output latch at some future time. The user could do
this by reproducing the sequence of signals illustrated in the
next section.
Update Second Rank of a DACAssuming that a new input code had previously been placed into
the first rank of the input latches, the user can update the out-
put of the DAC by simply pulling CS low while keeping LS,
MS, TR, RD and RST high. Address data is not needed in this
case. In reality, all second ranks are being updated by this pro-
cedure, but only those which receive data different from that
already there would manifest a change. Updating the second
rank does not change the contents of the first rank.
Figure 11.Update Second Rank of a DAC
The same options that exist for individual DAC input loading
also exist for multiple DAC input loading. That is, the user can
choose to update the first and second ranks of the registers or
preload the first ranks and then update them at a future time.
Preload Multiple First Rank RegistersThe first ranks of the DAC input registers may be preloaded
with new input data without disturbing the second rank data.
This is done by transferring the data into the first rank by bring-
Figure 12.Preload First Rank Registers
Load and Update Multiple DAC OutputsThe following examples demonstrate two ways to update all
DAC outputs. The first method involves doing all data transfers
during one long CS low period. Note that in this case, shown in
Figure 13, LS returns high before CS goes high. Data hold time,
relative to an address change, is 70 ns. This updates the outputs
of all DACs simultaneously.
Figure 13.Update All DAC Outputs
The second method involves doing a CS assertion (low) and an
LS toggle separately for each DAC. It is basically a series of
preload operations (Figure 10). In this case, illustrated in Figure
14, two LS signals are shown. One, labeled LS, goes high before
CS returns high. This transfers the “new” input word to the
DAC outputs sequentially. The second LS signal, labeled Alter-
nate LS, stays low until CS returns high. Using this sequence
loads the first ranks with each “new” input word but doesn’t up-
date the DAC outputs. To then update all DAC outputs simul-
taneously would require the signals illustrated in Figure 11.
Figure 14.Load and Update Multiple DACs
SELECTING GAIN RANGE AND MODES (44-PIN
VERSIONS)The AD664’s mode select feature allows a user to configure the
gain ranges and output modes of each of the four DACs.
AD664occupies the topmost eight bits of the input word. The last four
bits of the input word are “don’t cares.”
Figure 15 shows the format of the MODE SELECT word. The
first four bits determine the gain range of the DAC. When set to
be a gain of 1, the output of the DAC spans a voltage of 1 times
the reference. When set to a gain of 2, the output of the DAC
spans a voltage of 2 times the reference.
The next four bits determine the mode of the DAC. When set to
UNIPOLAR, the output goes from 0 to REF or 0 to 2 REF.
When the BIPOLAR mode is selected, the output goes from
–REF/2 to REF/2 or –REF to REF.
Figure 15.Mode Select Word Format
Load and Update Mode of One DACIn this next example, the object is to load new mode informa-
tion for one of the DACs into the first rank of latches and then
immediately update the second rank. This is done by putting the
new mode information (8-bit word length) onto the databus.
Then MS and LS are pulled low. Following that, CS is pulled
low. This loads the mode information into the first rank of
latches. LS is then brought high. This action updates the second
rank of latches (and, therefore, the DAC outputs). The load
cycle ends when CS is brought high.
In reality, this load cycle really updates the modes of all the
DACs, but the effect is to only change the modes of those
DACs whose mode select information has actually changed.
Figure 16a.Load and Update Mode of One DAC
tLS*0
tLW
tCH
tDH
Preloading the Mode Select RegisterMode data can be written into the first rank of the mode select
latch without changing the modes currently being used. This
feature is useful when a user wants to preload new mode infor-
mation in anticipation of strobing that in at a future time. Fig-
ure 17 illustrates the correct sequence and timing of control
signals to accomplish this task.
This allows the user to “preload” the data to a DAC and strobe
it into the output latch at some future time. The user could do
this by reproducing the sequence of signals illustrated in Figures
17c and 17d.
Figure 17a.Preload Mode Select Register
Figure 17b.Preload Mode Select Register Timing
Figure 17c.
Figure 17d.
Timing
Transparent Operation (44-Pin Versions)Transparent operation allows data from the inputs of the
AD664 to be transferred into the DAC registers without the
intervening step of being latched into the first rank of latches.
Two modes of transparent operation exist, the “partially trans-
parent” mode and a “fully transparent” mode. In the “partially
