AD6645ASQ-80 ,14-Bit, 80 MSPS A/D ConverterAPPLICATIONSlead PowerQuad 4 (LQFP_ED) specified from –40∞C to +85∞C.Multichannel, Multimode Receiv ..
AD6645ASQ-80 ,14-Bit, 80 MSPS A/D ConverterFEATURES generation in a wideband ADC family, preceded by the80 MSPS Guaranteed Sample Rate AD9042 ..
AD664AD-BIP ,Monolithic 12-Bit Quad DACspecifications.REV. CInformation furnished by Analog Devices is believed to be accurate andreliable ..
AD664BD-BIP ,Monolithic 12-Bit Quad DACFEATURESFour Complete Voltage Output DACs44-Pin PackageData Register Readback Feature“Reset to Zero ..
AD664BD-UNI ,Monolithic 12-Bit Quad DACSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
AD664BD-UNI ,Monolithic 12-Bit Quad DACSpecifications shown in boldface are tested on all production units at final electrical test. Resul ..
ADC0820BCV ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820BCWM ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820BCWMX ,8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionADC0820 8-Bit High Speed µP Compatible A/D Converter with Track/Hold FunctionMarch 2004ADC08208-Bit ..
ADC0820CCD ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF‘ = GND, RD-MODE, TA = TON to TMAX, unless ..
ADC0820CCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionBlock Diagram
Ft
BMW?
HIT! HUT
DIIVEIS PINS "
WI?
I4LSII
ADCOB2O
mama AID comm. ..
ADC0820CCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionGeneral Description
The ADC0820 is a high speed, microprocessor com-
patible, 8 bit analog-to-d ..
AD6645ASQ-80
14-Bit, 80 MSPS A/D Converter
14-Bit, 80 MSPS
A/D ConverterREV.0
FEATURES
80 MSPS Guaranteed Sample Rate
SNR = 75 dB, fIN 15 MHz @ 80 MSPS
SNR = 72 dB, fIN 200 MHz @ 80 MSPS
SFDR = 89 dBc, fIN 70 MHz @ 80 MSPS
100 dB Multitone SFDR
IF Sampling to 200 MHz
Sampling Jitter 0.1 ps
1.5 W Power Dissipation
Differential Analog Inputs
Pin-Compatible to AD6644
Two’s Complement Digital Output Format
3.3 V CMOS-Compatible
DataReady for Output Latching
APPLICATIONS
Multichannel, Multimode Receivers
Base Station Infrastructure
AMPS, IS-136, CDMA, GSM, WCDMA
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation
PRODUCT DESCRIPTIONThe AD6645 is a high-speed, high-performance, monolithic
14-bit analog-to-digital converter. All necessary functions,
including track-and-hold (T/H) and reference, are included on
the chip to provide a complete conversion solution. The AD6645
provides CMOS-compatible digital outputs. It is the fourth
generation in a wideband ADC family, preceded by the
AD9042 (12-bit, 41MSPS), the AD6640 (12-bit, 65 MSPS,
IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS).
Designed for multichannel, multimode receivers, the AD6645 is
part of Analog Device’s SoftCell™ transceiver chipset. The
AD6645 maintains 100 dB multitone, spurious-free dynamic
range (SFDR) through the second Nyquist band. This break-
through performance eases the burden placed on multimode
digital receivers (software radios) that are typically limited by
the ADC. Noise performance is exceptional; typical signal-to-
noise ratio is 74.5 dB through the first Nyquist band.
The AD6645 is built on Analog Devices’ high-speed complemen-
tary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are available in a thermally enhanced 52-
lead PowerQuad 4® (LQFP_ED) specified from –40∞C to +85∞C.
PRODUCT HIGHLIGHTSIF Sampling
The AD6645 maintains outstanding ac performance up to
input frequencies of 200 MHz. Suitable for multicarrier 3G
wideband cellular IF sampling receivers.
2. Pin Compatibility
The ADC has the same footprint and pin layout as the
AD6644, 14-Bit 40 MSPS/65 MSPS ADC.SFDR Performance and Oversampling
Multitone SFDR performance of –100 dBc can reduce the
requirements of high-end RF components and allows the use
of receive signal processors such as the AD6620 or AD6624/
AD6624A.
FUNCTIONAL BLOCK DIAGRAMSoftCell is a trademark of Analog Devices, Inc.
PowerQuad 4 is a registered trademark of Amkor Technology, Inc.
AD6645
DC SPECIFICATIONSNOTESVREF is provided for setting the common-mode offset of a differential amplifier such as the AD8138 when a dc-coupled analog input is required. VREF should be
buffered if used to drive additional circuit functions.Specified for dc supplies with linear rise-time characteristics. The use of dc supplies with linear rise-times of <45 ms is highly recommended.
Specifications subject to change without notice
DIGITAL SPECIFICATIONSNOTESAll ac specifications tested by driving ENCODE and ENCODE differentially.The functionality of the Over-Range bit is specified for a temperature range of 25∞C to 85∞C only.Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF will degrade performance.
(AVCC = 5 V, DVCC = 3.3 V; TMIN = –40�C, TMAX = +85�C, unless otherwise noted.)
(AVCC = 5 V, DVCC = 3.3 V; TMIN = –40�C, TMAX = +85�C, unless otherwise noted.)
–SPECIFICATIONS
AD6645
AC SPECIFICATIONS1NOTESAll ac specifications tested by driving ENCODE and ENCODE differentially.Analog input signal power swept from –10 dBFS to –100 dBFS.F1 = 30.5 MHz, F2 = 31.5 MHz.F1 = 55.25 MHz, F2 = 56.25 MHz.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS*Several timing parameters are a function of tENCL and tENCH.
Specifications subject to change without notice.
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40�C, TMAX = +85�C, unless
otherwise noted.)
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40�C, TMAX = +85�C, unless
otherwise noted.)
AD6645
SWITCHING SPECIFICATIONS (continued)ENCODE/DataReady
DataReady (DRY
APERTURE DELAY
NOTESSeveral timing parameters are a function of tENC and tENCH.To compensate for a change in duty cycle for tH_DR and tS_DR use the following equation:
NewtH_DR = (tH_DR – % Change(tENCH))
NewtS_DR = (tS_DR – % Change(tENCH))ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the Analog-to-Digital Converter, tE_RL = tH_E.ENCODE TO DATA Delay (Setup Time) is calculated relative to 80 MSPS (50% duty cycle). To calculate tS_E for a given encode, use the following equation:
NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: NewtS_E(TYP) = 25 ¥ 10–9 – 15.38 ¥ 10–9 + 9.8 ¥ 10–9 = 19.4 ¥ 10 –9).DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.DataReady to DATA Delay (tH_DR and tS_DR) is calculated relative to 80 MSPS (50% duty cycle) and is dependent on tENC and duty cycle. To calculate tH_DR and
tS_DR for a given encode, use the following equations:
NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: NewtH_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 7.2 ¥ 10–9 = 13.45 ¥ 10–9
NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 ¥ 10–9 – 6.25 ¥ 10–9 + 3.6 ¥ 10–9 = 9.85 ¥ 10–9
Specifications subject to change without notice.
Figure 1.Timing Diagram
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = 80 MSPS; TMIN = –40�C,
TMAX = +85�C, CLOAD = 10 pF, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*
THERMAL CHARACTERISTICS52-Lead PowerQuad 4 . . . . . . . . . . . . . . . . . . . . . .LQFP_ED
�JA = 23∞C/W . . . . . . . . . . . . . . . Soldered Slug, No Airflow
�JA = 17∞C/W . . . . . . . . Soldered Slug, 200 LFPM Airflow
�JA = 30∞C/W . . . . . . . . . . . . . Unsoldered Slug, No Airflow
�JA = 24∞C/W . . . . . . Unsoldered Slug, 200 LFPM Airflow
�JC = 2∞C/W . . . . . . . . . . . . . Bottom of Package (Heatslug)
Typical Four-Layer JEDEC Board Horizontal Orientation
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6645 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.
II.100% production tested at 25∞C and guaranteed by design
and characterization at temperature extremes.
III.Sample tested only.
IV.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
*Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability
of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute
maximum rating conditions for an extended period of time may affect device reliability.
ORDERING GUIDE
