AD6644AST-40 ,14-Bit, 40 MSPS/65 MSPS A/D ConverterSPECIFICATIONS (AV = 5 V, DV = 3.3 V; T = –25C, T = +85C)CC CC MIN MAXTest AD6644AST-40 A ..
AD6644AST-40 ,14-Bit, 40 MSPS/65 MSPS A/D ConverterSPECIFICATIONSCC CC MIN MAXTest AD6644AST-40 AD6644AST-65Parameter Temp Level Min Typ Max Min ..
AD6644AST-65 ,14-Bit, 40 MSPS/65 MSPS A/D ConverterSPECIFICATIONS (AV = 5 V, DV = 3.3 V; T = –25C, T = +85C)CC CC MIN MAXTest AD6644AST-40 AD6 ..
AD6645ASQ-105 ,14-Bit, 80 /105 MSPS A/D ConverterAPPLICATIONS52-lead PowerQuad 4 (LQFP_PQ4) specified from –40°C toMultichannel, Multimode Receivers ..
AD6645ASQ-80 ,14-Bit, 80 MSPS A/D ConverterAPPLICATIONSlead PowerQuad 4 (LQFP_ED) specified from –40∞C to +85∞C.Multichannel, Multimode Receiv ..
AD6645ASQ-80 ,14-Bit, 80 MSPS A/D ConverterFEATURES generation in a wideband ADC family, preceded by the80 MSPS Guaranteed Sample Rate AD9042 ..
ADC081S101CISD ,1MSPS, 8-Bit A/D Converter in SOT-23applicationsn Portable Systemswhere space is a critical consideration. TheADC081S101 isalso availab ..
ADC0820 ,CMOS High-Speed 8-Bit A/D Converter with Track/Hold Function
ADC08200CIMT/NOPB ,8-Bit, 20 Msps to 200 Msps, Low Power A/D Converter with Internal Sample-and-Hold 24-TSSOP -40 to 85FEATURES DESCRIPTIONThe ADC08200 is a low-power, 8-bit, monolithic2• Single-Ended Inputanalog-to-di ..
ADC0820BCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionApplications
Digital Signal Processing
High Speed Data Acquisition
Telecommunications
High ..
ADC0820BCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionFeatures
I Built-in track-and-hold function
I No missing codes
No external clocking
Sin ..
ADC0820BCM ,CMOS High Speed 8-Bit A/D Converter with Track/Hold FunctionELECTRICAL CHARACTERISTICS
(VDD = +5V, VREF+ = +5V, VREF‘ = GND, RD-MODE, TA = TON to TMAX, unless ..
AD6644AST-40-AD6644AST-65
14-Bit, 40 MSPS/65 MSPS A/D Converter
REV.0
14-Bit, 40 MSPS/65 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
FEATURES
65 MSPS Guaranteed Sample Rate
40 MSPS Version Available
Sampling Jitter < 300 fs
100 dB Multitone SFDR
1.3 W Power Dissipation
Differential Analog Inputs
Digital Outputs
Two’s Complement Format
3.3 V CMOS-Compatible
Data Ready for Output Latching
APPLICATIONS
Multichannel, Multimode Receivers
AMPS, IS-136, CDMA, GSM, Third Generation
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation
PRODUCT DESCRIPTIONThe AD6644 is a high-speed, high-performance, monolithic
14-bit analog-to-digital converter. All necessary functions,
including track-and-hold (T/H) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third genera-
tion in a wideband ADC family, preceded by the AD9042 (12-bit
41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.)
Designed for multichannel, multimode receivers, the AD6644 is
part of ADI’s new SoftCell™ transceiver chipset. The AD6644
achieves 100 dB multitone, spurious-free dynamic range (SFDR)
through the Nyquist band. This breakthrough performance eases
the burden placed on multimode digital receivers (software radios)
which are typically limited by the ADC. Noise performance is
exceptional; typical signal-to-noise ratio is 74 dB.
The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
W-CDMA). With oversampling, harmonics can be placed out-
side the analysis bandwidth. Oversampling also facilitates the use of
decimation receivers (such as the AD6620), allowing the noise
floor in the analysis bandwidth to be reduced. By replacing tradi-
tional analog filters with predictable digital components, modern
receivers can be built using fewer “RF” components, resulting
in decreased manufacturing costs, higher manufacturing yields,
and improved reliability.
The AD6644 is built on Analog Devices’ high-speed complemen-
tary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are packaged in a 52-terminal Low-
Profile Quad Plastic Flatpack (LQFP) specified from –25°C
to +85°C.
PRODUCT HIGHLIGHTSGuaranteed sample rate is 65 MSPS.Fully differential analog input stage.Digital outputs may be run on 3.3 V supply for easy interface
to digital ASICs.Complete Solution: reference and track-and-hold.Packaged in small, surface-mount, plastic, 52-terminal LQFP.
SoftCell is a trademark of Analog Devices, Inc.
AD6644–SPECIFICATIONS
DC SPECIFICATIONSTEMPERATURE DRIFT
ANALOG INPUTS (AIN, AIN)
POWER SUPPLY
NOTESAVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V.
Specifications subject to change without notice.
DIGITAL SPECIFICATIONSLOGIC OUTPUTS (D13–D0, DRY, OVR)
NOTESAll ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 22 for performance versus encode power.Digital output logic levels: DVCC = 3.3V, CLOAD = 10 pF. Capacitive loads >10pF will degrade performance.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(AVCC = 5 V, DVCC = 3.3V; TMIN = –25�C, TMAX = +85�C)
(AVCC = 5 V, DVCC = 3.3V; TMIN = –25�C, TMAX = +85�C)
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN =
–25�C, TMAX = +85�C)
AD6644
AC SPECIFICATIONS1AVCC = 5 V to 5.25 V for rated ac performance.Analog input signal power swept from –7 dBFS to –100 dBFS.F1 = 15MHz, F2 = 15.5MHz.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONSENCODE/DATA READY
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN = –25�C, TMAX = +85�C)
(AVCC = 5 V, DVCC = 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; TMIN =
–25�C, TMAX = +85�C, CLOAD = 10 pF)
AD6644–SPECIFICATIONSFigure 1.Timing Diagram
NOTESSeveral timing parameters are a function of tENC and tENCH.To compensate for a change in duty cycle for tH_DR and tS_DR use the following equation:
NewtH_DR = (tH_DR – % Change(tENCH)) × tENC/2
NewtS_DR = (tS_DR – % Change(tENCH)) × tENC/2.ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter.ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate tS_E for a given encode use the following equation:
NewtS_E = tENC(NEW) – tENC + tS_E (i.e., for 40 MSPS: NewtS_E(TYP) = 25 × 10–9 – 15.38 × 10–9 + 9.8 × 10–9 = 19.4 × 10 –9).DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.Data Ready to DATA Delay(tH_DR and tS_DR) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on tENC and duty cycle. In order to calculate tH_DR
and tS_DR for a given encode use the following equations:
NewtH_DR = tENC(NEW)/2 – tENCH + tH_DR (i.e., for 40 MSPS: NewtH_DR(TYP) = 12.5 × 10–9 – 7.69 × 10–9 + 8.6 × 10–9 = 13.4 × 10–9
NewtS_DR = tENC(NEW)/2 – tENCH + tS_DR (i.e., for 40 MSPS: NewtS_DR(TYP) = 12.5 × 10–9 – 7.69 × 10–9 + 5.5 × 10–9 = 10.3 × 10–9.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances (52-terminal LQFP); θJA = 33°C/W; θJC = 11°C/W.
These measurements were taken on a 6 layer board in still air with a solid ground
plane.
EXPLANATION OF TEST LEVELS
Test Level100% production tested.100% production tested at 25°C, and guaranteed by
design and characterization at temperature extremes.
IIISample tested only.Parameter is guaranteed by design and characterization
testing.Parameter is a typical value only.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6644 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.
