AD6640AST Fast Delivery |IC PHOENIX CO.,LIMITED

AD6640AST ,12-Bit, 65 MSPS IF Sampling A/D ConverterAPPLICATIONS ENCODEMSB LSBCellular/PCS Base StationsGND D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D ..
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AD6640AST
12-Bit, 65 MSPS IF Sampling A/D Converter
12-Bit, 65 MSPSIF Sampling A/D Converter
FEATURES
65 MSPS Minimum Sample Rate
80 dB Spurious-Free Dynamic Range
IF-Sampling to 70 MHz
710 mW Power Dissipation
Single +5 V Supply
On-Chip T/H and Reference
Twos Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
APPLICATIONS
Cellular/PCS Base Stations
Multichannel, Multimode Receivers
GPS Anti-Jamming Receivers
Communications Receivers
Phased Array Receivers
FUNCTIONAL BLOCK DIAGRAM
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GND
AIN
AIN
VREF
ENCODE
ENCODE
AVCCDVCC
PRODUCT DESCRIPTION
The AD6640 is a high speed, high performance, low power,
monolithic 12-bit analog-to-digital converter. All necessary
functions, including track-and-hold (T/H) and reference are
included on-chip to provide a complete conversion solution.
The AD6640 runs on a single +5V supply and provides CMOS-
compatible digital outputs at 65MSPS.
Specifically designed to address the needs of multichannel,
multimode receivers, the AD6640 maintains 80 dB spurious-
free dynamic range (SFDR) over a bandwidth of 25MHz.
Noise performance is also exceptional; typical signal-to-noise
ratio is 68dB.
The AD6640 is built on Analog Devices’ high speed complemen-
tary bipolar process (XFCB) and uses an innovative multipass
architecture. Units are packaged in a 44-terminal Plastic Thin
Quad Flatpack (TQFP) specified from –40°C to +85°C.
PRODUCT HIGHLIGHTSGuaranteed sample rate is 65 MSPS.Fully differential analog input stage specified for frequencies
up to 70 MHz; enables “IF Sampling.”Low power dissipation:710 mW off a single +5V supply.Digital outputs may be run on +3.3 V supply for easy inter-
face to digital ASICs.Complete Solution: reference and track-and-hold.Packaged in small, surface mount, plastic 44-terminal TQFP.
REV.0
DC SPECIFICATIONS
POWER SUPPLY
NOTESENCODE = 20 MSPSIf VREF is used to provide a dc offset to other circuits, it should first be buffered.The AD6640 is designed to be driven differentially. Both AIN and AIN should be driven at levels VREF ± 0.5 volts. The input signals should be 180 degrees out of phase to
produce a 2 V p-p differential input signal. See Driving the Analog Inputs section for more details.Analog input common-mode range specifies the offset range the analog inputs can tolerate in dc-coupled applications (see Figure 35 for more detail).
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
LOGIC OUTPUTS (D11–D0)
NOTESBest dynamic performance is obtained by driving ENC and ENC differentially. See Encoding the AD6640 section for more details. Performance versus ENC/ENC power is
shown in Figure 18 under Typical Performance Characteristics.For dc-coupled applications, Encode Input Common-Mode Range specifies the common-mode range the encode inputs can tolerate when driven differentially by minimum
differential input voltage of 0.4 V p-p. For differential input voltage swings greater than 0.4 V p-p, the common-mode range will change. The minimum value insures that the
(AVCC = +5 V, DVCC = +3.3V; TMIN = –408C, TMAX = +858C)
AD6640–SPECIFICATIONS
(AVCC = +5 V, DVCC = +3.3V; TMIN = –408C, TMAX = +858C)
SWITCHING SPECIFICATIONS1
NOTESAll switching specifications tested by driving ENCODE and ENCODE differentially.A plot of Performance vs. Encode is shown in Figure 16 under Typical Performance Characteristics.A plot of Performance vs. Duty Cycle (Encode = 65 MSPS) is shown in Figure 17 under Typical Performance Characteristics.Outputs driving one LCX gate. Delay is measured from differential crossing of ENC, ENC to the time when all output data bits are within valid logic levels.
Specifications subject to change without notice.
AC SPECIFICATIONS1
SINAD
Worst Harmonic
Worst Harmonic
Multitone SFDR (w/Dither)
NOTESAll ac specifications tested by driving ENCODE and ENCODE differentially.For a single test tone at –1 dBFS, the worst case spectral performance is typically limited by the direct or aliased 2nd or 3rd harmonic. If a system is designed such
that the 2nd and 3rd harmonics fall out-of-band, overall performance in the band of interest is typically improved by 5 dB. Worst Harmonic (4th or Higher) includes
4th and higher order harmonics and all other spurious components. Reference Figure 12 for more detail.See Overcoming Static Nonlinearities with Dither section for details on improving SFDR performance. To measure SFDR, eight tones from 14 MHz to 18 MHz
(0.5 MHz spacing) are swept from –20 dBFS to –90 dBFS. An open channel at 16 MHz is used to monitor SFDR.F1 = 14.9 MHz, F2 = 16 MHz.
AD6640
(AVCC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –408C, TMAX = +858C)
(AVCC = +5 V, DVCC = +3.3 V; ENCODE & ENCODE = 65 MSPS; TMIN = –408C, TMAX = +858C)
AD6640
ABSOLUTE MAXIMUM RATINGS1
NOTESAbsolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.Typical thermal impedances (44-terminal TQFP); θJA = 55°C/W.
ORDERING GUIDE
EXPLANATION OF TEST LEVELS
Test Level–100% production tested.–100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample
basis.
III–Sample tested only.–Parameter is guaranteed by design and characterization
testing.–Parameter is a typical value only.–All devices are 100% production tested at +25°C; sample
tested at temperature extremes.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6640 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
NOTEOutput coded as twos complement.
PIN CONFIGURATION
DVCC
DVCC
ENCODE
ENCODE
GND
GND
AIN
NC = NO CONNECT
VREF
AVCC
D0 (LSB)
GND
D11 (MSB)GNDGNDGNDGNDD10
GND
GND
GNDGNDGND
GND
AIN
AD6640
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the EN-
CODE pulse should be left in logic “1” state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. At a given clock rate, these
specs define an acceptable Encode duty cycle.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third order intermodulation product; re-
ported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels is lowered), or in dBFS (always
related back to converter full scale).
Worst Harmonic
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
AIN
AIN
AVCCVCH
VCL
Figure 2.Analog Input Stage
AVCC
ENCODEENCODE
Figure 3.Encode Inputs
AVCC
VREF
DVCC
DVCC
D0–D11
Figure 5.Digital Output Stage
VREF
AVCC
0.5mA
2.4V
AVCC
Figure 6.2.4 V ReferenceDIGITAL OUTPUTS
(D11–D0)
N + 1
ANALOG
INPUTS
ENCODE INPUTS
(ENCODE)
AIN
AIN
Figure 1.Timing Diagram
AD6640
–Typical Performance Characteristics
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
120
Figure 7. Single Tone at 2.2 MHz
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
120
Figure 8. Single Tone at 15.5 MHz
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
120
Figure 9. Single Tone at 31.0 MHz
ANALOG INPUT FREQUENCY – MHz
WORST CASE HARMONIC – dBc21283542495663
Figure 10. Harmonics vs. AIN
ANALOG INPUT FREQUENCY – MHz
SNR – dB21283542495663
Figure 11. Noise vs. AIN
ANALOG INPUT FREQUENCY – MHz110010
SNR, HARMONICS – dB, dBc42040200300
Figure 12. Harmonics, Noise vs. AIN
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
120
Figure 13.Two Tones at 15.0 MHz & 16.0 MHz
ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS – dBc and dBFS
–60–50–40–30–20–10
Figure 14.Single Tone SFDR
INPUT POWER LEVEL (F1 = F2) – dBFS
WORST CASE SPURIOUS – dBc and dBFS
–60–50–40–30–20–10
Figure 15.Two Tone SFDR
Figure 16. SNR, Worst Spurious vs. Encode
ENCODE DUTY CYCLE – %7530
SNR, WORST FULL SCALE SPURIOUS – dB, dBc40455055606570
Figure 17.SNR, Worst Spurious vs. Duty Cycle
ENCODE POWER – dBm
SNR, WORST FULL SCALE SPURIOUS – dB, dBc–9–6–3036912
Figure 18. SNR, Worst Spurious vs. Encode Power
AD6640
POWER RELATIVE TO ADC FULL SCALE – dB13.019.526.032.5
FREQUENCY – MHz
Figure 19.16K FFT without Dither

ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS – dBc
–60–50–40–30–20–10
Figure 20.SFDR without Dither
7555606570
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
–30
Figure 21.IF-Sampling at 70 MHz without Dither
POWER RELATIVE TO ADC FULL SCALE – dB6513.019.526.032.5
FREQUENCY – MHz
Figure 22.16K FFT with Dither

ANALOG INPUT POWER LEVEL – dBFS
WORST CASE SPURIOUS – dBc
–60–50–40–30–20–10
Figure 23.SFDR with Dither7555606570
FREQUENCY – MHz
POWER RELATIVE TO ADC FULL SCALE – dB
–30
Figure 24.IF-Sampling at 70 MHz with Dither
THEORY OF OPERATION
The AD6640 analog-to-digital converter (ADC) employs a two-
stage subrange architecture. This design approach ensures
12-bit accuracy, without the need for laser trim, at low power.
As shown in the functional block diagram, the AD6640 has
complementary analog input pins, AIN and AIN. Each analog
input is centered at 2.4 volts and should swing ±0.5 volts
around this reference (ref. Figure 2). Since AIN and AIN are
180 degrees out of phase, the differential analog input signal isvolts peak-to-peak.
Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in
hold mode. The held value of TH1 is applied to the input of a
6-bit coarse ADC. The digital output of the coarse ADC drives
a 6-bit DAC; the DAC is 12 bits accurate. The output of the 6-
bit DAC is subtracted from the delayed analog signal at the
input of TH3 to generate a residue signal. TH2 is used as an
analog pipeline to null out the digital delay of the coarse ADC.
The 6-bit coarse ADC word and 7-bit residue word are added
together and corrected in the digital error correction logic to
generate the output word. The result is a 12-bit parallel digital
CMOS-compatible word, coded as twos complement.
APPLYING THE AD6640
Encoding the AD6640
Best performance is obtained by driving the encode pins dif-
ferentially. However, the AD6640 is also designed to interface
with TTL and CMOS logic families. The source used to drive
the ENCODE pin(s) must be clean and free from jitter. Sources
with excessive jitter will limit SNR (reference Equation 1 under
“Noise Floor and SNR”).
0.01mF
TTL OR CMOS
SOURCE
Figure 25.Single-Ended TTL/CMOS Encode
The AD6640 encode inputs are connected to a differential input
stage (see Figure 3 under EQUIVALENT CIRCUITS). With
no input signal connected to either ENCODE pin, the voltage
dividers bias the inputs to 1.6 volts. For TTL or CMOS usage,
the encode source should be connected to ENCODE, Pin 3.
ENCODE should be decoupled using a low inductance or mi-
crowave chip capacitor to ground.
If a logic threshold other than the nominal 1.6 V is required, the
following equations show how to use an external resistor, Rx, to
raise or lower the trip point (see Figure 3; R1 = 17 kΩ, R2 = 8 kΩ).
0.01mF
ENCODE
SOURCE
Figure 26.Lower Logic Threshold for Encode
0.01mF
ENCODE
SOURCE
AVCC
Figure 27.Raise Logic Threshold for Encode
While the single-ended encode will work well for many applica-
tions, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, adB to 3 dB improvement in SNR can be realized. It is not
recommended that differential TTL logic be used however,
because most TTL families that support complementary outputs
are not delay or slew rate matched. Instead, it is recommended
that the encode signal be ac-coupled into the ENCODE and
ENCODE pins.
The simplest option is shown below. The low jitter TTL signal
is coupled with a limiting resistor, typically 100 ohms, to the
primary side of an RF transformer (these transformers are inex-
pensive and readily available; part number in Figure 28 is from
Mini-Circuits). The secondary side is connected to the EN-
CODE and ENCODE pins of the converter. Since both encode
inputs are self-biased, no additional components are required.
TTLENCODE
ENCODE
AD6640
100VT1–1T0.1mF
Figure 28.TTL Source – Differential Encode
A clean sine wave may be substituted for a TTL clock. In this
case, the matching network is shown below. Select a transformer
ratio to match source and load impedances. The input impedance
of the AD6640 encode is approximately 11kΩ differentially.
Therefore “R,” shown in the Figure 29, may be any value that is
convenient for available drive power.
AD6640
T1–1TSINE
SOURCE
Figure 29.Sine Source – Differential Encode
If a low jitter ECL clock is available, another option is to ac-
couple a differential ECL signal to the encode input pins as
shown below. The capacitors shown here should be chip ca-
pacitors but do not need to be of the low inductance variety.
–VS
Figure 30.Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
–VS
Figure 31.ECL Comparator for Encode
Driving the Analog Input
Because the AD6640 operates from a single +5 volt supply, the
analog input voltage range is offset from ground by 2.4 volt.
Each analog input connects through a 450 ohm resistor to the
2.4volt bias voltage and to the input of a differential buffer
(Figure 32). This resistor network on the input properly biases
the followers for maximum linearity and range. Therefore, the
analog source driving the AD6640 should be ac-coupled to the
input pins. Since the differential input impedance of the AD6640
is 0.9kΩ, the analog input power requirement is only –3 dBm,
simplifying the drive amplifier in many cases.
To take full advantage of this high input impedance, a 20:1
transformer would be required. This is a large ratio and could
result in unsatisfactory performance. In this case, a lower
step-up ratio could be used. For example, if RT were set to
260 ohms, along with a 4:1 transformer, the input would match
to a 50ohm source with a full-scale drive of +4 dBm (Figure
33). Note that the external load resistor, RT, is in parallel with
the AD6640 analog input resistance of 900 ohms. The external
resistor value can be calculated from the following equation:
where Z is the desired impedance (200 Ω for a 4:1 transformer
with 50 Ω input source).
0.1mF
1:4
ANALOG
INPUT
SIGNAL
Figure 33.Transformer-Coupled Analog Input Signal
If the lower drive power is attractive, a combination transformer
match and LC match could be employed that would use a 4:1
transformer with an LC as shown in Figure 34. This solution is
useful when good performance in the third Nyquist zone is
required. Such a requirement arises when digitizing high inter-
mediate frequencies in communications receivers.
0.1mF
1:4–j125V
+j100VANALOG
SIGNAL
–3dBm
Figure 34.Low Power Drive Circuit
In applications where gain is needed but dc-coupling is not
necessary, an extension of Figure 34 is recommended. Aohm gain block may be placed in front of the LC matching
network. Such gain blocks are readily available for commercial
applications. These low cost modules can have excellent NF and
intermodulation performance. This circuit is especially good for
the “IF” receiver application previously mentioned.
In applications where dc-coupling is required the following
circuit can be used (Figure 35). It should be noted that the
addition of circuitry for dc-coupling may compromise performance
in terms of noise, offset and dynamic performance. This circuit
requires an inverting and noninverting signal path. Additionally,
an offset must be generated so that the analog input to each pin
is centered near 2.4 volts. Since the input is differential, small

Partno	Mfg	Dc	Qty	Available	Descript
AD6640AST	AD	N/a	57	avai	12-Bit, 65 MSPS IF Sampling A/D Converter
AD6640AST		N/a	5	avai	12-Bit, 65 MSPS IF Sampling A/D Converter