AD6635BB ,4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)APPLICATIONS8 Independent Digital Receivers in a Single PackageMulticarrier, Multimode Digital Rece ..
AD6636BBCZ ,150 MSPS Wideband Digital Down Converter (DDC)Characteristics ........ 9 User-Configurable Built-In Self-Test (BIST)........ 47 ESD Caution. 9 Ch ..
AD6640AST ,12-Bit, 65 MSPS IF Sampling A/D ConverterSPECIFICATIONS (AV = +5 V, DV = +3.3 V; T = –408C, T = +858C)CC CC MIN MAXTest AD6640ASTP ..
AD6640AST ,12-Bit, 65 MSPS IF Sampling A/D ConverterAPPLICATIONS ENCODEMSB LSBCellular/PCS Base StationsGND D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D ..
AD6641BCPZ-500 , 250 MHz Bandwidth DPD Observation Receiver
AD6643BCPZ-200 , Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference
ADC081C027CIMK , ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter (ADC) with Alert Function
ADC081S021 ,Single Channel, 500 kSPS, 8-Bit A/D ConverterPin Descriptions and Equivalent CircuitsPin No. Symbol DescriptionANALOG I/O3V Analog inputs. This ..
ADC081S021CIMF ,Single Channel, 50 to 200 ksps, 8-Bit A/D Converter 6-SOT-23 -40 to 85Features 3 DescriptionThe ADC081S021 device is a low-power, single-1• Characterized and Specified O ..
ADC081S021CIMFX , Single Channel, 50 to 200ksps, 8-Bit A/D Converter
ADC081S051CIMF , ADC081S051 Single Channel, 200 to 500 ksps, 8-Bit A/D Converter
ADC081S101CIMF ,1MSPS, 8-Bit A/D Converter in SOT-23Block Diagram20110218 2ADC121S101/ADC101S101/ADC081S101ADC121S101/ADC101S101/ADC081S101Absolute Max ..
AD6635BB
4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)
REV.0
4-Channel, 80 MSPS WCDMA
Receive Signal Processor (RSP)
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Four 80 MSPS Wideband Inputs (14 Linear Bits Plus 3 RSSI)
4 Real Input Ports/2 Complex Input Ports
Processes 4 Wideband Channels (UMTS or cdma2000
1x) or 8 GSM/EDGE, IS136 Channels
8 Independent Digital Receivers in a Single Package
Four 16-Bit Parallel Output Ports and Four 8-Bit Link Ports
4 Programmable Digital AGC Loops with 96 dB Range
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
4 Interpolating Half-Band Filters
Flexible Control for Multicarrier and Phased Array
Programmable Attenuator Control for Clip Prevention and
External Gain Ranging via Level Indicator
3.3 V I/O, 2.5 V CMOS Core
User Configurable Built-in Self Test (BIST) Capability
APPLICATIONS
Multicarrier, Multimode Digital Receivers
GSM, IS136, EDGE, PHS, IS95, UMTS, cdma2000
Micro and Pico Cell Systems, Software Radios
Wireless Local Loop
Smart Antenna Systems
In-Building Wireless Telephony
AD6635
GENERAL DESCRIPTIONThe AD6635 is a multimode, 8-channel, digital Receive Signal
Processor (RSP) capable of processing up to four WCDMA
channels. Each channel consists of four cascaded signal-process-
ing elements: a frequency translator, two CIC decimating filters,
and a programmable coefficient-decimating filter. Each input
port has input level threshold detection circuitry for accommo-
dating large dynamic ranges or situations where gain ranging
converters are used. Quad 16-bit parallel output ports accom-
modate high data rate WBCDMA applications. On-chip
interpolating half-band filters can also be used to further
increase the output rate. In addition, each output port has a
digital AGC for accommodating large dynamic ranges using
smaller bit widths. The AGCs can maintain either signal level or
clipping level, depending on their mode. Link port outputs are
provided to enable glueless interfaces to Analog Devices’
TigerSHARC DSP core.
The AD6635 is part of Analog Devices’ SoftCell Multicarrier
transceiver chipset designed for compatibility with Analog Devices’
family of high sample rate IF sampling ADCs (AD9238/AD6645
12-bit and 14-bit). The SoftCell receiver comprises a digital
receiver capable of digitizing an entire spectrum of carriers and
digitally selecting the carrier of interest for tuning and channel
selection. This architecture eliminates redundant radios in wireless
base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, processing gain can improve the SNR of the ADC by
30 dB or more. In addition, the programmable RAM coefficient
filter allows antialiasing, matched filtering, and static equaliza-
tion functions to be combined in a single, cost-effective filter.
Half-band interpolating filters at the output are used in various
applications, especially in WCDMA or cdma2000 applications,
to increase the output rate from 2¥ to 4¥ the chip rate. The
AD6635 is equipped with four independent automatic gain
control (AGC) loops for direct interface to a RAKE receiver.
The AD6635 is compatible with standard ADC converters, such
as the AD664x, AD943x, AD923x, and the AD922x families of
data converters. The AD6635 is also compatible with the
AD6600 Diversity ADC, and hence can be designed into exist-
ing systems that use AD6600 ADCs.
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .2
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
RECOMMENDED OPERATING CONDITIONS . . . . . . .7
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . .7
GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . .8
MICROPROCESSOR PORT TIMING
CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . .10
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . .12
PIN CONFIGURATION (PIN OUT) . . . . . . . . . . . . . . . .13
PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . .14
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
INPUT DATA PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Gain Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Input Data Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Scaling with Fixed-Point ADCs . . . . . . . . . . . . . . . . . . . .24
Scaling with Floating-Point or Gain-Ranging ADCs . . . .25
NUMERICALLY CONTROLLED OSCILLATOR . . . . .26
Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . .26
NCO Frequency Hold-Off Register . . . . . . . . . . . . . . . . .26
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .26
By-Pass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Clear Phase Accumulator on Hop . . . . . . . . . . . . . . . . . .26
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Mode 00: Blank on IEN Low . . . . . . . . . . . . . . . . . . .27
Mode 01: Clock on IEN High . . . . . . . . . . . . . . . . . . .27
Mode 10: Clock on IEN Transition to High . . . . . . . .27
Mode 11: Clock on IEN Transition to Low . . . . . . . . .27
WB Input Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Sync Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SECOND-ORDER rCIC FILTER . . . . . . . . . . . . . . . . . . .27
rCIC2 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Example Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Decimation and Interpolation Registers . . . . . . . . . . . . . .29
rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
FIFTH-ORDER CIC FILTER . . . . . . . . . . . . . . . . . . . . . .29
CIC5 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . .30
RCF Decimation Register . . . . . . . . . . . . . . . . . . . . . . . .30
RCF Decimation Phase . . . . . . . . . . . . . . . . . . . . . . . . . .30
RCF Filter Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
RCF Output Scale Factor and Control Register . . . . . . . .31
INTERPOLATING HALF BAND FILTERS . . . . . . . . . .32
AUTOMATIC GAIN CONTROL . . . . . . . . . . . . . . . . . . .32
The AGC Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Desired Signal Level Mode . . . . . . . . . . . . . . . . . . . . . . .33
Desired Clipping Level Mode . . . . . . . . . . . . . . . . . . . . .34
RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Channel BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . .36
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Start with No Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Start with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Start with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Set Freq No Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Hop with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Hop with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PARALLEL OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . .37
Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
AGC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Master/Slave PCLKn Modes . . . . . . . . . . . . . . . . . . . . . .39
Parallel Port Pin Functionality . . . . . . . . . . . . . . . . . . . . .39
LINK PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Link Port Data Format . . . . . . . . . . . . . . . . . . . . . . . . . .40
Link Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
TigerSHARC Configuration . . . . . . . . . . . . . . . . . . . . . .41
AD6635 CHANNEL MEMORY MAP . . . . . . . . . . . . . . . .41
0x00-0x7F: Coefficient Memory (CMEM) . . . . . . . . . . .42
0x80: Channel Sleep Register . . . . . . . . . . . . . . . . . . . . .42
0x81: Soft_SYNC Register . . . . . . . . . . . . . . . . . . . . . . .42
0x82: Pin_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . .42
0x83: Start Hold-Off Counter . . . . . . . . . . . . . . . . . . . . .42
0x84: NCO Frequency Hold-Off Counter . . . . . . . . . . .42
0x85: NCO Frequency Register 0 . . . . . . . . . . . . . . . . . .42
0x86: NCO Frequency Register 1 . . . . . . . . . . . . . . . . . .42
0x87: NCO Phase Offset Register . . . . . . . . . . . . . . . . . .42
0x88: NCO Control Register . . . . . . . . . . . . . . . . . . . . .42
0x90: rCIC2 Decimation – 1 (MrCIC2-1) . . . . . . . . . . .44
0x91: rCIC2 Interpolation – 1 (LrCIC2-1) . . . . . . . . . . .44
0x92: rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
0x93: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
0x94: CIC5 Decimation – 1 (MCIC5-1) . . . . . . . . . . . . .44
0x95: CIC5 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
0x96: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
0xA0: RCF Decimation – 1 (MRCF-1) . . . . . . . . . . . . .44
0xA1: RCF Decimation Phase (PRCF) . . . . . . . . . . . . . .44
0xA2: RCF Number of Taps Minus 1 (NRCF-1) . . . . . .44
0xA3: RCF Coefficient Offset (CORCF) . . . . . . . . . . . .44
0xA4: RCF Control Register . . . . . . . . . . . . . . . . . . . . . .45
0xA5: BIST Register for I . . . . . . . . . . . . . . . . . . . . . . . .45
0xA6: BIST Register for Q . . . . . . . . . . . . . . . . . . . . . . .45
0xA7: BIST Control Register . . . . . . . . . . . . . . . . . . . . .45
0xA8: RAM BIST Control Register . . . . . . . . . . . . . . . .45
0xA9: Output Control Register . . . . . . . . . . . . . . . . . . . .45
Memory Map for Input Port Control Registers . . . . . . . . . .46
Input Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . .46
0x00: Lower Threshold A: . . . . . . . . . . . . . . . . . . . . . . . .46
0x01: Upper Threshold A: . . . . . . . . . . . . . . . . . . . . . . . .46
0x02: Dwell Time A: . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
0x03: Gain Range A Control Register: . . . . . . . . . . . . . . .46
0x04: Lower Threshold B: . . . . . . . . . . . . . . . . . . . . . . . .47
0x05: Upper Threshold B: . . . . . . . . . . . . . . . . . . . . . . . .47
AD66350x08: Port A Control Register . . . . . . . . . . . . . . . . . . . . .50
0x09: Port B Control Register . . . . . . . . . . . . . . . . . . . . .50
0x0A AGC A Control Register . . . . . . . . . . . . . . . . . . . . .50
0x0B AGC A Hold off Counter . . . . . . . . . . . . . . . . . . . .50
0x0C AGC A Desired Level . . . . . . . . . . . . . . . . . . . . . . .50
0x0D AGC A Signal Gain . . . . . . . . . . . . . . . . . . . . . . . .51
0x0E AGC A Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . .51
0x0F AGC A Pole Location . . . . . . . . . . . . . . . . . . . . . . .51
0x10 AGC A Average Samples . . . . . . . . . . . . . . . . . . . . .51
0x11 AGC A Update Decimation . . . . . . . . . . . . . . . . . .51
0x12 AGC B Control Register . . . . . . . . . . . . . . . . . . . . .51
0x13 AGC B Hold off Counter . . . . . . . . . . . . . . . . . . . .51
0x14 AGC B Desired Level . . . . . . . . . . . . . . . . . . . . . . .51
0x15 AGC B Signal Gain . . . . . . . . . . . . . . . . . . . . . . . . .51
0x16 AGC B Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . .51
0x17 AGC B Pole Location . . . . . . . . . . . . . . . . . . . . . . .52
0x18 AGC B Average Samples . . . . . . . . . . . . . . . . . . . . .52
0x19 AGC B Update Decimation . . . . . . . . . . . . . . . . . .52
0x1A Parallel Port Control A . . . . . . . . . . . . . . . . . . . . . .52
0x1B Link Port Control A . . . . . . . . . . . . . . . . . . . . . . . .52
0x1C Parallel Port Control B . . . . . . . . . . . . . . . . . . . . . .52
0x1D Link Port Control B . . . . . . . . . . . . . . . . . . . . . . . .53
0x1E Port Clock Control . . . . . . . . . . . . . . . . . . . . . . . . .53
TABLE OF CONTENTSMICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . .53
External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Access Control Register (ACR) . . . . . . . . . . . . . . . . . . . .54
Channel Address Register (CAR) . . . . . . . . . . . . . . . . . . .54
SOFT_SYNC Control Register . . . . . . . . . . . . . . . . . . . .55
PIN_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . .55
SLEEP Control Register . . . . . . . . . . . . . . . . . . . . . . . . .55
Data Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .55
Write Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Read Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Read/Write Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . .56
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . .56
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . .56
Serial Port Timing Specifications . . . . . . . . . . . . . . . . . . .56
SDI0, SDI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
SCLK0, SCLK4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . .58
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . .58
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .59
ARCHITECTUREEach channel of the AD6635 has four signal processing stages:
a Frequency Translator, a second-order Resampling Cascaded
Integrator Comb FIR Filter (rCIC2), a fifth-order Cascaded
Integrator Comb FIR Filter (CIC5), and a RAM Coefficient
FIR Filter (RCF). Multiple modes are supported for clocking
data into and out of the chip, and for providing flexibility for inter-
facing to a wide variety of digitizers. Programming and control is
accomplished via serial and/or microprocessor interfaces.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into inphase (I) and quadrature (Q) com-
ponents by multiplying with the complex NCO word. This stage
translates the input signal from a digital intermediate frequency
(IF) to digital baseband. Phase and amplitude dither may be
enabled on-chip to improve spurious performance of the NCO.
A phase-offset word is available to create a known phase rela-
tionship between multiple AD6635s or between channels.
Following frequency translation is a fixed coefficient, high speed,
second-order, Resampling Cascade Integrator Comb (rCIC2) filter
that reduces the sample rate based on the ratio between the deci-
mation and interpolation registers.
The next stage is a fifth-order Cascaded Integrator Comb (CIC5)
filter whose response is defined by the decimation rate. The pur-
pose of these filters is to reduce the data rate to the final filter stage
(RCF), so that it can calculate more taps for the same RCF band-
width. The CIC5 filter has better antialiasing (filtering) compared
to rCIC2. In light of this, the user is advised to use this filter only if
resampling is required or if the required decimation cannot be
handled by CIC5 alone.
The final stage is a sum-of-products FIR filter with program-
mable 20-bit coefficients, and decimation rates programmable
from 1 to 256 (1 to 32 in practice). The RAM Coefficient FIR
Filter (RCF) can handle a maximum of 160 taps.
The data coming out of the RCF can be sent to output ports or
to an interleaver. This section can interleave data from more
than one channel. One carrier can be processed using more than
one channel and the interleaver will interleave the data back into
the output section. This way, processing power from more than
one channel can be used for one carrier.
The interleaved data is sent into a fixed coefficient half-band
interpolation filter where data is interpolated by a factor of two.
Digital AGC following the half-band filter has a gain range of
96.3 dB. This AGC section is completely programmable in
terms of its response. Four each of half-band filters and AGCs
are present in the AD6635, as shown in the Functional Block
Diagram. These half-band filters and AGC sections can be
bypassed independent of each other.
The overall filter response for the AD6635 is the composite of
all decimating and interpolating stages. Each successive filter
stage is capable of narrower transition bandwidths, but requires
a greater number of CLK cycles to calculate the output. More
decimation in the first filter stage will minimize overall power
consumption. Each independent filter stage can be bypassed in
a unique way. Data from the chip is interfaced to the DSP via
either a high speed parallel port or a TigerSHARC compatible
link port. Each output can be independently configured to use
either the parallel port or the link port.
Figure 1 illustrates the tuning function of the AD6635 NCOs to
select and filter a single channel from a wide input spectrum.
The frequency translator “tunes” the desired carrier to base-
band. Figure 2 shows the combined filter response of the rCIC2,
CIC5, and RCF filters for a sample filter configuration.
AD6635Figure 1.AD6635 Frequency Translation of Wideband Input Spectrum
Figure 2.Composite Filter Response of rCIC2, CIC5, and RCF for a Sample Filter Configuration
AD6635
RECOMMENDED OPERATING CONDITIONSSpecifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
SPECIFICATIONS
AD6635
SPECIFICATIONS (continued)
GENERAL TIMING CHARACTERISTICS1, 2tCLKH
tRESL
tHI
tHS
tHSI
tPOCLKH
AD6635
GENERAL TIMING CHARACTERISTICS1, 2NOTESAll Timing Specifications valid over VDD range of 2.25 V to 2.75 V, and VDDIO range of 3.0 V to 3.6 V.CLOAD = 40 pF on all outputs unless otherwise specified.The timing parameters for Px[15:0], PxREQ, PxACK, LxCLKOUT, and Lx[7:0] apply for output ports A, B, C, and D. (x stands for A, B, C, or D.)
Specifications subject to change without notice.
AD6635
MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2NOTESAll Timing Specifications valid over VDD range of 2.25 V to 2.75 V, and VDDIO range of 3.0 V to 3.6 V.CLOAD = 40 pF on all outputs unless otherwise specified.Specification pertains to control signals: R/W, (WR), DS, (RD), CS0, CS1.
Specifications subject to change without notice.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD6635 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.6 V
Input Voltage . . . . . . . . . . . . .–0.3 V to +5.3 V (5 V Tolerant)
Output Voltage Swing . . . . . . . . . . .–0.3 V to VDDIO + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . .150∞C
Storage Temperature Range . . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . .280∞C
*Stresses greater than those listed above may cause permanent damage to the device
These are stress ratings only; functional operation of the devices at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Thermal Characteristics324-Lead BGA:
�JA = 16.87∞C/W, no airflow.
Thermal measurements made in the horizontal position on a
4-layer board.
EXPLANATION OF TEST LEVELS100% Production Tested.100% Production Tested at 25∞C, and Sample Tested at
Specified Temperatures.
IIISample Tested Only.Parameter Guaranteed by Design and Analysis.Parameter is Typical Value Only.100% Production Tested at 25∞C, and Sample Tested at
Temperature Extremes.
ORDERING GUIDE
AD6635
PIN CONFIGURATION
19mm � 19mm – 182 BALL ZAPHOD PACKAGE
BSC
BSC23456789101817161514131211
A1 BALL
CORNER
PIN CONFIGURATION (PIN OUT)3456789101112131415161718
AD6635
PIN FUNCTION DESCRIPTION
PIN FUNCTION DESCRIPTION (continued)
AD6635
TIMING DIAGRAMSFigure 3.Level Indicator Output Switching Characteristics (x = A, B, C, D; and y = A, B)
(For x = A and B, n = 0; and for x = C or D, n = 1)
Figure 4.Reset Timing Requirements
Figure 5.SCLK Switching Characteristics (n = 0, 4)
SCLKnFigure 6.Serial Port Input Timing Characteristics (n = 0, 4)
Figure 7.Input Timing for A and B Channels
Figure 8.SYNC Timing Inputs
Figure 9.PCLKn to CLKn Switching Characteristics Divide by 1
Figure 10.PCLKn to CLKn Switching Characteristics Divide by 2, 4, or 8
AD6635Figure 11.Master Mode PxACK to PCLKn Setup and Hold Characteristics
(n = 0 and x = A, B; or n = 1 and x = C, D)
Figure 12.Master Mode PxACK to PCLKn Switching Characteristics
(n = 0 and x = A, B; or n = 1 and x = C, D)
Figure 14.Slave Mode PxACK to PCLKn Setup and Hold Characteristics
(n = 0 and x = A, B; or n = 1 and x = C, D)
Figure 15.Slave Mode PxACK to PCLKn Switching Characteristics
(n = 0 and x = A, B; or n = 1 x = C, D)
Figure 16.Slave Mode PxREQ to PCLKn Switching Characteristics
(n = 0 and x = A, B; or n = 1 and x = C, D)
AD6635Figure 17.LxCLKOUT to PCLKn (n = 0 and x = A, B; or n = 1 and x = C, D) Switching Characteristics
Figure 18.LxCLKIN to LxCLKOUT Data Switching Characteristics
Figure 19.LxCLKOUT to Lx[7:0] Data Switching Characteristics
TIMING DIAGRAMS – INM Microport Mode (MODE = 0)Figure 20.INM Microport Write Timing Requirements. CLK0 corresponds to CS0, and CLK1 to CS1.
CS0 and CS1 both active (low) at the same time will cause errors in writing.
Figure 21.INM Microport Read Timing Requirements. CLK0 corresponds to CS0, and CLK1 to CS1.
AD6635
TIMING DIAGRAMS – MNM Microport Mode (MODE = 1)Figure 22.MNM Microport Write Timing Requirements. CLK0 corresponds to CS0, and CLK1 to CS1.
CS0 and CS1 both active (low) at the same time will cause errors in writing.
INPUT DATA PORTSThe AD6635 features four high speed ADC Input Ports, A, B,
C, and D. The input ports allow for the most flexibility with a
single tuner chip. These can be diversity inputs or truly inde-
pendent inputs such as separate antenna segments. Channels 0
through 3 can take data from either of the input ports A or B
independently. Similarly, Channels 4 through 7 can take data
from either of the Input Ports C or D independently. For added
flexibility, each input port can be used to support multiplexed
inputs, such as found on the AD6600 or other ADCs with multi-
plexed outputs. This added flexibility allows up to eight different
analog sources to be processed simultaneously by the eight
internal AD6635 channels.
In addition, the front end of the AD6635 contains circuitry that
enables high speed signal level detection and control. This is
accomplished with a unique high speed level detection circuit
that offers minimal latency and maximum flexibility to control
up to four analog signal paths. The overall signal path latency
from input to output on the AD6635 can be expressed in high
speed clock cycles. The equation below can be used to calculate
the latency.
MrCIC2 and MCIC5 are decimation values for the rCIC2 and CIC5
filters, respectively. NTAPS is the number of RCF taps chosen.
Input Data FormatEach input port consists of a 14-bit mantissa and 3-bit exponent. If
interfacing to a standard ADC, the exponent bits can be grounded.
If connected to a floating point ADC, such as the AD6600, the
exponent bits from that ADC product can be connected to the
input exponent bits of the AD6635. The mantissa data format is
twos complement, and the exponent is unsigned binary.
Input TimingThe data from each high speed input port is latched on the
rising edge of CLK. This clock signal is used to sample the
input port and clock the synchronous signal processing stages
that follow in the selected channels.
Figure 24.Input Data Timing Requirements
The clock signals can operate up to 80 MHz and have a 50%
duty cycle. In applications using high speed ADCs, the ADC
sample clock or data valid strobe is typically used to clock the
AD6635.
Figure 25.CLKn Timing Requirements (n = 0, 1)
Input Enable ControlThere are four Input Enable pins IENx (x = A, B, C, or D)
corresponding to individual Input Ports A through D. There are
four modes of operation possible while using each IEN pin.
Using these modes, it is possible to emulate operation of the
other RSPs such as the AD6620, which offer dual channel
modes normally associated with diversity operations. These
modes are IEN transition to Low, IEN transition to High, IEN
High, and Blank on IEN Low.
In the IEN High mode, the inputs and normal operations occur
when the Input Enable is High. In the IEN transition to Low
mode, normal operations occur on the first rising edge of the
clock after the IEN transitions to Low. Likewise in the IEN
transition to High mode, operations occur on the rising edge of
the clock after the IEN transitions to High. See the numerically
Controlled Oscillator section for more details on configuring the
Input Enable Modes. In Blank on IEN Low mode, the input
data is interpreted as zero when IEN is low.
A typical application for input modes would be to take the data
from an AD6600 Diversity ADC to one of the inputs of the
AD6635. The A/B_OUT from that chip would be tied to the
IEN of the corresponding input port. Then one channel within
the AD6635 would be set so that IEN transition to Low is
enabled. Another channel would be configured so that IEN
transition to High is enabled. This would allow two of the
AD6635 channels to be configured to emulate that AD6620 in
diversity mode and receive interleaved input data. Though the
NCO frequencies and other channel characteristics would need
to be set similarly, this feature allows the AD6635 to handle
interleaved data streams such as found on the AD6600.
The difference between the IEN transition to High and the
IEN High is found when a system clock is provided that is
higher than the data rate of the converter. It is often advanta-
geous to supply a clock that runs faster than the data rate so
that additional filter taps can be computed. This indeed leads
to better filtering. To ensure that other parts of the circuit
properly recognize the faster clock in the simplest manner,
the IEN transition to Low or High should be used. In this
mode, only the first clock edge that meets the setup and hold
times will be used to latch and process the input data. All other
clocks pulses are ignored by front end processing. However,
each clock cycle will still produce a new filter computation pair.
Gain SwitchingThe AD6635 includes circuitry that is useful in applications where
either large dynamic ranges exist, or where gain ranging converters
are employed. This circuitry allows digital thresholds to be set such
AD6635would be to provide a flag that could be used to quickly insert
an attenuator that would prevent ADC overdrive. If 18 dB (or
any other arbitrary value) of attenuation is switched in, then the
signal dynamic range of the system will have been increased by
18 dB. The process begins when the input signal reaches the
upper programmed threshold. In a typical application, this may
be set 1 dB (user definable) below full scale. When this input
condition is met, the appropriate LI signal (LIA-A, LIB-A, LIC-A,
or LID-A) associated with its corresponding input port (A through
D) is made active. This can be used to switch the gain or attenua-
tion of the external circuit. The LI line stays active until the input
condition falls below the lower programmed threshold. To provide
hysteresis, a dwell time register (see Memory Map for Input Con-
trol Registers) is available to hold off switching of the control line
for a predetermined number of clocks. Once the input condition is
below the lower threshold, the programmable counter begins
counting high speed clocks. As long as the input signal stays
below the lower threshold for the number of high speed clock
cycles programmed, the attenuator will be removed on the
terminal count. However, if the input condition goes above
the lower threshold with the counter running, the counter is
reset and input must fall below the lower threshold again to
initiate the process. This will prevent unnecessary switching
between states.
This is illustrated in Figure 26. When the input signal goes
above the upper threshold, the appropriate LI signal becomes
active. Once the signal falls below the lower threshold, the
counter begins counting. If the input condition goes above the
lower threshold, the counter is reset and starts again as shown.
Once the counter has terminated to 0, the LI line goes inactive.
Figure 26.Threshold Settings for LI
The LI line can be used for a variety of functions. It can be used
to set the controls of an attenuator, DVGA, or it can be inte-
grated and used with an analog VGA. To simplify the use of this
feature, the AD6635 includes two separate gain settings, one
when this LI line is inactive (rCIC2_QUIET[4:0] stored in Bits 9:5
of 0x92 register) and the other when active (rCIC2_LOUD[4:0]
stored in Bits 4:0 of 0x92 register). This allows the digital gain to
be adjusted to the external changes. In conjunction with the
gain setting, a variable holdoff is included to compensate for the
pipeline delay of the ADC and the switching time of the gain
control element. Together, these two features provide seamless
gain switching.
Another use of this pin is to facilitate a gain-range holdoff within a
gain-ranging ADC. For converters that use gain-ranging to
increase total signal dynamic range, it may be desirable to prohibit
internal gain ranging from occurring in some instances. For such
consistent with the gain ranges of the specific converter. Then
the holdoff delay can be set appropriately for any of a number of
factors, such as fading profile, signal peak-to-average ratio, or
any other time based characteristics that might cause unnecessary
gain changes.
The AD6635 has a total of eight gain control circuits to support
all channels, and hence can be used even when all input ports
have interleaved data. When data is interleaved on a certain
input port, the appropriate bit should be set in the Gain Range
Control Register. This way both interleaved channel data can be
monitored, and LIA-B, LIB-B, LIC-B, or LID-B pins associ-
ated with their corresponding Input Ports A through D act as
output indicators for the interleaved channel. LIx-A pins act as
indicators for input data corresponding to IENx Low, and LIx-B
act as indicators for input data corresponding to IENx High in
this mode. When interleaved channels are not used, LIx-B pins
are complimentary to LIx-A pins acting as indicators with oppo-
site polarity. It should be noted that the gain control circuits are
wideband and are implemented prior to any filtering elements to
minimize loop delay.
The chip also provides appropriate scaling of the internal data
based on the attenuation associated with the LI signal. In this
manner, data to the DSP maintains a correct scale value through-
out the process, making it entirely independent. Since there
often are finite delays associated with external gain switching
components, the AD6635 includes a variable pipeline delay that
can be used to compensate for external pipeline delays or gross
settling times associated with gain/attenuator devices. This delay
may be set for up to seven high speed clocks. These features
ensure smooth switching between gain settings.
Input Data ScalingThe AD6635 has four data input ports. Each accepts a 14-bit
mantissa (twos complement integer) IN[13:0], a 3-bit exponent
(unsigned integer) EXP[2:0], and the Input Enable(IEN). Input
Ports A and B are clocked by CLK0 and Input Ports C and D
are clocked by CLK1. These pins allow direct interfacing to both
standard fixed-point ADCs such as the AD9238 and AD6645, as
well as to gain-ranging ADCs such as the AD6600. For normal
operation with ADCs having fewer than 14 bits, the active bits
should be MSB justified and the unused LSBs should be tied low.
The 3-bit exponent, EXP[2:0] is interpreted as an unsigned
integer. The exponent will subsequently be modified by either
of rCIC2_LOUD[4:0] or rCIC2_QUIET[4:0], depending on
whether the LI line is active or not. These 5-bit scale values are
stored in the rCIC2 scale register (0x92) and the scaling is applied
before the data enters the rCIC2 resampling filter. These 5-bit
registers contain scale values to compensate for the rCIC2 gain,
external attenuator (if used), and the Exponent Offset (Expoff). If
no external attenuator is used, both the rCIC2_QUIET and
rCIC2_LOUD registers contain the same value. A detailed
explanation and equation for setting the attenuating scale
register is given in the Scaling with Floating-Point ADCs section.
Scaling with Fixed-Point ADCsFor fixed-point ADCs the AD6635 exponent inputs, EXP[2:0],
are typically not used and should be tied low. The ADC outputs
are tied directly to the AD6635 inputs, MSB-justified. The
Figure 27.Typical Interconnection of the AD6645
Fixed-Point ADC and the AD6635
Scaling with Floating-Point or Gain-Ranging ADCsAn example of the exponent control feature combines the
AD6600 and the AD6635. The AD6600 is an 11-bit ADC with
3 bits of gain ranging. In effect, the 11-bit ADC provides the
mantissa, and the 3 bits of relative signal strength indicator
(RSSI) for the exponent. Only five of the eight available steps
are used by the AD6600. See the AD6600 data sheet for addi-
tional details.
For gain-ranging ADCs such as the AD6600,
ExpInv = 1, ExpWeight = 0
where IN is the value of IN[13:0], Exp is the value of EXP[2:0],
and rCIC2 is the rCIC scale register value (0x92 bits 9-5 and 4-0).
“mod” is the remainder function. For example, mod(1,32) = 1,
mod(2,32) = 2, and mod(34,32) = 2.
The RSSI output of the AD6600 grows numerically with increas-
ing signal strength of the analog input (RSSI = 5 for a large
signal, RSSI = 0 for a small signal). When the Exponent Invert
Bit (ExpInv) is set to zero, the AD6635 will consider the small-
est signal at the IN[13:0] to be the largest, and as the EXP word
increases, it shifts the data down internally (EXP = 5 will shift a
14-bit word to the right by 5 internal bits before passing the
data to the rCIC2). In this example, if ExpInv = 0, the AD6635
regards the RSSI[2:0] = 5 as smallest signal and RSSI[2:0] = 0
as the largest signal possible on the AD6600. Thus, we can use
the Exponent Invert Bit to make the AD6635 exponent agree
with the AD6600 RSSI. Setting ExpInv = 1 forces the AD6635
to shift the data up (left) for growing EXP instead of down.
The exponent invert bit should always be set high for use
with the AD6600.
The Exponent Offset is used to shift the data up. For example,
Table I shows that with no rCIC2 scaling, 12 dB of range is
lost when the ADC input is at the largest level. This is not
desired because it lowers the dynamic range and SNR of the
system by reducing the signal of interest relative to the quan-
tization noise floor.
Table I.AD6600 Transfer Function with
AD6635 ExpInv = 1, and no ExpOffExpInv = 1, rCIC2 Scale = 0)
To avoid this automatic attenuation of the full-scale ADC sig-
nal, the ExpOff is used to move the largest signal (RSSI = 5) up
to the point where there is no downshift. In other words, once
the Exponent Invert bit has been set, the Exponent Offset should
be adjusted so that mod(7-5 + ExpOff,32) = 0. This is the case
when Exponent Offset is set to 30 since mod(32,32) = 0. Table II
illustrates the use of ExpInv and ExpOff when used with the
AD6600 ADC.
Table II.AD6600 Transfer Function with
AD6620 ExpInv = 1, and ExpOff = 30ExpInv = 1, ExpOff = 30, Exp Weight = 0)
This flexibility in handling the exponent allows the AD6635 to
interface with other gain-ranging ADCs besides the AD6600.
The Exponent Offset can be adjusted to allow up to seven
RSSI(EXP) ranges to be used as opposed to the AD6600’s five.
It also allows the AD6635 to be tailored in a system that employs
the AD6600 but does not utilize all of its signal range. For
example, if only the first four RSSI ranges are expected to
occur, then the ExpOff could be adjusted to 29, which would
make RSSI = 4 correspond to the 0 dB point of the AD6635.
Note that the above scale factor set in the rCIC2 register is only
to account for the ExpOff required. This register should also
account for compensating rCIC2 filter gain. The value required
for this will be given in the CIC2 filter section. Hence the final
value set in the rCIC2 register will be the sum total of ExpOff
and rCIC2 scale required.
AD6635Figure 28.Typical Interconnection of the AD6600
Gain-Ranging ADC and the AD6635.
NUMERICALLY CONTROLLED OSCILLATOR
Frequency TranslationThis processing stage comprises a digital tuner consisting of two
multipliers and a 32-bit complex NCO. Each channel of the
AD6635 has an independent NCO. The NCO serves as a quadra-
ture local oscillator capable of producing an NCO frequency
between –CLK/2 and +CLK/2 with a resolution of CLK/232 in the
complex mode. The worst-case spurious signal from the NCO is
better than –100 dBc for all output frequencies.
The NCO frequency value in registers 0x85 and 0x86 are inter-
preted as a 32-bit unsigned integer. The NCO frequency is
calculated using the equation below.
where NCO_FREQ is the 32-bit integer (registers 0x85 and
0x86) that the user needs to set in order to tune to a desired
frequency fCHANNEL, and CLKn is the AD6635 master clock rate
or Input data rate, depending on the Input Enable mode used.
See the Input Enable Control section to determine when it is
CLK and when it is Input data rate. For Channels 0 through 3
use CLK0, and for Channels 4 through 7 use CLK1.
“mod” is similar to the remainder function. For example if
fCHANNEL = 220 MHz and CLK = 80 MHz, then mod(220/80,1)
= mod(2.75,1) = 0.75.
But for negative frequencies, for example,
mod(–220/80,1) = mod(–1.75,1) = 0.25.
This definition works if NCO_FREQ register is treated as a
signed number.
NCO Frequency Holdoff RegisterWhen the NCO frequency registers are written, data is actually
passed to a shadow register. Data may be moved to the main
registers by one of two methods: when the channel comes out of
sleep mode, or when a SYNC hop occurs. In either event, a
counter can be loaded with the NCO Frequency Holdoff regis-
ter value. The 16-bit unsigned integer counter (0x84) starts
counting down, clocked by the Master clock, and when it reaches
zero, the new frequency value in the shadow register is written
Phase OffsetThe Phase Offset register (0x87) adds an offset to the phase
accumulator of the NCO. The NCO phase accumulator starts
with the value in this register in the event of a START SYNC.
This is a 16-bit register and is interpreted as a 16-bit unsigned
integer. A 0x0000 in this register corresponds to a 0 radian
offset, and a 0xFFFF corresponds to an offset of 2� ¥ (1 – 1/(216))
radians. This register allows multiple NCOs to be synchronized to
produce sine waves with a known and steady phase difference.
NCO Control RegisterThe NCO control register located at 0x88 is used to configure
the features of the NCO. These are controlled on a per channel
basis and are described below.
BypassThe NCO in the front end of the AD6635 can be bypassed.
Bypass mode is enabled by setting Bit 0 of 0x88 high. When the
NCO is bypassed, down conversion is not performed and the
AD6635 channel functions simply as a real filter on complex
data. This is useful for a baseband sampling application where
the A input is connected to the I signal path within the filter,
and the B input is connected to the Q signal path for Channels 0
through 3. Similarly, input C is connected to I signal path and
input D to Q signal path for Channels 4 through 7. This may be
desired if the digitized signal has already been converted to
baseband in prior analog stages or by other digital preprocessing.
Phase DitherThe AD6635 provides a phase dither option for improving the
spurious performance of the NCO. Phase dither is enabled by
setting Bit 1 of the NCO control register. When phase dither is
enabled by setting this bit high, spurs due to phase truncation in
the NCO are randomized. The energy from these spurs is
spread into the noise floor and spurious-free dynamic range is
increased at the expense of very slight decreases in the SNR.
The choice of whether phase dither is used in a system will
ultimately be decided by the system goals. If lower spurs are
desired at the expense of a slightly raised noise floor, it should
be employed. If a low noise floor is desired and the higher spurs
can be tolerated or filtered by subsequent stages, phase dither is
not needed.
Amplitude DitherAmplitude dither can also be used to improve spurious perfor-
mance of the NCO. Amplitude dither is enabled by setting Bit 2.
Amplitude dither improves performance by randomizing the
amplitude quantization errors within the angular-to-Cartesian
conversion of the NCO. This option may reduce spurs at the
expense of a slightly raised noise floor. Amplitude dither and phase
dither can be used together, separately, or not at all.
Clear Phase Accumulator on HopWhen Bit 3 is set, the NCO phase accumulator is cleared prior
to a frequency hop. This ensures a consistent phase of the NCO
on each hop. The NCO phase offset is unaffected by this setting
and is still in effect. If phase-continuous hopping is desired, this
bit should be cleared and the last phase in the NCO phase regis-
ter will be the initiating point for the new frequency.
Input Enable ControlThere are four different modes of operation for the input enable.
Input Select section). Similarly, any of the four filter Channels
4 through 7 can be programmed to take data from either of the
two Input Ports C or D. Along with data is the IENx signal. Each
filter channel can be configured to process the IEN signal in one
of four modes. Three of the modes are associated with when
data is processed based on a time division multiplexed data
stream. The fourth mode is used in applications that employ time
division duplex, such as radar, sonar, ultrasound, and com-
munications that involve TDD.
Mode 00: Blank on IEN LowIn this mode, data is blanked while the IEN line is low. While
the IEN line is high, new data is strobed on each rising edge of
the input clock. When the IEN line is lowered, input data is
replaced with zero values. During this period, the NCO contin-
ues to run such that when the IEN line is raised again, the
NCO value will be at the same value it would have been had the
IEN line never been lowered. This mode has the effect of blank-
ing the digital inputs when the IEN line is lowered. Back end
processing (rCIC2, CIC5, and RCF) continues while the IEN
line is high. This mode is useful for time division multiplexed
applications.
Mode 01: Clock on IEN HighIn this mode, data is clocked into the chip while the IEN line is
high. While the IEN line is high, new data is strobed on each
rising edge of the input clock. When the IEN line is lowered,
input data is no longer latched into the channel. Additionally,
NCO advances are halted. However, back end processing
(rCIC2, CIC5, and RCF) continues during this period. The
primary use for this mode is to allow for a clock that is faster
than the input sample data rate so that more filter taps can be
computed than would otherwise be possible. In the diagram
below, input data is strobed only while IEN is high, despite the
fact that the CLK continues to run at a rate four times faster
than the data.
Figure 29.Fractional Rate Input Timing (4 ¥ CLK)
in Mode 01
Mode 10: Clock on IEN Transition to HighIn this mode, data is clocked into the chip only on the first
clock edge after the rising transition of the IEN line. Although
data is only latched on the first valid clock edge, the back end
processing (rCIC2, CIC5, and RCF) continues on each avail-
able clock that may be present, similar to Mode 01. The NCO
phase accumulator is incremented only once for each new input
data sample, not once for each input clock.
Mode 11: Clock on IEN Transition to LowIn this mode, data is clocked into the chip only on the first clock
edge after the falling transition of the IEN line. Although data is
only latched on the first valid clock edge, the back end process-
ing (rCIC2, CIC5, and RCF) continues on each available clock
that may be present, similar to Mode 01. The NCO phase accu-
mulator is incremented only once for each new input data sample,
not once for each input clock.
WB Input SelectBit 6 in this register controls which input port is selected for
signal processing. For Channels 0 through 3, if this bit is set
high, then Input Port B (INB, EXPB, and IENB) is connected
to the selected AD6635 channel. If this bit is cleared, Input Port A
(INA, EXPA, and IENA) is connected to the selected filter
channel. Similarly for Channels 4 through 7 Input Port D is
selected when Bit 6 is set and Input Port C is selected when this
bit is cleared.
Sync SelectBits 7 and 8 of this register determine which external sync pin is
associated with the selected channel. The AD6635 has four sync
pins named SYNCA, SYNCB, SYNCC, and SYNCD. Any of
these sync pins can be associated with any of the eight receiver
channels within the AD6635. Additionally, if only one sync
signal is required for the system, all eight receiver channels can
reference the same sync pin. Bit value 00 selects SYNCA, 01
selects SYNCB, 10 selects SYNCC, and 11 selects SYNCD.
SECOND-ORDER rCIC FILTERThe rCIC2 filter is a second-order resampling Cascaded Inte-
grator Comb filter. The resampler is implemented using a
unique technique that does not require the use of a high speed
clock, thus simplifying the design and saving power. The
resampler allows noninteger relationships between the master
clock and the output data rate. This allows easier implementa-
tion of systems that are either multimode or require a master
clock that is not a multiple of the data rate to be used.
Interpolation up to 512 and decimation up to 4096 is allowed in
the rCIC2. The resampling factor for the rCIC2 (L) is a 9-bit
integer. When combined with the 12-bit decimation factor M,
the total rate change can be any fraction in the form of:
The only constraint is that the ratio L/M must be less than or
equal to 1. This implies that the rCIC2 decimates by 1 or more.
Resampling is implemented by apparently increasing the input
sample rate by the factor L using zero stuffing for the new data
samples. Following the resampler is a second-order cascaded
integrator comb filter. Filter characteristics are determined only
by the fractional rate change (L/M).
The filter can process signals at the full rate of the input port
80 MHz. The output rate of this stage is given by the equa-
tion below.
AD6635Both LrCIC2 and MrCIC2 are unsigned integers. The interpolation
rate (LrCIC2) may be from 1 to 512 and the decimation (MrCIC2)
may be from 1 to 4096. The stage can be bypassed by setting
the decimation/interpolation to 1/1.
The frequency response of the rCIC2 filter is given by the fol-
lowing equations.
The scale factor, SrCIC2 is a programmable unsigned 5-bit value
between 0 and 31. This serves as an attenuator that can reduce
the gain of the rCIC2 in 6 dB increments. For the best dynamic
range, SrCIC2 should be set to the smallest value possible (i.e.,
lowest attenuation) without creating an overflow condition.
This can be safely accomplished using the equation below,
where input_level is the largest fraction of full scale possible at
the input to the AD6635 (normally 1). The rCIC2 scale factor
The ceil function used above denotes the next whole integer,
and the floor function denotes the previous whole integer. For
example, ceil(4.5) is 5, while floor(4.5) is 4.
There are two scale registers (rCIC2_LOUD[4:0] Bits 4–0 in
0x92), and (rCIC2_QUIET[4:0] Bits 9–5 in 0x92), which are
used to implement the SrCIC2 scale factor. The value written into
the these programmable registers is the sum total of SrCIC2, ExpOff
required for floating point ADCs (explained in the Input Port
section), and any compensation for external attenuation that
may be activated using the LI (level indicator) pins. The third
component can have different values when the LI pin is active
and when it is inactive, and hence two registers, rCIC2_LOUD
and rCIC2_QUIET. The sum total of these components is
supplied to the AD6635 as rCIC2_LOUD and rCIC2_QUIET
registers, and these registers can contain a maximum number of
31. It should also be noted that the scaling specified by these
register is applied at only one place in the AD6635 channel
(before the rCIC2 filter).
The gain and passband droop of the rCIC2 should be calculated
by the equations above, as well as the filter transfer equations
where IN is the value of INx[13:0] (x = A, B, C, D), Exp is the
value of EXPx[2:0], and rCIC2 is the value of the 0x92
(rCIC2_QUIET[4:0] or rCIC2_LOUD[4:0], depending on
LI pin) scale register.
rCIC2 RejectionTable III illustrates the amount of bandwidth in percent of the
data rate into the rCIC2 stage. The data in this table may be
scaled to any other allowable sample rate up to 80 MHz. The
table can be used as a tool to decide how to distribute the deci-
mation between rCIC2, CIC5 and the RCF.
Table III.SSB rCIC2 Alias Rejection Table (fSAMP = 1)
Bandwidth Shown as Percentage of fSAMP. (input rate)
Example CalculationsGoal: Implement a filter with an input sample rate of 10 MHz
requiring 100 dB of alias rejection for a ±7 kHz pass band.
Solution: First determine the percentage of the sample rate that
is represented by the pass band.
In the –100 dB column on the right of the table, look for a
value greater than or equal to your passband percentage of the
clock rate. Then look across to the extreme left column and
find the corresponding rate change factor (MrCIC2/LrCIC2). Referring
to the table, notice that for a MrCIC2/LrCIC2 of 4, the frequency
having –100 dB of alias rejection is 0.071%, which is slightly
greater than the 0.07% calculated. Therefore, for this example,
the maximum bound on rCIC2 rate change is 4. Choosing a
higher MrCIC2/LrCIC2 results in less alias rejection than the
required 100 dB.
An MrCIC2/LrCIC2 of less than 4 would still yield the required
rejection, however the power consumption can be minimized by
decimating as much as possible in this rCIC2 stage. Decimation
in rCIC2 lowers the data rate, and thus reduces power consumed
of L/M that yields 0.25 will work (1/4, 2/8, or 4/16). However,
for the best dynamic range, the simplest ratio should be used.
For example, 1/4 gives better performance than 4/16.
Decimation and Interpolation RegistersrCIC2 decimation values are stored in register 0x90. This 12-bit
register contains the decimation portion less 1. The interpola-
tion portion is stored in register 0x91. This 9-bit value holds the
interpolation less 1.
rCIC2 ScaleRegister 0x92 contains the scaling information for this section of
the circuit. The primary function is to store the scale value
computed in the sections above.
Bits 4–0 (rCIC2_LOUD[4:0]) of this register are used to contain
the scaling factor for the rCIC2 during conditions of strong
signals. These five bits represent the rCIC2 scalar calculated
above, plus any external signal scaling with an attenuator.
Bits 9–5 (rCIC2_QUIET[4:0]) of this register are used to con-
tain the scaling factor for the rCIC2 during conditions of weak
signals. In this register, no external attenuator would be consid-
ered and is not included. Only the value computed above for
rCIC2 compensation is stored in these bits.
Bit 10 of this register is used to indicate the value of the external
exponent. If this bit is set low, then external exponent represents
6 dB per step as in the AD6600. If this bit is set high, each
exponent represents a 12 dB step.
Bit 11 of this register is used to invert the external exponent
before internal calculation. This bit should be set high for gain-
ranging ADCs that use an increasing exponent to represent an
increasing signal level. This bit should be set low for gain-ranging
ADCs that use a decreasing exponent for representing an
increasing signal level.
In applications that do not require the features of the rCIC2, it
may be bypassed by setting the L/M ratio to 1/1. This effectively
bypasses all circuitry of the rCIC2 except the scaling which is
still in effect.
FIFTH-ORDER CIC FILTERThe third signal processing stage, CIC5, implements a sharper,
fixed-coefficient, decimating filter sharper than rCIC2. The
input rate to this filter is fSAMP2. The maximum input rate to this
filter is equal to the input rate into the AD6635, so bypassing
the rCIC2 filter is allowed.
The decimation ratio, MCIC5, may be programmed from 2 to
32 (all integer values). The frequency response of the filter is
given by the following equations. The gain and passband droop
of CIC5 should be calculated by these equations. Both parameters
may be compensated for in the RCF stage.
The scale factor SCIC5 is a programmable, unsigned integer
between 0 and 20. It serves to control the attenuation of the
data into the CIC5 stage in 6 dB increments. For the best dynamic
range, SCIC5 should be set to the smallest value possible (low-
est attenuation) without creating an overflow condition. This
can be safely accomplished using the equation below, where
OLrCIC2 is the largest fraction of full scale possible at the input
to this filter stage. This value is output from the rCIC2 stage,
then pipelined into the CIC5.
The output rate of this stage is given by the equation below.
CIC5 RejectionTable IV illustrates the amount of bandwidth in percentage of the
clock rate (input rate) that can be protected with various decima-
tion rates and alias rejection specifications. The maximum input
rate into the CIC5 is 80 MHz when the rCIC2 decimates by 1. As
in the previous table, these are the 1/2 bandwidth characteristics
of the CIC5. Notice that the CIC5 stage can protect a much wider
band to any given rejection level compared to the rCIC2 stage.
This table helps to calculate an upper bound on decimation,
MCIC5, for given desired filter characteristics.
AD6635
Table IV. SSB CIC5 Alias Rejection Table (fSAMP2 = 1).
Bandwidths are given as percentage of fSAMP2.
RAM COEFFICIENT FILTERThe final signal processing stage for each individual channel is a
sum-of-products decimating filter with programmable coeffi-
cients. A simplified block diagram is shown below. The data
memories I-RAM and Q-RAM store the 160 most recent com-
plex samples from the previous filter stage with 20-bit resolution.
The coefficient memory, CMEM, stores up to 256 coefficients
with 20-bit resolution. On every CLK cycle, one tap for I and
one tap for Q are calculated using the same coefficients. The
RCF output consists of 24-bit data.
Figure 30.RAM Coefficient Filter (RCF) Block Diagram
RCF Decimation RegisterEach RCF channel can be used to decimate the data rate. The
decimation register is an 8-bit register and can decimate from
1 to 256. The RCF decimation is stored in 0xA0 in the form of
MRCF – 1. The input rate to the RCF is fSAMP5.
RCF Decimation PhaseThe RCF decimation phase can be used to synchronize multiple
filters within a chip. This is useful when using multiple channels
within the AD6635 to implement a polyphase filter allowing the
resources of several RCF filters to be paralleled. In such an
application, two RCF filters would be processing the same data
from the CIC5. However, each filter will be delayed by one half
the decimation rate, thus creating a 180∞ phase difference between
the two halves.
The AD6635 filter channel uses the value stored in this register
to preload the RCF counter. Therefore, instead of starting from
0 (coefficient number 0), the counter is loaded with
thus creating an offset in the processing that should be equiva-
lent to the required processing delay. The number of channels
or RCFs used to process one carrier is used in the above equa-
tion. fCLK is the input clock rate to the AD6635 and fRCF is the
input sample rate to the RCF from the CIC5 stage. This data is
stored in 0xA1 as an 8-bit number. The RCF decimation phase
can be used only when the ratio of RCF decimation and num-
ber of RCFs used is an integer.
RCF Filter LengthThe maximum number of taps this filter can calculate, NTAPS, is
given by the equation below. The value NTAPS – 1 is written to
the Channel register within the AD6635 at address 0xA2.
The function “min” used above gives the minimum of all the
expressions inside the parenthesis.
The RCF coefficients are located in addresses 0x00 to 0x7F and
are interpreted as 20-bit twos complement numbers. When
writing the coefficient RAM, the lower addresses will be multi-
plied by relatively older data from the CIC5 and the higher
coefficient addresses will be multiplied by relatively newer data
from the CIC5. The coefficients need not be symmetric and the
coefficient length, NTAPS, may be even or odd. If the coefficients
are symmetric, then both sides of the impulse response must be
written into the coefficient RAM.
Although the base memory for coefficients is only 128 words
long, the actual length is 256 words long. There are two pages,
each 128 words long. The page is selected by Bit 8 of 0xA4.
