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AD6630AR
Differential, Low Noise IF Gain Block with Output Clamping
REV.0
Differential, Low Noise IF Gain
Block with Output Clamping
FUNCTIONAL BLOCK DIAGRAM
NC = NO CONNECTVCC
IP2
IP1
IP1
IP2
CLLO
CLHI
CD1
VEE
CMD
CD2
VCC
FEATURES
24 dB Gain
4 dB Noise Figure
Easy Match to SAW Filters
Output Limiter Adjustable +8.5 dBm to +12 dBm
700 MHz Bandwidth
10 V Single or Dual 5 V Power Supply
300 mW Power Dissipation
APPLICATIONS
ADC IF Drive Amp
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
PRODUCT DESCRIPTIONThe AD6630 is an IF gain block designed to interface between
SAW filters and differential input analog-to-digital converters.
The AD6630 has a fixed gain of 24 dB and has been optimized
for use with the AD6600 and AD6620 in digitizing narrowband
IF carriers in the 70 MHz to 250 MHz range.
Taking advantage of the differential nature of SAW filters, the
AD6630 has been designed as a differential in/differential out
gain block. This architecture allows 100 dB of adjacent channel
blocking using low cost SAW filters. The AD6630 provides
output limiting for ADC and SAW protection with ,10° phase
variation in recovery from overdrive situations.
Designed for “narrow-band” cellular/PCS receivers, the high
linearity and low noise performance of the AD6630 allows for
implementation in a wide range of applications ranging from
GSM to CDMA to AMPS. The clamping circuitry also main-
tains the phase integrity of an overdriven signal. This allows
phase demodulation of single carrier signals with an overrange
signal.
While the AD6630 is optimized for use with the AD6600 Dual
Channel, Gain Ranging ADC with RSSI, it can also be used in
many other IF applications. The AD6630 is designed with an
input impedance of 200 W and an output of 400 W. In the typi-
cal application shown below, these values match the real portion
of a typical SAW filter. Other devices can be matched using
standard matching network techniques.
The AD6630 is built using Analog Devices’ high speed comple-
mentary bipolar process. Units are available in a 300 mil SOIC
(16 leads) plastic surface mount package and specified to operate
over the industrial temperature range (–40°C to +85°C).
Figure 1.Reference Design
AD6630–SPECIFICATIONS
NORMAL OPERATING CONDITIONS
DC SPECIFICATIONS
AC SPECIFICATIONS
(TMIN = –408C, TMAX = +858C. Output dc levels are nominally at VM, where VM = VCC + VEE = [+5 V + (–5 V)] = 0.
Inputs should be AC coupled.)
(TMIN = –408C, TMAX = +858C. All AC production tests are performed at 5 MHz. 70 MHz and 250 MHz
performance limits are correlated to 5 MHz testing based on characterization data.)
AD6630NOTESAll specifications are valid across the operating frequency range when the source and load impedance are a conjugate match to the amplifier’s input and output
impedance.Test is for two tones separated by 1 MHz for IFs at 70 MHz and 250 MHz at –23 dBm per tone input.Low Level Clamp is selected by connecting pin CLLO to the negative supply, while pin CLHI is left floating. Clamping can be set at lower levels by connecting pin
CLLO and CLHI to the negative supply through an external resistor.High Level Clamp is selected by connecting pin CLHI to the negative supply, while pin CLLO is left floating, this allows the maximum linear range of the device to
be utilized.Output clamp levels are measured for hard clamping with a +3 dBm input level. Valid for a maximum input level of +8 dBm/200 W = 3.2 V p-p—differential.Measured as the change in output phase when the input level is changed from –53 dBm to +8 dBm (i.e., from linear operation to clamping).Ratio of the differential output signal (referenced to the input) to the common-mode input signal presented to all input pins.Ratio of signal on supply to differential output (<500 kHz).
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS100% production tested.
II.100% production tested at +25°C, and guaranteed by
design and analysis at temperature extremes.
III.Sample tested only.
IV.Parameter guaranteed by design and analysis.Parameter is typical value only.
VI.100% production tested at +25°C, and sample tested at
temperature extremes.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD6630
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
INPUT FREQUENCY – MHz
INTERCEPT POINT – dBm
100300Figure 2.3rd Order Intercept (IP3) vs. Frequency
GAIN – dB
Typical Performance Characteristics
INPUT FREQUENCY – MHz
1dB COMPRESSION POINT
100300Figure 4.1 dB Compression Point (Typical)
OUTPUT AMPLITUDE – dBm
AD6630
MAIN
DIVERSITY
–28dBm–29dBm–14dBm
LOCAL
OSCILLATOR
–23dBm–25dBm–10dBm–15dBm9dBm4dBm
–1dB15dB–9dB–2dB15dB–5dB24dB–5dB
SAWSAW
ANTENNA
–104dBm
–43dBm
–28dBm
–16dBm
–15dBm
AD6630 INPUT
–91dBm
–30dBm
–15dBm
–3dBm
–2dBm
AD6630 OUTPUT
–67dBm
–6dBm
+9dBm
+9dBm
+9dBm
AD6600 INPUT
–71dBm
–10dBm
+4dBm
+4dBm
+4dBmFigure 6.GSM Design Example
THEORY OF OPERATIONThe AD6630 amplifier consists of two stages of gain. The first
stage is differential. This differential amplifier provides good
common-mode rejection to common-mode signals passed by
the SAW filter. The second stage consists of matched current
feedback amplifiers on each side of the differential pair. These
amplifiers provide additional gain as well as output drive capa-
bility. Gain set resistors for these stages are internal to the de-
vice and cannot be changed, allowing fixed compensation for
optimum performance.
Clamping levels for the device are normally set by tying CLLO
or CLHI pins to the negative supply. This internally sets bias
points that generate symmetric clamping levels. Clamping is
achieved primarily in the output amplifiers. Additional input
stage clamping is provided for additional protection. Clamping
levels may be adjusted to lower levels as discussed below.
APPLICATIONSThe AD6630 provides several useful features to meet the needs
of radio designers. The gain and low noise figure of the device
make it perfect for providing interstage gain between differential
SAW filters and/or analog-to-digital converters (ADC). Addi-
tionally, the on-board clamping circuitry provides protection for
sensitive SAW filters or ADCs. The fast recovery of the clamp
circuit permits demodulation of constant envelope modulated
IF signals by preserving the phase response during clamping.
The following topics provide recommendations for using the
AD6630 in narrowband, single carrier applications.
Adjusting Output Clamp LevelsNormally, the output clamp level is set by tying either CLLO or
CLHI to ground or VEE. It is possible to set the limit between
8.5 dBm and 12 dBm levels by selecting the appropriate exter-
nal resistor.
To set to a different level, CLLO and CLHI should be tied
together and then through a resistor to ground. The value of the
resistor can be selected using the following equation.
This equation is derived from measured data at 170 MHz. Clamp
levels vary with frequency, see Figure 5. Output clamp levels
less than 8.5 dBm will result in damage to the clamp circuitry
unless the absolute maximum input power is derated. Similarly,
the output clamp level cannot be set higher than 12 dBm.
Figure 7. Clamp Level Resistor
Matching SAW FiltersThe AD6630 is designed to easily match to SAW filters. SAW
filters are largely capacitive in nature. Normally a conjugate
match to the load is desired for maximum power transfer.
Another way to treat the problem is to make the SAW filter look
purely resistive. If the SAW filter load looks resistive there is no
lead or lag in the current vs. voltage. This may not preserve
maximum power transfer, but maximum voltage swing will
exist. All that is required to make the SAW filter input or output
look real is a single inductor shunted across the input. When the
correct value is used, the impedance of the SAW filter becomes
real.
Figure 8.Saw Filter Model (170 MHz)
EVALUATION BOARDFigures 9, 10 and 12 refer to the schematic and layout of the
AD6630AR as used on Analog Devices’ GSM Diversity Re-
ceiver Reference Design (only the IF section is shown). Figure
14 references the schematic of the stand-alone AD6630 evalua-
tion board and uses a similar layout. The evaluation board uses
center tapped transformers to convert the input to a differential
AD6630
C102
0.1mF
L1AL1
SMA
CHNA
+10VFigure 9.Reference Design Schematic (One Channel)
Figure 10.Reference Design PCB Layout
CLLO
CLHI
OUTPUTFigure 12.Reference Design Component Placement (Two
Channels Shown)
