AD6624AABC ,Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)CHARACTERISTICS . . . . . . . . . . . . . . . . 3 SBM0 . . . . . . . . . . . . . . . . . . . . . . ..
AD6624AS ,Four-channel, 80 MSPS digital receive signal processor (RSP)CHARACTERISTICS . . . . . . . . . . . . 4ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . ..
AD6630AR ,Differential, Low Noise IF Gain Block with Output Clampingspecifications are valid across the operating frequency range when the source and load impedance ar ..
AD6630AR ,Differential, Low Noise IF Gain Block with Output ClampingSPECIFICATIONSTest1Parameter Temp Level Min Typ Max UnitsGAIN (POWER) @ 70 MHz Full II 23 24 25 dBG ..
AD6633BBCZ ,Multi-channel Digital Upconverter with VersaCREST™ Crest Reduction EngineOVERVIEW An all-pass phase equalizer, designed to comply with IS-95, including cdma2000 standards, ..
AD6635BB ,4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP)APPLICATIONS8 Independent Digital Receivers in a Single PackageMulticarrier, Multimode Digital Rece ..
ADC0816CCN ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0816CCN/NOPB ,8-Bit Microprocessor Compatible A/D Converterwith 16-Channel Multiplexer 40-PDIP -40 to 85features a highimpedance chopper stabilized comparator, a 256R• 0V to 5V analog input voltage range ..
ADC0816CJ ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0817CCN ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel MultiplexerFeaturesn Easy interface to all microprocessorsThe ADC0816, ADC0817 data acquisition component is a ..
ADC0819BCV ,8-Bit Serial I/O A/D Converter with 19-Channel MultiplexerADC08198-BitSerialI/OA/DConverterwith19-ChannelMultiplexerDecember1994ADC08198-BitSerialI/OA/DConve ..
ADC0819BCVX ,8-Bit Serial I/O A/D Converter with 19-Channel MultiplexerADC08198-BitSerialI/OA/DConverterwith19-ChannelMultiplexerDecember1994ADC08198-BitSerialI/OA/DConve ..
AD6624AABC
Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
REV.0
The AD6624A is part of Analog Devices’ SoftCell® multicarrier
transceiver chipset designed for compatibility with Analog
Devices’ family of high sample rate IF sampling ADCs (AD6640/
AD6644 12- and 14-bit). The SoftCell receiver comprises a
digital receiver capable of digitizing an entire spectrum of
carriers and digitally selecting the carrier of interest for tuning
and channel selection. This architecture eliminates redundant
radios in wireless base station applications.
High dynamic range decimation filters offer a wide range of
decimation rates. The RAM-based architecture allows easy
reconfiguration for multimode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies less
bandwidth than the input signal, this rejection of out-of-band
noise is called “processing gain.” By using large decimation
factors, this “processing gain” can improve the SNR of the
ADC by 30 dB or more. In addition, the programmable RAM
coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The AD6624A is compatible with standard ADC converters such
as the AD664x, AD9042, AD943x and the AD922x families of
data converters. The AD6624A is also compatible with the
AD6600 Diversity ADC, providing a cost and size reduction path.
Four-Channel, 100 MSPS Digital
Receive Signal Processor (RSP)
FUNCTIONAL BLOCK DIAGRAM
EXPB[2:0]
FEATURES
100 MSPS Wideband Inputs (14 Linear Bits Plus 3 RSSI)
Dual High-Speed Data Input Ports
Four Independent Digital Receivers in Single Package
Digital Resampling for Noninteger Decimation Rates
Programmable Decimating FIR Filters
Programmable Attenuator Control for Clip Prevention
and External Gain Ranging via Level Indicator
Flexible Control for Multicarrier and Phased Array
3.3 V I/O, 2.5 V CMOS Core
User-Configurable Built-In Self-Test (BIST) Capability
JTAG Boundary Scan
APPLICATIONS
Multicarrier, Multimode Digital Receivers GSM, IS136,
EDGE, PHS, IS95
Micro and Pico Cell Systems
Wireless Local Loop
Smart Antenna Systems
Software Radios
In-Building Wireless Telephony
PRODUCT DESCRIPTIONThe AD6624A is a four-channel (quad) digital receive signal
processor (RSP) with four cascaded signal-processing elements:
a frequency translator, two fixed-coefficient decimating filters,
and a programmable-coefficient decimating filter.
SoftCell is a registered trademark of Analog Devices, Inc.
AD6624AFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . .1
SPECIFICATIONS/CHARACTERISTICS . . . . . . . . . . . . . . . .3
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . .9
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . .11
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
EXAMPLE FILTER RESPONSE . . . . . . . . . . . . . . . . . . . . . .14
INPUT DATA PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Gain Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Input Data Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Scaling with Fixed-Point ADCs . . . . . . . . . . . . . . . . . . . . . . .16
Scaling with Floating-Point or Gain-Ranging ADCs . . . . . . .16
NUMERICALLY CONTROLLED OSCILLATOR . . . . . . . .17
Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
NCO Frequency Hold-Off Register . . . . . . . . . . . . . . . . . . . .17
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Clear Phase Accumulator on HOP . . . . . . . . . . . . . . . . . . . . .17
Input Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Mode 00:Blank On IEN Low . . . . . . . . . . . . . . . . . . . . . . . .17
Mode 01:Clock On IEN High . . . . . . . . . . . . . . . . . . . . . . .18
Mode 10:Clock on IEN Transition to High . . . . . . . . . . . . .18
Mode 11: Clock on IEN Transition to Low . . . . . . . . . . . . . .18
WB Input Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Sync Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
SECOND ORDER rCIC FILTER . . . . . . . . . . . . . . . . . . . . . .18
rCIC2 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Example Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Decimation and Interpolation Registers . . . . . . . . . . . . . . . . .19
rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
FIFTH ORDER CASCADED INTEGRATOR COMB
FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
CIC5 Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . . . .20
RCF Decimation Register . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RCF Decimation Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RCF Filter Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RCF Output Scale Factor and Control Register . . . . . . . . . .21
USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST) . .22
RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
CHANNEL BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
CHIP SYNCHRONIZATION . . . . . . . . . . . . . . . . . . . . . . . . .22
Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Hop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
SERIAL OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . .24
Serial Output Data Format . . . . . . . . . . . . . . . . . . . . . . . . . .24
Compact Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . .24
Serial Data Frame (Serial Bus Master) . . . . . . . . . . . . . . . . . .24
Serial Data Frame (Serial Cascade) . . . . . . . . . . . . . . . . . . . .25
Configuring the Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . .25
Serial Port Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Serial Port to DSP Interconnection . . . . . . . . . . . . . . . . . . . .25
Serial Slave Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Ports Cascaded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Serial Output Frame Timing (Master and Slave) . . . . . . . . . .26
Serial Port Timing Specifications . . . . . . . . . . . . . . . . . . . . . .28
SBM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SDFS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SDFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Serial Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SDFS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Mapping RCF Data to the BIST Registers . . . . . . . . . . . . . .30
0x00–0x7F:Coefficient Memory (CMEM) . . . . . . . . . . . . . .30
0x80:Channel Sleep Register . . . . . . . . . . . . . . . . . . . . . . . .30
0x81:Soft_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . . .30
0x82: Pin_SYNC Register . . . . . . . . . . . . . . . . . . . . . . . . . . .30
0x83:Start Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . . . .30
0x84:NCO Frequency Hold-Off Counter . . . . . . . . . . . . . .30
0x85:NCO Frequency Register 0 . . . . . . . . . . . . . . . . . . . . .30
0x86:NCO Frequency Register 1 . . . . . . . . . . . . . . . . . . . . .30
0x87:NCO Phase Offset Register . . . . . . . . . . . . . . . . . . . . .30
0x88:NCO Control Register . . . . . . . . . . . . . . . . . . . . . . . . .30
0x90:rCIC2 Decimation – 1 (MrCIC2–1) . . . . . . . . . . . . . . . .31
0x91:rCIC2 Interpolation – 1 (LrCIC2–1) . . . . . . . . . . . . . . .31
0x92:rCIC2 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
0x93: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
0x94:CIC5 Decimation – 1 (MCIC5–1) . . . . . . . . . . . . . . . . .31
0x95:CIC5 Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
0x96: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
0xA0: RCF Decimation – 1 (MRCF–1) . . . . . . . . . . . . . . . . . .31
0xA1:RCF Decimation Phase (PRCF) . . . . . . . . . . . . . . . . . .31
0xA2:RCF Number of Taps Minus One (NRCF-1) . . . . . . . .31
0xA3:RCF Coefficient Offset (CORCF) . . . . . . . . . . . . . . . . .31
0xA4:RCF Control Register . . . . . . . . . . . . . . . . . . . . . . . . .31
0xA5:BIST Register for I . . . . . . . . . . . . . . . . . . . . . . . . . . .32
0xA6:BIST Register for Q . . . . . . . . . . . . . . . . . . . . . . . . . .32
0xA7:BIST Control Register . . . . . . . . . . . . . . . . . . . . . . . .32
0xA8:RAM BIST Control Register . . . . . . . . . . . . . . . . . . .32
0xA9:Serial Port Control Register . . . . . . . . . . . . . . . . . . . .32
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . .33
External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Access Control Register (ACR) . . . . . . . . . . . . . . . . . . . . . . .33
External Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Channel Address Register (CAR) . . . . . . . . . . . . . . . . . . . . . .34
SOFT_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . . .34
PIN_SYNC Control Register . . . . . . . . . . . . . . . . . . . . . . . . .34
SLEEP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Data Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Write Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Read Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Read/Write Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . . . .35
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . . . .35
Input Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . .35
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . .36
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . . . .36
INTERNAL WRITE ACCESS . . . . . . . . . . . . . . . . . . . . . . . . .37
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
INTERNAL READ ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . .38
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
TABLE OF CONTENTS
AD6624A
SPECIFICATIONS(VDD = 2.5 V � 5%, VDDIO = 3.3 V � 10%. All specifications TA = TMIN to TMAX, unless otherwise noted.)
ELECTRICAL CHARACTERISTICSLOGIC OUTPUTS
POWER DISSIPATION
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS
AD6624A
GENERAL TIMING CHARACTERISTICS1, 2Input Wideband Data Timing Requirements:
tSI
NOTESAll Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.CLOAD = 40 pF on all outputs unless otherwise specified.The timing parameters for SCLK, SDFS, SDFE, SDO, SDI, and DR apply to all four channels (0, 1, 2, and 3). The slave serial port’s (SCLK) operating frequency is
limited to 62.5 MHz.
Specifications subject to change without notice.
MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2tSC
tHC
tHWR
tSAM
tHAM
tDRDY
tHC
tSAM
tHAM
tDRDY
tSC
tHC
tHDS
tHRW
tHAM
tHC
tSAM
tHAM
tZD
NOTESAll Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.CLOAD = 40 pF on all outputs unless otherwise specified.Specification pertains to control signals: RW, (WR), DS, (RD), CS.
Specifications subject to change without notice.
AD6624A
TIMING DIAGRAMSFigure 1.Level Indicator Output Switching
Characteristics
Figure 2.RESET Timing Requirements
Figure 3.Input Data Timing Requirements
Figure 4.SCLK Switching Characteristics (Divide by 1)
Figure 5.SCLK Switching Characteristic (Divide by 2 or
EVEN Integer)
Figure 6.SCLK Switching Characteristic (Divide by 3 or
ODD Integer)
Figure 7.Serial Port Switching Characteristics
Figure 8.SDO, SDFE Switching Characteristics
Figure 9.CLK, DR Switching Characteristics
Figure 10.SCLK, DR Switching Characteristics
Figure 11.SDFS Timing Requirements (SBM = 0)
Figure 12.Input Timing for A and B Channels
Figure 13.SYNC Timing Inputs
AD6624A
TIMING DIAGRAMS—INM MICROPORT MODEFigure 14.INM Microport Write Timing Requirements
Figure 15.INM Microport Read Timing Requirements
TIMING DIAGRAMS—MNM MICROPORT MODEFigure 16.MNM Microport Write Timing Requirements
Figure 17.MNM Microport Read Timing Requirements
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Input Voltage . . . . . . . . . . . . –0.3 V to +5.3 V (5 V Tolerant)
Output Voltage Swing . . . . . . . . . . –0.3 V to VDDIO + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . .280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Thermal Characteristics196-Lead Ball Grid Array:
θJA = 26.3°C/W, No Airflow
θJA = 22°C/W, 200 LFPM Airflow
Thermal measurements made in the horizontal position on
a 4-layer board.
EXPLANATION OF TEST LEVELS100% Production Tested.
II.100% Production Tested at 25°C, and Sample Tested at
Specified Temperatures.
III.Sample Tested Only.
IV.Parameter Guaranteed by Design and Analysis.Parameter is Typical Value Only.
VI.100% Production Tested at 25°C, and Sample Tested at
Temperature Extremes.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6624A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD6624A
PIN CONFIGURATION
(Top View)
PIN FUNCTION DESCRIPTIONS 196-LEAD BGA
INPUTS
CONTROL
MICROPORT CONTROLDTACK (RDY)
AD6624A
PIN FUNCTION DESCRIPTIONS 196-LEAD BGA (continued)
OUTPUT
JTAG and BISTNOTESPins with a pull-down resistor of nominal 70 kΩ.Pins with a pull-up resistors of nominal 70 kΩ.
ARCHITECTUREThe AD6624A has four signal processing stages: a Frequency
Translator, second order Resampling Cascaded Integrator
Comb FIR filters (rCIC2), a fifth order Cascaded Integrator
Comb FIR filter (CIC5) and a RAM Coefficient FIR filter
(RCF). Multiple modes are supported for clocking data into and
out of the chip, and provide flexibility for interfacing to a wide
variety of digitizers. Programming and control is accomplished
via serial and microprocessor interfaces.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into in-phase (I) and quadrature (Q)
components. This stage translates the input signal from a digital
intermediate frequency (IF) to digital baseband. Phase and
amplitude dither may be enabled on-chip to improve spurious
performance of the NCO. A phase-offset word is available to
create a known phase relationship between multiple AD6624s or
between channels.
Following frequency translation is a resampling, fixed-coefficient,
high-speed, second order, Resampling Cascade Integrator
Comb (rCIC2) filter that reduces the sample rate based on the
ratio between the decimation and interpolation registers.
The next stage is a fifth order Cascaded Integrator Comb (CIC5)
filter whose response is defined by the decimation rate. The
purpose of these filters is to reduce the data rate to the final
filter stage so it can calculate more taps per output.
The final stage is a sum-of-products FIR filter with program-
mable 20-bit coefficients, and decimation rates programmable
from 1 to 256 (1–32 in practice). The RAM Coefficient FIR
filter (RCF in the Functional Block Diagram) can handle a
maximum of 160 taps.
The overall filter response for the AD6624A is the composite of
all decimating and interpolating stages. Each successive filter
stage is capable of narrower transition bandwidths but requires
a greater number of CLK cycles to calculate the output. More
decimation in the first filter stage will minimize overall power
consumption. Data from the chip is interfaced to the DSP via a
high-speed synchronous serial port.
Figure 18a illustrates the basic function of the AD6624A: to
select and filter a single channel from a wide input spectrum.
The frequency translator “tunes” the desired carrier to baseband.
Figure 18b shows the combined filter response of the rCIC2,
CIC5, and RCF.
Figure 18a.Frequency Translation of Wideband Input Spectrum
AD6624A
EXAMPLE FILTER RESPONSEThe filter in Figure 19 is based on a 65 MSPS input data rate
and an output rate of 541.6666 kSPS (two samples per symbol
for EDGE). Total decimation rate is 120 distributed between
the rCIC2, CIC5 and RCF.
Figure 19.Filter Response
The filter in Figure 20 is designed to meet the IS-136 specifica-
tions. For this configuration, the clock is set to 61.44 MSPS
with a total decimation rate of 320 providing an output data
rate of 192 kSPS or four samples per symbol.
Figure 20.Filter Response
INPUT DATA PORTSThe AD6624A features dual, high-speed ADC input ports, Input
Port A and Input Port B. The dual input ports allow for the
most flexibility with a single tuner chip. These can be diversity
inputs or truly independent inputs such as separate antenna
segments. Either ADC port can be routed to one of four tuner
channels. For added flexibility, each input port can be used to
support multiplexed inputs such as found on the AD6600 or
other ADCs with mixed outputs. This added flexibility can
allow for up to four different analog sources to be processed
simultaneously by the four internal channels.
that offers minimal latency and maximum flexibility to control
up to four analog signal paths. The overall signal path latency
from input to output on the AD6624A can be expressed in high-
speed clock cycles. The equation below can be used to calculate
MrC1C2 and MCIC5 are decimation values for the rC1C2 and
CIC5 filters respectively, NTAPS is the number RCF taps chosen,
and SDIV is the chosen SCLK divisor factor.
Input Data FormatEach input port consists of a 14-bit mantissa and 3-bit exponent. If
interfacing to a standard ADC is required, the exponent bits can
be grounded. If connected to a floating point ADC such as the
AD6600, the exponent bits from that product can be connected
to the input exponent bits of the AD6624A. The mantissa data
format is two’s-complement and the exponent is unsigned binary.
Input TimingThe data from each high-speed input port is latched on the
rising edge of CLK. This clock signal is used to sample the
input port and clock the synchronous signal processing stages
that follow in the selected channels.
The clock signals can operate up to 80 MHz and have a 50% duty
cycle. In applications using high-speed ADCs, the ADC sample
clock or data valid strobe is typically used to clock the AD6624A.
Figure 21.Input Data Timing Requirements
Figure 22.CLK Timing Requirements
Input Enable ControlThere is an IENA and an IENB pin for the Input Port A and
Input Port B respectively. There are four modes of operation
used for each IEN pin. Using these modes, it is possible to
emulate operation of the other RSPs such as the AD6620, which
offer dual channel modes normally associated with diversity
operations. These modes are: IEN transition to low, IEN transi-
tion to high, IEN high, and blank on IEN low.
In the IEN high mode, the inputs and normal operations occur
when the Input Enable is high. In the IEN transition to low
mode, normal operations occur on the first rising edge of the
clock after the IEN transitions to low. Likewise, in the IEN
transition to high mode, operations occur on the rising edge of
the clock after the IEN transitions to high. See the Numerically
A typical application for this feature would be to take the data
from an AD6600 Diversity ADC to one of the inputs of the
AD6624A. The A/B_OUT from that chip would be tied to the
IEN. One channel within the AD6624A would be then set so
that IEN transition to low is enabled. Another channel would be
configured so that IEN transition to high is enabled. One of the
serial outputs would be configured as the Serial Bus Master and
the other as a serial bus slave and the output bus configured as
shown in Figure 25. This would allow two of the AD6624A
channels to be configured to emulate that AD6620 in diversity
mode. Of course the NCO frequencies and other channel char-
acteristics would need to be set similarly, but this feature allows
the AD6624A to handle interleaved data streams such as found
on the AD6600.
The difference between the IEN transition to high and the IEN
high is found when a system clock is provided that is higher than
the data rate of the converter. It is often advantageous to supply
a clock that runs faster than the data rate so that additional filter
taps can be computed. This naturally provides better filtering.
In order to ensure that other parts of the circuit properly recog-
nize the faster clock in the simplest manner, the IEN transition
to low or high should be used. In this mode, only the first clock
edge that meets the setup and hold times will be used to latch
and process the input data. All other clock pulses are ignored by
front end processing. However, each clock cycle will still pro-
duce a new filter computation pair.
Gain SwitchingThe AD6624A includes circuitry that is useful in applications
where either large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresh-
olds to be set such that an upper and a lower threshold can
be programmed.
One such use of this may be to detect when an ADC converter
is about to reach full-scale with a particular input condition.
The result would be to provide a flag that could be used to
quickly insert an attenuator that would prevent ADC overdrive.
If 18 dB (or any arbitrary value) of attenuation (or gain) is
switched in, the signal dynamic range of the system will have
been increased by 18 dB. The process begins when the input
signal reaches the upper programmed threshold. In a typical
application, this may be set 1 dB (user-definable) below full-
scale. When this input condition is met, the appropriate LI
(LIA-A, LIA-B, LIB-A, or LIB-B) signal associated with either
the A or B input port is made active. This can be used to switch
the gain or attenuation of the external circuit. The LI signal stays
active until the input condition falls below the lower programmed
threshold. To provide hysteresis, a dwell-time register (see
Memory Map for Input Control Registers) is available to hold
off switching of the control line for a predetermined number of
clocks. Once the input condition is below the lower thresh-
old, the programmable counter begins counting high-speed
clocks. As long as the input signal stays below the lower thresh-
old for the number of high-speed clock cycles programmed, the
attenuator will be removed on the terminal count. However, if
the input condition goes above the lower threshold with the
counter running, it will be reset and must fall below the lower
threshold again to initiate the process. This will prevent unnec-
This is illustrated in Figure 23. When the input signal goes
above the upper threshold, the appropriate LI signal becomes
active. Once the signal falls below the lower threshold, the
counter begins counting. If the input condition goes above the
lower threshold, the counter is reset and starts again as shown
in Figure 23. Once the counter has terminated to zero, the LI
signal goes inactive.
Figure 23.Threshold Settings for LI
The LI signal can be used for a variety of functions. It can be
used to set the controls of an attenuator DVGA or integrated and
used with an analog VGA. To simplify the use of this feature,
the AD6624A includes two separate gain settings, one when this
line is inactive (rCIC2_QUIET[4:0]) and the other when active
(rCIC2_LOUD[4:0]). This allows the digital gain to be adjusted
to the external changes. In conjunction with the gain setting, a
variable hold-off is included to compensate for the pipeline delay of
the ADC and the switching time of the gain control element.
Together, these two features provide seamless gain switching.
Another use of these pins is to facilitate a gain range hold-off within
a gain-ranging ADC. For converters that use gain ranging to
increase total signal dynamic range, it may be desirable to pro-
hibit internal gain ranging from occurring in some instances.
For such converters, the LI (A or B) signals can be used to hold
this off. For this application, the upper threshold would be set
based on similar criteria. However, the lower threshold would
be set to a level consistent with the gain ranges of the specific
converter. The hold-off delay can then be set appropriately for
any number of factors such as fading profile, signal peak to
average ratio, or any other time-based characteristics that might
cause unnecessary gain changes.
Since the AD6624A has a total of four gain control circuits that
can be used if both A and B Input Ports have interleaved data,
each respective LI pin is independent and can be set to different
set points. It should be noted that the gain control circuits are
wideband and are implemented prior to any filtering elements to
minimize loop delay. Any of the four channels can be set to
monitor any of the possible four input channels (two in normal
mode and four when the inputs are time-multiplexed).
The chip also provides appropriate scaling of the internal data
based on the attenuation associated with the LI signal. In this
manner, data to the DSP maintains a correct scale value through-
out the process, making it totally independent. Since finite
delays are often associated with external gain switching compo-
nents, the AD6624A includes a variable pipeline delay that can
be used to compensate for external pipeline delays or gross
settling times associated with gain/attenuator devices. This delay
AD6624AThe RSSI output of the AD6600 numerically grows with increasing
signal strength of the analog input (RSSI = 5 for a large signal,
RSSI = 0 for a small signal). When the Exponent Invert Bit
(ExpInv) is set to zero, the AD6624A will consider the smallest
signal at the IN[13:0] to be the largest and as the EXP word
increases, it shifts the data down internally (EXP = 5 will shift a
14-bit word right by five internal bits before passing the data to
the rCIC2). In this example, where ExpInv = 0, the AD6624A
regards the largest signal possible on the AD6600 as the smallest
signal. Thus, the Exponent Invert Bit can be used to make the
AD6624A exponent agree with the AD6600 RSSI. By setting
ExpInv = 1, it forces the AD6624A to shift the data up (left) for
growing EXP instead of down. The exponent invert bit should
always be set high for use with the AD6600.
The Exponent Offset is used to shift the data right. For example,
Table I shows that with no rCIC2 scaling, 12 dB of range is lost
when the ADC input is at the largest level. This is undesirable
because it lowers the Dynamic Range and SNR of the system by
reducing the signal of interest relative to the quantization noise floor.
Table I.AD6600 Transfer Function with AD6624A ExpInv = 1,
and No ExpOff(ExpInv = 1, ExpOff = 0)
To avoid this automatic attenuation of the full-scale ADC
signal, the ExpOff is used to move the largest signal (RSSI = 5)
up to the point where there is no downshift. In other words,
once the Exponent Invert bit has been set, the Exponent Offset
should be adjusted so that mod(7–5 + ExpOff,8) = 0. This is
the case when Exponent Offset is set to 6 since mod(8,8) = 0.
Table II illustrates the use of ExpInv and ExpOff when used
with the AD6600 ADC.
Table II. AD6600 Transfer Function with AD6624A ExpInv = 1,
and ExpOff = 6(ExpInv = 1, ExpOff = 6)
This flexibility in handling the exponent allows the AD6624A
to interface with gain-ranging ADCs other than the AD6600.
The Exponent Offset can be adjusted to allow up to seven
RSSI(EXP) ranges to be used as opposed to the AD6600’s five.
Input Data ScalingThe AD6624A has two data input ports: an A Input Port and a
B Input Port. Each accepts 14-bit mantissa (two’s-complement
integer) IN[13:0], a 3-bit exponent (unsigned integer) EXP[2:0]
and the Input Enable (IEN). Both inputs are clocked by CLK.
These pins allow direct interfacing to both standard fixed-point
ADCs such as the AD9225 and AD6640, as well as to gain-
ranging ADCs such as the AD6600. For normal operation with
ADCs having fewer than 14 bits, the active bits should be MSB-
justified and the unused LSBs should be tied low.
The 3-bit exponent, EXP[2:0], is interpreted as an unsigned
integer. The exponent will subsequently be modified by either of
the 5-bit scale values stored in register 0x92, Bits 4–0 or Bits 9–5.
These 5-bit registers contain the sum of the rCIC2 scale value plus
the external attenuator scale settings and the Exponent Offset
(ExpOff). If no external attenuator is used, these values can only
be set to the value of the rCIC2 scale. If an external attenuator is
used, Bit Position 4–0 (Register 0x92 rCIC2_LOUD[4:0]) con-
tains the scale value for the largest input range. Bit Positions
9–5 (Register 0x92 rCIC2_QUIET[4:0]) are used for the nonat-
tenuated input signal range.
Scaling with Fixed-Point ADCsFor fixed-point ADCs, the AD6624A exponent inputs EXP[2:0]
are typically not used and should be tied low. The ADC outputs
are tied directly to the AD6624A Inputs, MSB-justified. The
ExpOff bits in 0x92 should be programmed to 0. Likewise, the
Exponent Invert bit should be 0.
Thus for fixed-point ADCs, the exponents are typically static
and no input scaling is used in the AD6624A.
Figure 24.Typical Interconnection of the AD6640 Fixed
Point ADC and the AD6624A
Scaling with Floating-Point or Gain-Ranging ADCsAn example of the exponent control feature combines the AD6600
and the AD6624A. The AD6600 is an 11-bit ADC with three bits
of gain ranging. In effect, the 11-bit ADC provides the mantissa,
and the three bits of relative signal strength indicator (RSSI) for
the exponent. Only five of the eight available steps are used by
the AD6600. See the AD6600 data sheet for additional details.
For gain-ranging ADCs such as the AD6600,
(1)
It also allows the AD6624A to be tailored in a system that employs
the AD6600, but does not utilize all of its signal range. For
example, if only the first four RSSI ranges are expected to occur,
the ExpOff could be adjusted to five, which would then make
RSSI = 4 correspond to the 0 dB point of the AD6624A.
Figure 25. Typical Interconnection of the AD6600 Gain-
Ranging ADC and the AD6624A
NUMERICALLY CONTROLLED OSCILLATOR
Frequency TranslationThis processing stage comprises a digital tuner consisting of two
multipliers and a 32-bit complex NCO. Each channel of the
AD6624A has an independent NCO. The NCO serves as a
quadrature local oscillator capable of producing an NCO frequency
between –CLK/2 and +CLK/2 with a resolution of CLK/232 in the
complex mode. The worst-case spurious signal from the NCO is
better than –100 dBc for all output frequencies.
The NCO frequency value in registers 0x85 and 0x86 are inter-
preted as a 32-bit unsigned integer. The NCO frequency is
calculated using the equation below.(2)
NCO_FREQ is the 32-bit integer (Registers 0x85 and 0x86),
fCHANNEL is the desired channel frequency, and
CLK* is the AD6624A master clock rate (CLK).
NCO Frequency Hold-Off RegisterWhen the NCO Frequency registers are written, data is actually
passed to a shadow register. Data may be moved to the main
registers by one of two methods. The first is to start the chip
using the soft sync feature, which will directly load the NCO
registers. The second allows changes to be pre-written and then
updated through direct software control. To accomplish this,
there is an NCO Frequency Hold-Off Counter. The counter
(0x84) is a 16-bit unsigned integer and is clocked at the master
CLK rate. This hold-off counter is also used in conjunction with
the frequency hopping feature of this chip.
Phase OffsetThe phase offset register (0x87) adds an offset to the phase
accumulator of the NCO. This is a 16-bit register and is inter-
preted as a 16-bit unsigned integer. A 0x0000 in this register
corresponds to a 0 radian offset and a 0xFFFF corresponds to16
NCO Control RegisterThe NCO control register located at 0x88 is used to configure
the features of the NCO. These are controlled on a per-channel
basis. These are described below.
BypassThe NCO in the front end of the AD6624A can be bypassed.
Bypass mode is enabled by setting Bit 0 of 0x88 high. When
they are bypassed, down conversion is not performed and the
AD6624A channel functions simply as a real filter on complex
data. This is useful for passband sampling application where the
A input is connected to the I signal path within the filter and the
B input is connected to the Q signal path. This may be desired if
the digitized signal has already been converted to passband in
prior analog stages or by other digital preprocessing.
Phase DitherThe AD6624A provides a phase dither option for improving the
spurious performance of the NCO. Phase dither is enabled by
setting Bit 1. When phase dither is enabled by setting this bit
high, spurs due to phase truncation in the NCO are randomized.
The energy from these spurs is spread into the noise floor and
Spurious Free Dynamic Range is increased at the expense of
very slight decreases in the SNR. The choice of whether phase
dither is used in a system will ultimately be decided by the system
goals. If lower spurs are desired at the expense of a slightly raised
noise floor, it should be employed. If a low noise floor is desired
and the higher spurs can be tolerated or filtered by subsequent
stages, phase dither is not needed.
Amplitude DitherAmplitude dither can also be used to improve spurious perfor-
mance of the NCO. Amplitude dither is enabled by setting Bit 2.
Amplitude dither improves performance by randomizing the
amplitude quantization errors within the angular to Cartesian
conversion of the NCO. This option may reduce spurs at the
expense of a slightly raised noise floor. Amplitude dither and
phase dither can be used together, separately, or not at all.
Clear Phase Accumulator on HOPWhen Bit 3 is set, the NCO phase accumulator is cleared prior
to a frequency hop. This ensures a consistent phase of the NCO
on each hop. The NCO phase offset is unaffected by this setting
and is still in effect. If phase-continuous hopping is desired, this
bit should be cleared and the last phase in the NCO phase regis-
ter will be the initiating point for the new frequency.
Input Enable ControlThere are four different modes of operation for the input enable.
Each of the high-speed input ports includes an IEN line. Any of
the four filter channels can be programmed to take data from
either of the two A or B Input Ports (see WB Input Select section).
Along with data is the IEN(A, B) signal. Each filter channel can
be configured to process the IEN signal in one of four modes.
Three of the modes are associated with when data is processed
based on a time division multiplexed data stream. The fourth
mode is used in applications that employ time division duplex
such as radar, sonar, ultrasound, and communications that
involve TDD.
Mode 00:Blank On IEN LowIn this mode, data is blanked while the IEN line is low. During the
AD6624Alowered, input data is replaced with zero values. During this
period, the NCO continues to run such that when the IEN line
is raised again, the NCO value will be at the value it would have
otherwise been in had the IEN line never been lowered. This
mode has the effect of blanking the digital inputs when the IEN
line is lowered. Back end processing (rCIC2, CIC5, and RCF)
continues while the IEN line is high. This mode is useful for
time division multiplexed applications.
Mode 01:Clock On IEN HighIn this mode, data is clocked into the chip while the IEN line is
high. During the period of time when the IEN line is high, new
data is strobed on each rising edge of the input clock. When
IEN line is lowered, input data is no longer latched into the
channel. Additionally, NCO advances are halted. However,
back end processing (rCIC2, CIC5, and RCF) continues during
this period. The primary use for this mode is to allow for a clock
that is faster than the input sample data rate to allow more filter
taps to be computed than would otherwise be possible. In Fig-
ure 26, input data is strobed only during the period of time when
IEN is high, despite the fact that the CLK continues to run at a
rate four times faster than the data.
Figure 26.Fractional Rate Input Timing (4× CLK) in
Mode 01
Mode 10:Clock on IEN Transition to HighIn this mode, data is clocked into the chip only on the first clock
edge after the rising transition of the IEN line. Although data is
only latched on the first valid clock edge, the back end process-
ing (rCIC2, CIC5, and RCF) continues on each available clock
that may be present, similar to Mode 01. The NCO phase accu-
mulator is incremented only once for each new input data sample
and not once for each input clock.
Mode 11: Clock on IEN Transition to LowIn this mode, data is clocked into the chip only on the first clock
edge after the falling transition of the IEN line. Although data is
only latched on the first valid clock edge, the back end process-
ing (rCIC2, CIC5, and RCF) continues on each available clock
that may be present, similar to Mode 01. The NCO phase accu-
mulator is incremented only once for each new input data sample
and not once for each input clock.
WB Input SelectBit 6 in this register controls which input port is selected for
signal processing. If this bit is set high, Input Port B (INB,
EXPB, and IENB) is connected to the selected filter channel. If
this bit is cleared, Input Port A (INA, EXPA, and IENA) is
connected to the selected filter channel.
Sync SelectBits 7 and 8 of this register determine which external sync pin is
associated with the selected channel. The AD6624A has four sync
channels within the AD6624A. Additionally, if only one sync
signal is required for the system, all four receiver channels can
reference the same sync pulse. Bit value 00 is Channel A, 01 is
Channel B, 10 is Channel C, and 11 is Channel D.
SECOND ORDER rCIC FILTERThe rCIC2 filter is a second order cascaded resampling integra-
tor comb filter. The resampler is implemented using a unique
technique, which does not require the use of a high-speed clock,
thus simplifying the design and saving power. The resampler
allows for noninteger relationships between the master clock
and the output data rate. This allows easier implementation of
systems that are either multimode or require a master clock that
is not a multiple of the data rate to be used.
Interpolation up to 512, and decimation up to 4096, is allowed
in the rCIC2. The resampling factor for the rCIC2 (L) is a 9-bit
integer. When combined with the decimation factor M, a 12-bit
number, the total rate change can be any fraction in the form of:
(3)
The only constraint is that the ratio L/M must be less than or
equal to one. This implies that the rCIC2 decimates by 1 or more.
Resampling is implemented by apparently increasing the input
sample rate by the Factor L, using zero stuffing for the new data
samples. Following the resampler is a second order cascaded
integrator comb filter. Filter characteristics are determined only
by the fractional rate change (L/M).
The filter can process signals at the full rate of the input port
80 MHz. The output rate of this stage is given by Equation 4.(4)
Both LrCIC2 and MrCIC2 are unsigned integers. The interpolation
rate (LrCIC2) may be from 1 to 512 and the decimation (MrCIC2)
may be between 1 and 4096. The stage can be bypassed by
setting the decimation to 1/1.
The frequency response of the rCIC2 filter is given by Equation 5.
(5)
The scale factor, SrCIC2 is a programmable, unsigned 5-bit value
between 0 and 31. This serves as an attenuator that can reduce
the gain of the rCIC2 in 6 dB increments. For the best dynamic
range, SrCIC2 should be set to the smallest value possible (i.e.,
where input_level is the largest fraction of full-scale possible at
the input to the AD6624A (normally 1). The rCIC2 scale factor
is always used whether or not the rCIC2 is bypassed.
Moreover, there are two scale registers (rCIC2_LOUD[4:0]
Bits 4–0 in x92), and (rCIC2_QUIET[4:0] Bits 9–5 in 0x92)
that are used in conjunction with the computed SrCIC2 which
determines the overall rCIC2 scaling. The SrCIC2 value must
be summed with the values in each respective scale register and
ExpOff, to determine the scale value that must be placed in the
rCIC2 scale register. This number must be less than 32 or the
interpolation and decimation rates must be adjusted to validate
this equation. The ceil function denotes the next whole integer
and the floor function denotes the previous whole integer. For
example, the ceil(4.5) is 5 while the floor(4.5) is 4.
The gain and passband droop of the rCIC2 should be calculated
by the equations above, as well as the filter transfer equations that
follow. Excessive passband droop can be compensated for in the
RCF stage by peaking the passband by the inverse of the roll-off.(7)
where: IN is the value of IN[15:0], Exp is the value of EXP[2:0],
and rCIC2 is the value of the 0x92 (rCIC2_QUIET[4:0] and
rCIC2_LOUD[4:0]) scale register.
rCIC2 RejectionTable III illustrates the amount of bandwidth in percent of the
data rate into the rCIC2 stage. The data in this table may be
scaled to any other allowable sample rate up to 80 MHz in
Single Channel Mode or 40 MHz in Diversity Channel Mode.
The table can be used as a tool to decide how to distribute the
decimation between rCIC2, CIC5, and the RCF.
Table III.SSB rCIC2 Alias Rejection Table (fSAMP = 1)
Bandwidth Shown in Percentage of fSAMP
Example CalculationsGoal:Implement a filter with an Input Sample Rate of 10 MHz
requiring 100 dB of alias rejection for a ±7 kHz passband.
Solution: First determine the percentage of the sample rate that
is represented by the passband.(8)
Find the –100 dB column in Table III and look down this column
for a value greater than or equal to your passband percentage of
the clock rate. Then look across to the extreme left column and
find the corresponding rate-change factor (MrCIC2/LrCIC2). Refer-
ring to the table, notice that for a MrCIC2/LrCIC2 of 4, the frequency
having –100 dB of alias rejection is 0.071 percent, which is
slightly greater than the 0.07 percent calculated. Therefore, for
this example, the maximum bound on rCIC2 rate change is 4.
A higher chosen MrCIC2/LrCIC2 means less alias rejection than
the 100 dB required.
An MrCIC2/LrCIC2 of less than four would still yield the required
rejection; however, the power consumption can be minimized
by decimating as much as possible in this rCIC2 stage. Decima-
tion in rCIC2 lowers the data rate, and thus reduces power
consumed in subsequent stages. It should also be noted that
there is more than one way to determine the decimation by 4. A
decimation of 4 is the same as an L/M ratio of 0.25. Thus any
integer combination of L/M that yields 0.25 will work (1/4, 2/8,
or 4/16). However, for the best dynamic range, the simplest
ratio should be used. For example, 1/4 gives better performance
than 4/16.
Decimation and Interpolation RegistersrCIC2 decimation values are stored in register 0x90. This is a
12-bit register and contains the decimation portion less 1. The
interpolation portion is stored in register 0x91. This 9-bit value
holds the interpolation less one.
rCIC2 ScaleRegister 0x92 contains the scaling information for this section of
the circuit. The primary function is to store the scale value
computed in the sections above.
Bits 4–0 (rCIC2_LOUD[4:0]) of this register are used to con-
tain the scaling factor for the rCIC2 during conditions of strong
signals. These five bits represent the rCIC2 scalar calculated above
plus any external signal scaling with an attenuator.
Bits 9–5 (rCIC2_QUIET[4:0]) of this register are used to con-
tain the scaling factor for the rCIC2 during conditions of weak
signals. In this register, no external attenuator would be used
and is not included. Only the value computed above is stored in
these bits.
(6)
AD6624ABit 11 of this register is used to invert the external exponent
before internal calculation. This bit should be set HIGH for
gain-ranging ADCs that use an increasing exponent to represent
an increasing signal level. This bit should be set LOW for gain-
ranging ADCs that use a decreasing exponent for representing
an increasing signal level.
In applications that do not require the features of the rCIC2,
it may be bypassed by setting the L/M ratio to 1/1. This effectively
bypasses all circuitry of the rCIC2 except the scaling, which
is still effectual.
FIFTH ORDER CASCADED INTEGRATOR COMB FILTERThe third signal processing stage, CIC5, implements a sharper
fixed-coefficient, decimating filter than CIC2. The input rate to
this filter is fSAMP2. The maximum input rate is given by Equa-
tion 9. NCH equals two for Diversity Channel Real input mode;
otherwise NCH equals one. In order to satisfy this equation, MCIC2
can be increased, NCH can be reduced, or fCLK can be increased
(reference fractional rate input timing described in the Input
Timing section).(9)
The decimation ratio, MCIC5, may be programmed from 2 to 32
(all integer values). The frequency response of the filter is given
by Equation 10. The gain and passband droop of CIC5 should
be calculated by these equations. Both parameters may be com-
pensated for in the RCF stage.
(10)
The scale factor, SCIC5 is a programmable unsigned integer
between 0 and 20. It serves to control the attenuation of the
data into the CIC5 stage in 6 dB increments. For the best
dynamic range, SCIC5 should be set to the smallest value possible
(lowest attenuation) without creating an overflow condition.
This can be safely accomplished using Equation 11, where
OLrCIC2 is the largest fraction of full scale possible at the input
to this filter stage. This value is output from the rCIC2 stage,
then pipelined into the CIC5.
(11)
The output rate of this stage is given by Equation 12.
CIC5 RejectionTable IV illustrates the amount of bandwidth in percentage of
the clock rate that can be protected with various decimation
rates and alias rejection specifications. The maximum input rate
into the CIC5 is 80 MHz when the rC1C2 decimates by one.
As in Table III, these are the 1/2 bandwidth characteristics of
the CIC5. Note that the CIC5 stage can protect a much wider
band than the CIC2 for any given rejection.
Table IV.SSB CIC5 Alias Rejection Table (fSAMP2 = 1)This table helps to calculate an upper bound on decimation,
MCIC5, given the desired filter characteristics.
RAM COEFFICIENT FILTERThe final signal processing stage is a sum-of-products decimat-
ing filter with programmable coefficients (see Figure 27). The
data memories I-RAM and Q-RAM store the 160 most recent
complex samples from the previous filter stage with 20-bit
resolution. The coefficient memory, CMEM, stores up to 256
coefficients with 20-bit resolution. On every CLK cycle, one tap
for I and one tap for Q are calculated using the same coefficients.
The RCF output consists of 24-bit data bits.
