AD6623AS ,4-Channel, 104 MSPS Digital Transmit Signal Processor TSPCHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 External Address 6 Lower ..
AD6623AS ,4-Channel, 104 MSPS Digital Transmit Signal Processor TSPOVERVIEW OF THE RCF BLOCKS . . . . . . . . . . . . . . . . . . . . . . . . 16 (0xn07) CIC2 Decimati ..
AD6624AABC ,Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)CHARACTERISTICS . . . . . . . . . . . . . . . . 3 SBM0 . . . . . . . . . . . . . . . . . . . . . . ..
AD6624AS ,Four-channel, 80 MSPS digital receive signal processor (RSP)CHARACTERISTICS . . . . . . . . . . . . 4ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . ..
AD6630AR ,Differential, Low Noise IF Gain Block with Output Clampingspecifications are valid across the operating frequency range when the source and load impedance ar ..
AD6630AR ,Differential, Low Noise IF Gain Block with Output ClampingSPECIFICATIONSTest1Parameter Temp Level Min Typ Max UnitsGAIN (POWER) @ 70 MHz Full II 23 24 25 dBG ..
ADC0816CCJ ,8-Bit P Compatible A/D Converters with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0816CCN ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0816CCN/NOPB ,8-Bit Microprocessor Compatible A/D Converterwith 16-Channel Multiplexer 40-PDIP -40 to 85features a highimpedance chopper stabilized comparator, a 256R• 0V to 5V analog input voltage range ..
ADC0816CJ ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel Multiplexerfeatures a high impedance chopper stabilized comparator, an 0V to 5V analog input voltage range wit ..
ADC0817CCN ,8-Bit Microprocessor Compatible A/D Converter with 16-Channel MultiplexerFeaturesn Easy interface to all microprocessorsThe ADC0816, ADC0817 data acquisition component is a ..
ADC0819BCV ,8-Bit Serial I/O A/D Converter with 19-Channel MultiplexerADC08198-BitSerialI/OA/DConverterwith19-ChannelMultiplexerDecember1994ADC08198-BitSerialI/OA/DConve ..
AD6623AS
4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
REV.0
4-Channel, 104 MSPS Digital
Transmit Signal Processor (TSP)
FUNCTIONAL BLOCK DIAGRAMA[2:0]MODERWDTACKDSD[7:0]
QIN
OEN
QOUT
OUT
[17:0]
SDINA
SDFIA
SDFOA
SCLKA
SDINB
SDFIB
SDFOB
SCLKB
SDINC
SDFIC
SDFOC
SCLKC
SDIND
SDFID
SCLKD
SDFOD
CLKRESET
[17–0]
NCO = NUMERICALLY CONTROLLED
OSCILLATOR/TUNER
TDLTMSTCKTRSTTDO
FEATURES
Pin Compatible to the AD6622
18-Bit Parallel Digital IF Output
Real or Interleaved Complex
18-Bit Bidirectional Parallel Digital IF Input/Output
Allows Cascade of Chips for Additional Channels
Clipped or Wrapped Over Range
Two’s Complement or Offset Binary Output
Four Independent Digital Transmitters in Single Package
RAM Coefficient Filter (RCF)
Programmable IF and Modulation for Each Channel
Programmable Interpolating RAM Coefficient Filter
p/4-DQPSK Differential Phase Encoder
3p/8-PSK Linear Encoder
8-PSK Linear Encoder
Programmable GMSK Look-Up Table
Programmable QPSK Look-Up Table
All-Pass Phase Equalizer
Programmable Fine Scaler
Programmable Power Ramp Unit
High Speed CIC Interpolating Filter
Digital Resampling for Noninteger Interpolation Rates
NCO Frequency Translation
Spurious Performance Better than –100 dBc
Separate 3-Wire Serial Data Input for Each Channel
Bidirectional Serial Clocks and Frames
Microprocessor Control
2.5 V CMOS Core, 3.3 V Outputs, 5 V Inputs
JTAG Boundary Scan
APPLICATIONS
Cellular/PCS Base Stations
Micro/Pico Cell Base Stations
Wireless Local Loop Base Stations
Multicarrier, Multimode Digital Transmit
GSM, EDGE, IS136, PHS, IS95, TDS CDMA, UMTS,
CDMA2000
Phased Array Beam Forming Antennas
Software Defined Radio
Tuning Resolution Better than 0.025 Hz
Real or Complex Outputs
AD6623
TABLE OF CONTENTSFEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . .1
PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . .4
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . .4
LOGIC INPUTS (5 V TOLERANT) . . . . . . . . . . . . . . . . . . . . . . . . .4
LOGIC OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
IDD SUPPLY CURRENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
GENERAL TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . .5
MICROPROCESSOR PORT TIMING CHARACTERISTICS . . . . . . . .6
MICROPROCESSOR PORT, MODE INM (MODE = 0) . . . . . . . . .6
MICROPROCESSOR PORT, MOTOROLA (MODE = 1) . . . . . . . .6
TIMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7–9
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . .10
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . .10
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PIN CONFIGURATION – 128-Lead MQFP . . . . . . . . . . . . . . . . . . . .11
128 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . .12
PIN CONFIGURATION – 196-Lead BGA . . . . . . . . . . . . . . . . . . . . . .13
196 PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . .14
POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
JTAG AND BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
SERIAL DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Serial Master Mode (SCS = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Serial Slave Mode (SCS = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Self-Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
External Framing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Serial Port Cascade Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PROGRAMMABLE RAM COEFFICIENT FILTER (RCF) . . . . . . . . .16
OVERVIEW OF THE RCF BLOCKS . . . . . . . . . . . . . . . . . . . . . . . .16
INTERPOLATING FIR FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . .17
RCF CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PSK MODULATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
�/4-DQSPK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
8-PSK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
3�/8-8-PSK MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
MSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
GMSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
QPSK Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
PHASE EQUALIZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
SCALE AND RAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
FINE SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RCF POWER RAMPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CASCADED INTERGRATOR COMB (CIC)
INTERPOLATING FILTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
CIC Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
CIC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
rCIC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
NUMERICALLY CONTROLLED
OSCILLATOR/TUNER (NCO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Phase Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Amplitude Dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
NCO Frequency Update and Phase Offset Update
Hold-Off Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Start with No Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Start with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Start with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Hop with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Hop with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Beam with Soft Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Beam with Pin Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
JTAG INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
SCALING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Multicarrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Single Carrier Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MICROPORT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MicroPort Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EXTERNAL MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Intel Nonmultiplexed Mode (INM) . . . . . . . . . . . . . . . . . . . . . . . . . .30
Motorola Nonmultiplexed Mode (MNM) . . . . . . . . . . . . . . . . . . . . .30
External Address 7 Upper Address Register (UAR) . . . . . . . . . . . . . .30
External Address 6 Lower Address Register (LAR) . . . . . . . . . . . . . .30
External Address 5 Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
External Address 4 Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
External Address 3:0 (Data Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . .31
INTERNAL CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . . .31
AD6623 and AD6622 Compatibility
Common Function Registers (not associated
with a particular channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Channel Function Registers (0x1XX = Ch. A,
0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D) . . . . . . . . . . .31
(0x000) Summation Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . .33
(0x001) Sync Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
(0x002) BIST Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
(0x003) BIST Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Channel Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn00) Start Update Hold-Off Counter . . . . . . . . . . . . . . . . . . . . . .34
(0xn01) NCO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn02) NCO Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn03) NCO Frequency Update Hold-Off Counter . . . . . . . . . . . . .34
(0xn04) NCO Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn05) NCO Phase Offset Update Hold-Off Counter . . . . . . . . . . . .34
(0xn06) CIC Scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn07) CIC2 Decimation – 1 (MCIC2 – 1) . . . . . . . . . . . . . . . . . . . . .34
(0xn08) CIC2 Interpolation – 1 (LCIC2 – 1) . . . . . . . . . . . . . . . . . . . .34
(0xn09) CIC5 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn0A) Number of RCF Coefficients – 1 . . . . . . . . . . . . . . . . . . . . .34
(0xn0B) RCF Coefficient Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn0C) Channel Mode Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .34
(0xn0D) Channel Mode Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn0E) Fine Scale Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn0F) RCF Time Slot Hold-Off Counter . . . . . . . . . . . . . . . . . . . .35
(0xn10–0xn11) RCF Phase Equalizer Coefficients . . . . . . . . . . . . . . .35
(0xn12–0xn15) FIR-PSK Magnitudes . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn16) Serial Port Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn17) Power Ramp Length 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn18) Power Ramp Length 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn19) Power Ramp Rest Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn20–0xn1F) Unused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn20–0xn3F) Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
(0xn40–0xn17F) Power Ramp Coefficient Memory . . . . . . . . . . . . . .35
Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Write Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Read Pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
USING THE AD6623 TO PROCESS UMTS CARRIERS . . . . . . . .36
DIGITAL-TO-ANALOG CONVERTER (DAC) SELECTION . . . . . . .36
MULTIPLE TSP OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Determining the Number of TSPs to Use . . . . . . . . . . . . . . . . . . . .36
PRODUCT DESCRIPTIONThe AD6623 is a 4-channel Transmit Signal Processor (TSP)
that creates high bandwidth data for Transmit Digital-to-Analog
Converters (TxDACs) from baseband data provided by a Digital
Signal Processor (DSP). Modern TxDACs have achieved suffi-
ciently high sampling rates, analog bandwidth, and dynamic range
to create the first Intermediate Frequency (IF) directly. The
AD6623 synthesizes multicarrier and multistandard digital signals
to drive these TxDACs. The RAM-based architecture allows easy
reconfiguration for multimode applications. Modulation, pulse-
shaping and anti-imaging filters, static equalization, and tuning
functions are combined in a single, cost-effective device. Digital
IF signal processing provides repeatable manufacturing, higher
accuracy, and more flexibility than comparable high dynamic
range analog designs.
The AD6623 has four identical digital TSPs complete with synchro-
nization circuitry and cascadable wideband channel summation.
AD6623 is pin compatible to AD6622 and can operate in AD6622-
compatible control register mode.
The AD6623 utilizes a 3.3 V I/O power supply and a 2.5 V core
power supply. All I/O pins are 5 V tolerant. All control registers
and coefficient values are programmed through a generic micro-
processor interface. Intel and Motorola microprocessor bus modes
are supported. All inputs and outputs are LVCMOS compatible.
FUNCTIONAL OVERVIEWEach TSP has five cascaded signal processing elements: a pro-
grammable interpolating RAM Coefficient Filter (RCF), a
programmable Scale and Power Ramp, a programmable fifth order
Cascaded Integrator Comb (CIC5) interpolating filter, a flexible
second order Resampling Cascaded Integrator Comb filter (rCIC2),
and a Numerically Controlled Oscillator/Tuner (NCO).
The outputs of the four TSPs are summed and scaled on-chip.
In multicarrier wideband transmitters, a bidirectional bus allows
the Parallel (wideband) IF Input/Output to drive a second DAC.
In this operational mode two AD6623 channels drive one DAC
and the other two AD6623 channels drive a second DAC. Mul-
tiple AD6623s may be combined by driving the INOUT[17:0] of
the succeeding with the OUT[17:0] of the preceding chip. The
INOUT[17:0] can alternatively be masked off by software to
allow preceding AD6623’s outputs to be ignored.
Each channel accepts input data from independent serial ports
that may be connected directly to the serial port of Digital Signal
Processor (DSP) chips.
The RCF implements any one of the following functions:
Interpolating Finite Impulse Response (FIR) filter, �/4-DQPSK
modulator, 8-PSK modulator, or 3 �/8-8-PSK modulator, GMSK
modulator, and QPSK modulator. Each AD6623 channel can
be dynamically switched between the GMSK modulation mode
and the 3 �/8-8-PSK modulation mode in order to support the
GSM/EDGE standard. The RCF also implements an Allpass
Phase Equalizer (APE) which meets the requirements of IS-95-A/B
standard (CDMA transmission).
The programmable Scale and Power Ramp block allows power
ramping on a time-slot basis as specified for some air-interface
standards (e.g., GSM, EDGE). A fine scaling unit at the pro-
grammable FIR filter output allows an easy signal amplitude
level adjustment on time slot basis.
The CIC5 provides integer rate interpolation from 1 to 32 and
coarse anti-image filtering. The rCIC2 provides fractional rate
interpolation from 1 to 4096 in steps of 1/512. The wide range
of interpolation factors in each CIC filter stage and a highly
flexible resampler incorporated into rCIC2 makes the AD6623
useful for creating both narrowband and wideband carriers in a
high-speed sample stream.
The high resolution 32-bit NCO allows flexibility in frequency
planning and supports both digital and analog air interface stan-
dards. The high speed NCO tunes the interpolated complex signal
from the rCIC2 to an IF channel. The result may be real or com-
plex. Multicarrier phase synchronization pins and phase offset
registers allow intelligent management of the relative phase of
independent RF channels. This capability supports the require-
ments for phased array antenna architectures and management
of the wideband peak/power ratio to minimize clipping at the DAC.
The wideband Output Ports can deliver real or complex data.
Complex words are interleaved into real (I) and imaginary (Q)
parts at half the master clock rate.
AD6623
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS*This specification denotes an absolute maximum supply current for the device. The conditions include all channels active, minimum interpolation in both CIC
stages, and maximum switching of input data. In an actual application the power will be less.
See the Thermal Management section of the data sheet for further details.
AD6623
GENERAL TIMING CHARACTERISTICS1,2tCLKL
RESET Timing Requirement:
Input Data Timing Requirements:
tSI
Output Data Timing Characteristics:
tDO
SYNC Timing Requirements:
tSS
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics
tSSFI0
tHSFI0
tSSDI0
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics
tSCLKL
tSCLKH
tSSDH
tSSFI1
tHSFI1
tSSDI1
NOTES
AD6623
MICROPROCESSOR PORT TIMING CHARACTERISTICS1,2tSC
tHC
tHWR
tSAM
tHAM
tDRDY
tHC
tSAM
tHAM
tZOZ
tDD
tDRDY
tSC
tHC
tHDS
tHRW
tHAM
tDDTACK
tHC
tHDS
tSAM
tHAM
tZD
tDD
tDDTACK
NOTESAll Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.CLOAD = 40 pF on all outputs (unless otherwise specified).Specification pertains to control signals: RW, (WR), DS, (RD), CS.
Specifications subject to change without notice.
TIMING DIAGRAMSFigure 1.Parallel Output Switching Characteristics
Figure 2.Wideband Input Timing
Figure 3.SYNC Timing Inputs
Figure 4.RESET Timing Requirements
Figure 5.SCLK Switching Characteristics (Divide by 1)
Figure 6.SCLK Switching Characteristic (Divide by 2 or
EVEN Integer)
Figure 7.SCLK Switching Characteristic (Divide by 3 or ODD Integer)
AD6623Figure 8.Serial Port Timing, Master Mode (SCS = 0), Channel is Self-Framing
Figure 9.Serial Port Timing, Slave Mode (SCS = 1), Channel is Self-Framing
Figure 10.Serial Port Timing, Master Mode (SCS = 0), Channel is External-Framing
Figure 11.Serial Port Timing, Slave Mode (SCS = 1), Channel is External-Framing
TIMING DIAGRAMS—INM MICROPORT MODEFigure 12.INM Microport Write Timing Requirements
Figure 13.INM Microport Read Timing Requirements
TIMING DIAGRAMS—MNM MICROPORT MODEFigure 14.MNM Microport Write Timing Requirements
Figure 15.Motorola Microport Read Timing Requirements
AD6623
ORDERING GUIDEAD6623ABC
AD6623S/PCB
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Input Voltage . . . . . . . . . . . . . . –0.3 V to +5 V (5 V Tolerant)
Output Voltage Swing . . . . . . . . . . –0.3 V to VDDIO + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . . 280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the devices at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
THERMAL CHARACTERISTICS128-Lead MQFP:
�JA = 33°C/W, no airflow
�JA = 27°C/W, 200 lfpm airflow
�JA = 24°C/W, 400 lfpm airflow
196-Lead BGA:
�JA = 26.3°C/W, no airflow
�JA = 22°C/W, 200 lfpm airflow
Thermal measurements made in the horizontal position on a
2-layer board.
EXPLANATION OF TEST LEVELS100% Production Tested
II.100% Production Tested at 25°C, and Sample Tested at
Specified Temperatures
III.Sample Tested Only
IV.Parameter Guaranteed by Design and AnalysisParameter is Typical Value Only
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6623 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
128-Lead MQFPSDFIC
GND
SDFIB
SDFOB
SCLKB
SDINA
SDFOA
SCLKA
TDI
TDO
TMS
SDFIA
VDD
GND
VDDIO
VDD
DS(RD)
DTACK(RDY)
RW(WR)
GND
GND
GND
MODE
GNDTCKTRSTGNDGNDINOUT0GNDGNDINOUT1INOUT2INOUT3INOUT4VDDIOINOUT11INOUT12VDDIOINOUT13INOUT14INOUT15INOUT16SYNC3
GNDOENGNDGNDGND
OUT0OUT1
GND
OUT3OUT4OUT5OUT6
VDDIO
OUT7OUT8OUT9
OUT10
GNDGNDGND
OUT11OUT12OUT13OUT14VDDIOOUT15OUT16OUT17
QOUT
GND
GND
GND
GNDGNDGNDD7
OUT2
VDD
RESET
SYNC0
SYNC1
GND
GND
GNDINOUT17INOUT5INOUT6INOUT7INOUT8GNDGNDGNDINOUT9INOUT10
QINSYNC2GNDCLKVDDGND
GND
VDDIO
SDFID
SDIND
SDFOD
SCLKD
VDDIO
SDINC
SDFOC
SDINB
SCLKC
VDD
GND
AD6623
128 PIN FUNCTION DESCRIPTIONS29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15,
13, 12, 11, 10, 8, 7, 6
47, 59, 66, 104, 127
14, 26, 41, 78, 90, 110, 122
33, 37, 40, 43, 44, 45, 46, 48
56, 57, 58
125
PIN CONFIGURATION
196-Lead BGA
AD6623
196-PIN FUNCTION DESCRIPTIONS
POWER SUPPLY
INPUTS
CONTROL
MICROPORT CONTROLDTACK (RDY)
OUTPUTS
JTAG AND BISTNOTESPins with a Pull-Down resistor of nominal 70 kΩ.
SERIAL DATA PORTThe AD6623 has four independent Serial Ports (A, B, C, and D),
and each accepts data to its own channel (A, B, C, or D) of the
device. Each Serial Port has four pins: SCLK (Serial CLocK), SDFO
(Serial Data Frame Out), SDFI (Serial Data Frame In), and SDIN
(Serial Data INput). SDFI and SDIN are inputs, SDFO is an output,
and SCLK is either input or output depending on the state of SCS
(Serial Clock Slave: 0xn16, Bit 4). Each channel can be operated
either as a Master or Slave channel depending upon SCS. The Serial
Port can be self-framing or accept external framing from the SFDI
pin or from the previous adjacent channel (0xn16, Bits 7 and 6).
Serial Master Mode (SCS = 0)In master mode, SCLK is created by a programmable internal
counter that divides CLK. When the channel is “sleeping,” SCLK
is held low. SCLK becomes active on the first rising edge of CLK
after Channel sleep is removed (D0 through D3 of external
address 4). Once active, the SCLK frequency is determined by
the CLK frequency and the SCLK divider, according to the
equations below.
AD6623 mode:(1)
AD6622 mode:(2)
The SCLK divider is a 5-bit unsigned value located at Internal
Channel Address 0xn0D (Bits 4–0), where “n” is 1, 2, 3, or 4 for
the chosen channel A, B, C, or D, respectively. The user must
select the SCLK divider to insure that SCLK is fast enough to
accept full input sample words at the input sample rate. See the
design example at the end of this section. The maximum SCLK
frequency is equal to the CLK when operating in AD6623 mode
serial clock master. When operating in AD6622 compatible mode,
the maximum SCLK frequency is one-half the CLK. The minimum
SCLK frequency is 1/32 of the CLK frequency in AD6623 mode
or 1/64 of the CLK frequency when in AD6622 mode. SDFO
changes on the positive edge of SCLK when in master mode. SDIN
is captured on positive edge when SCLK is in master mode.
Serial Slave Mode (SCS = 1)Any of the AD6623 serial ports may be operated in the serial slave
mode. In this mode, the selected AD6623 channel requires that
an external device such as a DSP to supply the SCLK. This is
done to synchronize the serial port to meet an external timing
requirement. SDIN is captured on negative edge of SCLK when
in slave mode.
Self-Framing ModeIn this mode Bit 7 of register 0xn16 is set low. The serial data
frame output, SDFO, generates a self-framing data request and
is pulsed high for one SCLK cycle at the input sample rate. In
this mode, the SDFI pin is not used, and the SDFO signal would
be programmed to be a serial data frame request (0xn16, Bit 5 = 0).
SDFO is used to provide a sync signal to the host. The input
sample rate is determined by the CLK divided by channel interpo-
lation factor. If the SCLK rate is not an integer multiple of the
input sample rate, then the SDFO will continually adjust the
period by one SCLK cycle to keep the average SDFO rate equal
to the input sample rate. When the channel is in sleep mode, SDFO
is held low. The first SDFO is delayed by the channel reset latency
after the Channel Reset is removed. The channel reset latency
varies dependent on channel configuration.
External Framing ModeIn this mode Bit 7 of register 0xn16 is set high. The external
framing can come from either the SDFI pin (0xn16, Bit 6 = 0)
or the previous adjacent channel (0xn16, Bit 6 = 1). In the case
of external framing from a previous channel, it uses the internal
frame end signal for serial data frame syncing. When in master
mode, SDFO and SDFI transition on the positive edge of SCLK,
and SDIN is captured on the positive edge of SCLK. When in
slave mode, SDFO and SDFI transition on the negative edge of
SCLK, and SDIN is captured on the negative edge of SCLK.
Serial Port Cascade ConfigurationIn this case the SDFO signal from the last channel of the first
chip would be programmed to be a serial data frame end (SFE:
0xn16, Bit 5 = 1). This SDFO signal would then be fed as an
input for the second cascaded chip’s SDFI pin input. The second
chip would be programmed to accept external framing from the
SDFI pin (0xn16, Bit 7 = 1, Bit 6 = 0).
Serial Data FormatThe format of data applied to the serial port is determined by
the RCF mode selected in Control Register 0xn0C. Below is a
table showing the RCF modes and input data format that it sets.
Table I.Serial Data FormatThe serial data input, SDIN, accepts 32-bit words as channel input
data. The 32-bit word is interpreted as two 16-bit two’s comple-
ment quadrature words, I followed by Q, MSB first. This results in
linear I and Q data being provided to the RCF. The first bit is
shifted into the serial port starting on the next rising edge of SCLK
after the SDFO pulse. Figure 16 shows a timing diagram for SCLK
master (SCS = 0) and SDFO set for frame request (SFE = 0).
AD6623
PROGRAMMABLE RAM COEFFICIENT FILTER (RCF)Each channel has a fully independent RAM Coefficient Filter (RCF).
The RCF accepts data from the Serial Port, processes it, and passes
the resultant I and Q data to the CIC filter. A variety of processing
options may be selected individually or in combination, including
PSK and MSK modulation, FIR filtering, all-pass phase equalization,
and scaling with arbitrary ramping. See Table III.
Table III.Data Format Processing Options
OVERVIEW OF THE RCF BLOCKSThe Serial Port passes data to the RCF with the appropriate
format and bit precision for each RCF configuration, see Figure 17.
The data may be modulated vectors or unmodulated bits. I and
Q vectors are sent directly to the Interpolating Fir Filter. Unmodu-
lated bits may be sent to the PSK Modulator, the Interpolating
MSK Modulator, or the Interpolating QPSK Modulator. The PSK
Modulator produces unfiltered I and Q vectors at the symbol
rate which are then passed through the Interpolating FIR Filter.
The Interpolating MSK Modulator and the Interpolating QPSK
Modulator produce oversampled, pulse-shaped vectors directly
without employing the Interpolating FIR Filter. When possible,
the MSK and QPSK modulators are recommended for increased
throughput and decreased power consumption compared to
Interpolating FIR Filter. In addition, the Interpolating MSK
Modulator can realize filters with nonlinear inter-symbol inter-
ference, achieving excellent accuracy for GMSK applications.
After interpolation, an optional Allpass Phase Equalizer (APE)
can be inserted into the signal path. The APE can realize any real,
stable, two-pole, two-zero all-pass filter at the RCF’s interpolated
rate. This is especially useful to precompensate for nonlinear
phase responses of receive filters in terminals, as specified by IS-95.
When active, the APE utilizes shared hardware with the interpo-
lating modulators and filter, which may reduce the allowed RCF
throughput, inter-symbol interference, or both. See Figure 18.
Figure 16.Serial Port Switching Characteristics
As an example of the Serial Port operation, consider a CLK fre-
quency of 62.208 MHz and a channel interpolation of 2560. In
that case, the input sample rate is 24.3 kSPS (62.208 MHz/2560),
which is also the SDFO rate. Substituting, fSCLK ≥ 32 � fSDFO
into the equation and solving for SCLKdivider, we find the mini-
mum value for SCLKdivider according to the equation below.(3)
Evaluating this equation for our example, SCLKdivider must be
less than or equal to 79. Since the SCLKdivider channel register
is a 5-bit unsigned number it can only range from 0 to 31.
Any value in that range will be valid for this example, but if it is
important that the SDFO period is constant, then there is another
restriction. For regular frames, the ratio fSCLK/fSDFO must be equal
to an integer of 32 or larger. For this example, constant SDFO
periods can only be achieved with an SCLK divider of 31 or less.
See Table II for usable SCLK divider values and the corresponding
SCLK and fSCLK/fSDFO ratio for the example of L = 2560.
In conclusion, SDFO rate is determined by the AD6623 CLK
rate and the interpolation rate of the channel. The SDFO rate is
equal to the channel input rate. The channel interpolation is
equal to RCF interpolation times CIC5 interpolation, times
CIC2 interpolation:(4)
The SCLK divide ratio is determined by SCLKdivider as shown
in the previous equation. The SCLK must be fast enough to
input 32 bits of data prior to the next SDFO. Extra SCLKs are
ignored by the serial port.
Table II.Example of Usable SCLK Divider
Values and fSCLK/fSDPO Ratios for L = 2560
Figure 17.Data Formats Supported by the AD6623 when
SCLK Master (SCS = 0), and SFDO Set for Frame Request (SFE = 0)
Figure 18.RCF Block Diagram
Table IV.FIR Filter Internal PrecisionThe Scale and Ramp block adjusts the final magnitude of the
modulated RCF output. A synchronization pulse from the SYNC0–3
pins or serial words can be used to command this block to ramp
down, pause, and ramp up to a new scale factor. The shape of
the ramp is stored in RAM, allowing complete sample by sample
control at the RCF interpolated rate. This is particularly useful
for time division multiplexed standards such as GSM/EDGE.
Modulator configurations can be updated while the ramp is quiet,
INTERPOLATING FIR FILTERThe Interpolating FIR Filter realizes a real, sum-of-products filter
on I and Q inputs using a single interleaved Multiply-Accumulator
(MAC) running at the CLK rate. The input signal is interpolated
by integer factors to produce arbitrary impulse responses up to
256 output samples long.
Each bus in the data path carries bipolar two’s complement values.
For the purpose of discussion, we will arbitrarily consider the radix
AD6623x–1 to 2x–1 – 2–y in 2–y steps. The range limits are tabulated in
TableIV for each bus. The hexadecimal values are bit-exact and
each MSB has negative weight. Note that the Product bus range is
limited by result of the multiplication and the two most significant
bits are the same except in one case.
Figure 19.Interpolating FIR Filter Block Diagram
The RCF realizes a FIR filter with optional interpolation. The FIR
filter can produce impulse responses up to 256 output samples
long. The FIR response may be interpolated up to a factor of 256,
although the best filter performance is usually achieved when the
RCF interpolation factor (LRCF) is confined to eight or below. The
256 � 16 coefficient memory (CMEM) can be divided among an
arbitrary number of filters, one of which is selected by the Coef-
ficient Offset Pointer (channel address 0x0B). The polyphase
implementation is an efficient equivalent to an integer up-sampler
followed FIR filter running at the interpolated rate.
The AD6623 RCF realizes a sum-of-products filter using a polyphase
implementation. This mode is equivalent to an interpolator followed
by a FIR filter running at the interpolated rate. In the functional
diagram below, the interpolating block increases the rate by the RCF
interpolation factor (LRCF) by inserting LRCF–1 zero valued samples
between every input sample. The next block is a filter with a finite
impulse response length (NRCF) and an impulse response of h[n],
where n is an integer from 0 to NRCF–1.
The difference equation for Figure 20 is written below, where h[n]
is the RCF impulse response, b[n] is the interpolated input sample
sequence at point ‘b’ in the diagram above, and c[n] is the output
sample sequence at point ‘c’ in Figure 20.
Figure 20.RCF Interpolation
(5)
This difference equation can be described by the transfer function
from point ‘b’ to ‘c’ as:(6)
The actual implementation of this filter uses a polyphase decom-
position to skip the multiply-accumulates when b[n–k] is zero.
Compared to the diagram above, this implementation has the benefits
of reducing by a factor of LRCF both the time needed to calculate
an output and the required data memory (DMEM). The price of
these benefits is that the user must place the coefficients into the coefficient
memory (CMEM) indexed by the interpolation phase. The process of
selecting the coefficients and placing them into the CMEM is broken
into three steps shown below.
The FIR accepts two’s complement I and Q samples from the serial
port with a fixed-point resolution of 16 bits each. When the serial port
provides data with less precision, the LSBs are padded with zeroes.
The Data-Mem stores the most recent 16 I and Q pairs for a total
of 32 words. The size of the Data-Mem limits the RCF impulse
response to 16 � LRCF output samples. When the data words from
the Serial Port have fewer than 16 bits, the LSBs are padded with
zeroes. The Data-Mem can be accessed through the Microport
from 0x20 to 0x5F above the processing channel’s base internal
address, while the channel’s Prog bit is set (external address 4).
In order to avoid start-up transients, the Data-Mem should be
cleared before operation. The Prog bit must then be reset to
enable normal operation.
The Coef-Mem stores up to 256 16-bit filter coefficients. The Coef-
Mem can be accessed through the Microport from 0x800 to 0x8FF
above the processing channel’s base internal address, while the channel’s
Prog bit is set (external address 4). For AD6622 compatibility, the lower
128 words are also mirrored from 0x080 to 0x0FF above the processing
channel’s base internal address, while the Prog bit is set. To avoid
start-up transients, the Data-Mem should be cleared before operation.
The Prog bit must then be reset to enable channel operation.
There is a single Multiply-Accumulator (MAC) on which both the
I and Q operations must be interleaved. Two CLK cycles are required
for the MAC to multiply each coefficient by an I and Q pair. The
MAC is also used for four additional CLK cycles if the All-pass
Phase Equalizer is active.
The size of the Data-Mem and Coef-Mem combined with the
speed of the MAC determine the total number of the taps per
phase (TRCF) that may be calculated. TRCF is the number of
RCF input samples that influence each RCF output sample.
The maximum available TRCF is calculated by the equation below.(7)
The impulse response length at the output of the RCF is determined
by the product of the number of interfering input samples (TRCF)
and the RCF interpolation factor (LRCF), as shown by equation
(8) below. The values of NRCF and TRCF are programmed into control
registers. LRCF is not a control register, but NRCF and TRCF must
be set so that LRCF is an integer. If the integer interpolation by
the RCF results in an inconvenient sample rate at the output of
the RCF, the desired output rate can usually be achieved by
selecting non-integer interpolation in the resampling CIC2 filter.(8)
Table V.RCF Control Registers0x110
0x111
0x112
0x113
0x114
0x115
0x116
PSK MODULATORThe PSK Modulator is an AD6623 extension feature that is
only available when the control register bit 0x000:7 is high.
The PSK Modulator creates 32-bit complex inputs to the
Interpolating FIR Filter from two or three data bits captured
by the serial port. The FIR Filter operates exactly as if the 32-
bit word came directly from the serial port. There are three
PSK modulation options to choose from: �/4-DQPSK, 8-PSK,
and 3�/8-8-PSK. Every symbol of any of these modulations
can be represented by one of the 16phases shown in Figure 21.
Figure 21.16-Phase Modulations
AD6623All of these phase locations are represented in rectangular coor-
dinates by only four unique magnitudes in the positive and negative
directions. These four values are read from four channel registers
that are programmed according to the following table, which
gives the generic formulas and a specific example. The example
is notable because it is only 0.046 dB below full-scale and the
16-bit quantization is so benign at that magnitude, that the rms
error is better than –122 dBc. It is also worth noting that because
none of the phases are aligned with the axes, magnitudes slightly
beyond 0.16 dB above full-scale are achievable.
Table VI.Program RegistersUsing the four channel registers from the preceding table, the PSK
Modulator assembles the 16 phases according to Table VII.
Table VII.PSK Modulator PhaseThe following three sections show how the phase values are
created for each PSK modulation mode.
�/4-DQPSK Modulation
IS-136 compliant �/4-DQPSK modulation is selected by setting
the channel register 0x0C: 6–4 to 001b. The phase word is calculated
according to the following diagram. The two LSBs of the serial
input word update the payload bits once per symbol. The QPSK
Mapper creates a data dependent static phase word (Sph) which
is added to a time dependent rotating phase word (Rph). The Rph
starts at zero when the RCF is reset or switches modes via a sync
pulse. Otherwise, the Rph increments by two on every symbol.
Figure 22.QPSK Mapper
The Sph word is calculated by the QPSK Mapper according to
the following truth table.
Table VIII.QPSK Mapper Truth Table
8-PSK ModulationIS-136+ compliant 8-PSK modulation is selected by setting the
channel register 0x0C: 6–4 to 101b. The Phase word is calculated
according to the following diagram. The three LSBs of the serial
input word update the payload bits once per symbol.
Figure 23.8-PSK Mapper
The Phase word is calculated by the 8-PSK Mapper according
to the following truth table:
Table IX.8-PSK Mapper Truth Table
3 �/8-8-PSK ModulationEDGE compliant 3 �/8-8-PSK modulation is selected by setting the
channel register 0x0C: 6–4 to 110b. The phase word is calculated
according to the following diagram. The three LSBs of the serial
input word update the payload bits once per symbol. The 8-PSK
Mapper creates a data-dependent static phase word (Sph) which is
added to a time-dependent rotating phase word (Rph). The 8-PSK
Mapper operates exactly as described in the preceding 8-PSK
Modulation section. The Rph starts at zero when the RCF is reset
or switches modes via a sync pulse. Otherwise, the Rph increments
by three on every symbol.
