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AD6620AS
65 MSPS Digital Receive Signal Processor
REV.0
65 MSPS Digital Receive
Signal Processor
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Input Sample Rate
65 MSPS Single Channel Real
32.5 MSPS Diversity Channel Real
32.5 MSPS Single Channel Complex
NCO Frequency Translation
Worst Spur Better than –100 dBc
Tuning Resolution Better than 0.02 Hz
2nd Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 2, 3...16
5th Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 1, 2, 3...32
Programmable Decimating RAM Coefficient FIR Filter
Up to 130 Million Taps per Second
256 20-Bit Programmable Coefficients
Programmable Decimation Rates: 1, 2, 3...32
Bidirectional Synchronization Circuitry
Phase Aligns NCOs
Synchronizes Data Output Clocks
Serial or Parallel Baseband Outputs
Pin Selectable Serial or Parallel
Serial Works with SHARC, ADSP-21xx, Most Other
DSPs
16-Bit Parallel Port, Interleaved I and Q Outputs
Two Separate Control and Configuration Ports
Generic mP Port, Serial Port
3.3 V Optimized CMOS Process
JTAG Boundary Scan
GENERAL DESCRIPTIONThe AD6620 is a digital receiver with four cascaded signal-
processing elements: a frequency translator, two fixed-
coefficient decimating filters, and a programmable coefficient
decimating filter. All inputs are 3.3 V LVCMOS compatible.
All outputs are LVCMOS and 5 V TTL compatible.
As ADCs achieve higher sampling rates and dynamic range, it
becomes increasingly attractive to accomplish the final IF stage
of a receiver in the digital domain. Digital IF Processing is less
expensive, easier to manufacture, more accurate, and more
flexible than a comparable highly selective analog stage.
The AD6620 diversity channel decimating receiver is designed
to bridge the gap between high speed ADCs and general pur-
pose DSPs. The high resolution NCO allows a single carrier to
be selected from a high speed data stream. High dynamic range
decimation filters with a wide range of decimation rates allow
both narrowband and wideband carriers to be extracted. The
RAM-based architecture allows easy reconfiguration for multi-
mode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-
band noise is called “processing gain.” By using large decima-
tion factors, this “processing gain” can improve the SNR of the
ADC by 36 dB or more. In addition, the programmable RAM
Coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,
and an A/B Select pin. These allow direct interfacing with the
AD6600, AD6640, AD9042 and most other high speed ADCs.
Three input modes are provided: Single Channel Real, Single
Channel Complex, and Diversity Channel Real.
When paired with an interleaved sampler such as the AD6600,
the AD6620 can process two data streams in the Diversity
Channel Real input mode. Each channel is processed with co-
herent frequency translation and output sample clocks. In addi-
tion, external synchronization pins are provided to facilitate
coherent frequency translation and output sample clocks among
several AD6620s. These features can ease the design of systems
with diversity antennas or antenna arrays.
Units are packaged in an 80-lead PQFP (plastic quad flatpack)
and specified to operate over the industrial temperature range
(–40°C to +85°C).
AD6620
RCFEXP[2:0]IN[15:0]
fSAMP5
CLK
A/B
RESET
SYNC
SYNC
SYNCNCO
PHASE
OFFSET
fSAMP2
fSAMP
OUT[15:0]
SCLK
SDI
SDO
SDFS
SDFE
SBM
WL[1:0]
RCF COEFFICIENTS
NUMBER OF TAPS
DECIMATE FACTOR
ADDRESS OFFSETCIC2, CIC5
DECIMATE FACTORS
SCALE FACTORSNCO FREQUENCY
PHASE OFFSET
DITHER
SYNC MASK
INPUT MODE
REAL, DUAL, COMPLEX
FIXED OR WITH EXPONENT
SYNC M/S
OUTPUT
SCALE
FACTORTCKTMSTDITDOD[7:0]A[2:0]R/WMODEPAR/SER
CONTROL REGISTERS
MICROPORT AND
SERIAL ACCESS
TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
SPECIFICATIONS/TIMING . . . . . . . . . . . . . . . . . . . . . . .4
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .11
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . .11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . .12
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . .13
INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . .18
FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . .20
2ND ORDER CASCADED INTEGRATOR
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5TH ORDER CASCADED INTEGRATOR
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . .25
CONTROL REGISTERS AND ON-CHIP RAM . . . . . . .27
PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . .29
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . .31
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . .34
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . .36
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .43
ARCHITECTUREAs shown in Figure 1, the AD6620 has four main signal pro-
cessing stages: a Frequency Translator, two Cascaded Integrator
Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR
Filter (RCF). Multiple modes are supported for clocking data
into and out of the chip. Programming and control is accom-
plished via serial and microprocessor interfaces.
Input data to the chip may be real or complex. If the input data
is real, it may be clocked in as a single channel or interleaved
with a second channel. The two-channel input mode, called
Diversity Channel Real, is typically used in diversity receiver
applications. Input data is clocked in 16-bit parallel words,
IN[15:0]. This word may be combined with exponent input bits
EXP[2:0] when the AD6620 is being driven by floating-point or
gain-ranging analog-to-digital converters such as the AD6600.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into in-phase (I) and quadrature (Q)
components. This stage translates the input signal from a digital
intermediate frequency (IF) to baseband. Phase and amplitude
dither may be enabled on-chip to improve spurious performance
of the NCO. A phase offset word is available to create a known
phase relationship between multiple AD6620s.
Following frequency translation is a fixed coefficient, high speed
decimating filter that reduces the sample rate by a program-
mable ratio between 2 and 16. This is a second order, cascaded
integrator comb FIR filter shown as CIC2 in Figure 1. (Note:
Decimation of 1 in CIC2 requires 2· or greater clock into
AD6620). The data rate into this stage equals the input data
rate, fSAMP. The data rate out of CIC2, fSAMP2, is determined by
the decimation factor, MCIC2.
Following CIC2 is the second fixed-coefficient decimating filter.
This filter, CIC5, further reduces the sample rate by a program-
mable ratio from 1 to 32. The data rate out of CIC5, fSAMP5, is
determined by the decimation factors of MCIC5 and MCIC2.
Each CIC stage is a FIR filter whose response is defined by the
decimation rate. The purpose of these filters is to reduce the
data rate of the incoming signal so that the final filter stage, a
FIR RAM coefficient sum-of-products filter (RCF), can calcu-
late more taps per output. As shown in Figure 1, on-chip multi-
plexers allow both CIC filters to be bypassed if a multirate clock
is used.
The fourth stage is a sum-of-products FIR filter with program-
mable 20-bit coefficients, and decimation rates programmable
from 1 to 32. The RAM Coefficient FIR Filter (RCF in Figure
1) can handle a maximum of 256 taps.
The overall filter response for the AD6620 is the composite of
all three cascaded decimating filters: CIC2, CIC5, and RCF.
Each successive filter stage is capable of narrower transition
bandwidths but requires a greater number of CLK cycles to
calculate the output. More decimation in the first filter stage will
minimize overall power consumption. Data comes out via a
parallel port or a serial interface.
Figure 2 illustrates the basic function of the AD6620: to select
and filter a single channel from a wide input spectrum. The
frequency translator “tunes” the desired carrier to baseband.
CIC2 and CIC5 have fixed order responses; the RCF filter
provides the sharp transitions. More detail is provided in later
sections of the data sheet.
–fS/2–3fS/8–5fS/16–fS/4–3fS/16–fS/8–fS /16DCfS/16fS/83fS/16fS/45fS/16fS/23fS/8
SIGNAL OF
INTEREST
SIGNAL OF INTEREST "IMAGE"
WIDEBAND INPUT SPECTRUM(–fsamp/2 TO fsamp/2)ACFigure 2a.Wideband Input Spectrum (e.g., 30 MHz from High Speed ADC)
–fS/2–3fS/8–5fS/16–fS/4–3fS/16–fS/8–fS/16DCfS/16fS/83fS/16fS/45fS/16fS/23fS/8
AFTER FREQUENCY TRANSLATION
NCO "TUNES" SIGNAL TO BASEBANDFigure 2b.Frequency Translation (e.g. Single 1 MHz Channel Tuned to Baseband)
CIC2, CIC5, AND RCF
dBc
FREQUENCYFigure 2c.Baseband Signal is Decimated and Filtered by CIC2, CIC5, RCF
AD6620–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSPOWER DISSIPATION
NOTESInput-Only Pins: CLK, RESET, IN[15:0], EXP[2:0], A/B, PAR/SEL.Bidirectional Pins: SYNC_NCO, SYNC_CIC, SYNC_RCF.Microinterface Input Pins: DS (RD), R/W (WR), CS.Microinterface Bidirectional Pins: A[2:0], D[7:0].JTAG Input Pins: TRST, TCK, TMS, TDI.Serial Mode Input Pins: SDI, SBM, WL[1:0], AD, SDIV[3:0].Serial Mode Bidirectional Pins: SCLK, SDFS.Output Pins: OUT[15:0], DVOUT, A/BOUT, I/QOUT.Microinterface Output Pins: DTACK (RDY).JTAG Output Pins: TDO.Serial Mode Output Pins: SDO, SDFE.Conditions for IDD @ 20 MHz. MCIC2 = 2, MCIC5 = 2, MRCF = 1, 4 RCF taps of alternating positive and negative full scale.Conditions for IDD @ 65 MHz. MCIC2 = 2, MCIC5 = 2, MRCF = 1, 4 RCF taps of alternating positive and negative full scale.Conditions for IDD in Reset (RESET = 0).
Specifications subject to change without notice.
TIMING CHARACTERISTICS(CLOAD = 40 pF All Outputs)NOTESSpecification pertains to: IN[15:0], EXP[2:0], A/B.Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
AD6620
TIMING CHARACTERISTICS(CLOAD = 40 pF All Outputs)NOTES
1Specification pertains to: R/W (WR), DS (RD), CS.
2Specification pertains to: A[2:0].
3Specification pertains to: D[7:0].
Specifications subject to change without notice.
TIMING DIAGRAMS
CLK, INPUTS, PARALLEL OUTPUTSRESET with PAR/SER = “1” establishes Parallel Outputs active.
Figure 3.CLK Timing Requirements
CLK
IN[15:0]
EXP[2:0]
A/BFigure 4. Input Data Timing Requirements
CLK
OUT[15:0]DVOUT
I/QOUTFigure 5. Parallel Output Switching Characteristics
SYNC PULSES: SLAVE OR MASTER
CLK
SYNC
SYNCCIC
SYNCFigure 6.SYNC Slave Timing Requirements
Figure 7.SYNC Master Delay
Figure 8. Reset Timing Requirements
AD6620
SERIAL PORT: BUS MASTERRESET with PAR/SER = “0” establishes Serial Port active.
SBM = “1” puts AD6620 in Serial Bus Master mode SCLK is
output; SDFS is output.
Figure 9.SCLK Switching Characteristics
Figure 10.Serial Input Data Timing Requirements
SCLK
SDFS
SDFEFigure 11.Serial Frame Switching Characteristics
Figure 12.Serial Output Data Switching Characteristics
SERIAL PORT: CASCADE MODERESET with PAR/SER = “0” establishes Serial Port active.
SBM = “0” puts AD6620 in Serial Port Cascade mode, SCLK
is input; SDFS is input.
Figure 13.SCLK Timing Requirements
SCLK
SDIFigure 14.Serial Input Data Timing Requirements
SCLK
SDFSFigure 15.SDFS Timing Requirements
SCLK
SDO
SDFEFigure 16.SDO, SDFE Switching Characteristics
MICROPORT MODE0, READTiming is synchronous to CLK; MODE = 0.
CLK1
WR2
RD2
CS3
D[7:0]
RDY1
A[2:0]
NOTES:
1 RDY IS DRIVEN LOW ASYNCHRONOUSLY BY RD AND CS GOING LOW AND RETURNS HIGH ON THE RISING EDGE
OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000), CLK "N+2" OTHERWISE.
2 THE SIGNAL, WR, MAY REMAIN HIGH AND RD MAY REMAIN LOW TO CONTINUE READ MODE.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE READ.Figure 17.MODE0 Read Timing Requirements and Switching Characteristics
MICROPORT MODE0, WRITETiming is synchronous to CLK; MODE = 0.
AD6620
MICROPORT MODE1, READTiming is synchronous to CLK; MODE = 1.
CLK1
R/W2
DS2
CS3
D[7:0]
DTACK
A[2:0]
NOTES:
1 DTACK IS DRIVEN LOW ON THE RISING EDGE OF CLK "N+3" FOR INTERNAL ACCESS (A[2:0] = 000),
CLK "N=2" OTHERWISE.
2 THE SIGNAL, R/W MAY REMAIN HIGH AND DS MAY REMAIN LOW TO CONTINUE READ MODE.
3 CS MUST RETURN TO HIGH STATE AND BE SAMPLED BY CLK (N+4 SHOWN) TO COMPLETE ACCESS
AND FORCE DTACK HIGH.Figure 19.MODE1 Read Timing Requirements and Switching Characteristics
MICROPORT MODE1, WRITETiming is synchronous to CLK; MODE = 1.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +4.5 V
Input Voltage . . . .–0.3 V to VDD + 0.3 V (Not 5 V Tolerant)
Output Voltage Swing . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . .+130°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . .+280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Thermal Characteristics80-Lead Plastic Quad Flatpack:JA = 44°C/Watt
EXPLANATION OF TEST LEVELS100% Production Tested.
II.100% Production Tested at +25°C, and Sampled Tested at
Specified Temperatures.
III.Sample Tested Only.
IV.Parameter Guaranteed by Design and Analysis.Parameter is Typical Value Only.
VI.100% Production Tested at +25°C, and Sampled Tested at
Temperature Extremes.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD6620Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-state.
SHARED PINS
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
Parallel Output Data(MSB) OUT15OUT14VDDOUT13OUT12OUT11VSSOUT10OUT9OUT8OUT7VDDOUT6OUT5OUT4
VSS
VDD
DTACK
R/W
VSS
MODE
OUT0 (LSB)
A/BOUT
I/QOUT
VDD
DVOUT
PAR/SER
RESET
TRST
TCK
TMS
TDO
TDI
VDD
SYNCNCO
SYNC
SYNCRCF
VSS
EXP2
IN15 (MSB)
IN14
VSS
IN13IN12IN11VDDIN10
IN9IN7
VSS
IN6IN5IN4IN8
VSSOUT3OUT2OUT1
CLK
A/B
IN0 (LSB)
VDD
IN3IN2IN1
EXP0
EXP1
Serial PortSCLKSDIVDDSDOSDFSSDFEVSSSBMWL1WL0ADVDDNCNCNC
VSS
VDD
DTACK
R/W
VSS
MODE
SDIV0
A/BOUT
I/QOUT
VDD
DVOUT
PAR/SER
RESET
TRST
TCK
TMS
TDO
TDI
VDD
SYNCNCO
SYNC
SYNCRCF
VSS
EXP2
IN15IN14
VSS
IN13IN12IN11VDDIN10
IN9IN7
VSS
IN6IN5IN4IN8
VSSSDIV3SDIV2SDIV1
CLK
A/B
IN0
VDD
IN3IN2IN1
EXP0
EXP1
THE HIGHEST NUMBERED BIT IS THE MSB FOR ALL PORTSNC = NO CONNECT
AD6620
LOG2 – M
POWER – mW
400Figure 21.Typical Power vs. Decimation Rates
–132
fSAMPFigure 22.Typical NCO Spur Without Dither
fSAMPFigure 23.Worst Case NCO Spur with Dither
Figure 24.High Decimation GSM Filter
Input sample rate 65 MSPS, decimation is 240, FIR taps is 240.
Unshown spectrum is below that shown. Decimation distribu-
tion is 3, 10, 8, respectively.
Figure 25.High Decimation AMPS Filter
Input sample rate 58.32 MSPS, decimation is 300, FIR taps is
128. Unshown spectrum is below that shown. Decimation
distribution among CIC2, CIC5 and RCF is 10, 30 and 1,
respectively.
INPUT DATA PORTThe input data port accepts a clock (CLK), a 16-bit mantissa
IN[15:0], a 3-bit exponent EXP[2:0], and channel select
Pin A/B. These pins allow direct interfacing to both standard
fixed-point ADCs such as the AD9225 and AD6640, as well as
to gain-ranging ADCs such as the AD6600. These inputs are
not +5 V tolerant and the ADC I/O should be set to +3.3 V.
The input data port accepts data in one of three input modes:
Single Channel Real, Diversity Channel Real, or Single Channel
Complex. The input mode is selected by programming the Input
Mode Control Register located at internal address space 300h.
Single Channel Real mode is used when a single channel ADC
drives the input to the AD6620. Diversity Channel Real mode is
the two channel mode used primarily for diversity receiver appli-
cations. Single Channel Complex mode accepts complex data in
conjunction with the A/B input which identifies in-phase and
quadrature samples (primarily for cascaded 6620s).
The input data port is sampled on the rising edge of CLK at a
maximum rate of 65 MSPS. The 16-bit mantissa, IN[15:0] is
interpreted as a twos complement integer. For most applications
with ADCs having fewer than 16 bits, the active bits should be
MSB justified and the unused LSBs should be tied low.
The 3-bit exponent, EXP[2:0] is interpreted as an unsigned
integer. The exponent can be modified by the 3-bit exponent
offset ExpOff (Control Register 0x305, Bits (7–5)) and an expo-
nent invert ExpInv (Control Register 0x305, Bit 4).
ExpOff sets the offset of the input exponent, EXP[2:0]. ExpInv
determines the direction of this offset. Equations below show
how the exponent is handled.
where: IN is the value of IN[15:0], Exp is the value of EXP[2:0],
and ExpOff is the value of ExpOff.
Input ScalingIn general there are two reasons for scaling digital data. The
first is to avoid “clipping” or, in the case of the AD6620 register,
“wrap-around” in subsequent stages. Wrap-around is not a
concern for the input data since the NCO is designed to accept
the largest possible input at the AD6620 data port.
The second use of scaling is to preserve maximum dynamic
range though the chip. As data flows from one stage to the next
it is important to keep the math functions performed in the
MSBs. This will keep the desired signal as far above the noise
floor as possible, thus maximizing signal-to-noise ratio.
Scaling with Fixed-Point ADCsFor fixed-point ADCs the AD6620 exponent inputs, EXP[2:0]
are typically not used and should be tied low. The ADC outputs
are tied directly to the AD6620 Inputs, MSB-justified. The
exponent offset (ExpOff) and exponent invert (ExpInv) should
both be programmed to 0. Thus the input equation,
where: IN is the value of IN[15:0], Exp is the value of EXP[0:2],
Thus for fixed-point ADCs, the exponents are typically static
and no input scaling is used in the AD6620.
+3.3VFigure 26. Typical Interconnection of the AD6640 Fixed
Point ADC and the AD6620
Scaling with Floating-Point ADCsAn example of the exponent control feature combines the AD6600
and the AD6620. The AD6600 is an 11-bit ADC with 3 bits of
gain ranging. In effect, the 11-bit ADC provides the mantissa,
and the 3 bits of relative signal strength indicator (RSSI) are the
exponent. Only five of the eight available steps are used by the
AD6600. See the AD6600 data sheet for additional details.
For gain-ranging ADCs such as the AD6600,
where: IN is the value of IN[15:0], Exp is the value of EXP[2:0],
and ExpOff is the value of ExpOff.
The RSSI output of the AD6600 numerically grows with in-
creasing signal strength of the analog input (RSSI = 5 for a large
signal, RSSI = 0 for a small signal). With the Exponent Offset
equal to zero and the Exponent Invert Bit equal to zero, the
AD6620 would consider the smallest signal at the parallel input
(EXP = 0) the largest and, as the signal and EXP word increase,
it shifts the data down internally (EXP = 5, will shift the 11-bit
data right by 5 bits internally before going into the CIC2). The
AD6620 regards the largest signal possible on the AD6600 as
the smallest signal. Thus the Exponent Invert Bit is used to
make the AD6620 exponent agree with the AD6600 RSSI.
When it is set high, it forces the AD6620 to shift the data up for
growing EXP instead of down. The exponent invert bit should
always be set high for use with the AD6600.
Table I.AD6600 Transfer Function with AD6620 ExpInv = 1,
and No ExpOff
AD6620The Exponent Offset is used to shift the data right. For ex-
ample, Table I shows that with no ExpOff shift, 12 dB of range
is lost when the ADC input is at the largest level. This is undes-
ired because it lowers the Dynamic Range and SNR of the sys-
tem by reducing the signal of interest relative to the quantization
noise floor.
To avoid this automatic attenuation of the full-scale ADC sig-
nal, the Exponent Offset is used to move the largest signal (RSSI =
5) up to the point where there is no downshift. In other words,
once the Exponent Invert bit has been set, the Exponent Offset
should be adjusted so that mod(7–5 + ExpOff,8) = 0. This is
the case when Exponent Offset is set to 6 since mod(8, 8) = 0.
Table II illustrates the use of ExpInv and ExpOff when used
with the AD6600 ADC.
Table II. AD6600 Transfer Function with AD6620 ExpInv = 1,
and ExpOff = 6(ExpInv = 1, ExpOff = 6)
This flexibility in handling the exponent allows the AD6620 to
interface with other gain ranging ADCs besides the AD6600.
The Exponent Offset can be adjusted to allow up to seven
RSSI(EXP) ranges to be used as opposed to the AD6600s five.
It also allows the AD6620 to be tailored in a system that employs
the AD6600, but does not utilize all of its signal range. For
example, if only the first four RSSI ranges are expected to occur
then the Exponent Offset could be adjusted to five, which would
then make RSSI = 4 correspond to the 0 dB point of the AD6620.
Figure 27. Typical Interconnection of the AD6600 Gain-
Ranging ADC and the AD6620 in a Diversity Application
Input TimingThe CLK signal is used to sample the input port and clock the
synchronous signal processing stages that follow. The CLK signal
can operate up to 65 MHz and have a duty cycle of 45% to
55%. In applications using high speed ADCs, the ADC sample
clock is typically used to clock the AD6620. Applications that
require a faster signal processing clock than the ADC sample
clock, may employ fractional rate input timing as shown in the
following sections. The input timing requirements vary accord-
ing to the mode of operation. Fractional rate input timing cre-
ates a longer “don’t care” time for the input data so that slower
ADCs need only meet the setup-and-hold conditions for their
data with respect to their own sample clock cycle, rather than
the faster signal processing clock. The ADC sample clock may
be any integer fraction of CLK up to and including 1, as long as
the clock and data rate are less than or equal to 65 MSPS.
Single Channel Real ModeIn the Single Channel Real mode the A/B input pin functions as
an active high input enable. If the A/D sample clock is fast enough
to perform the necessary filter functions, full rate input timing
can be used and A/B should be tied high as shown in Figure 28.
Figure 28.Full Rate Input Timing, Single Channel
Real Mode
When a faster processing clock is used to achieve better filter
performance, the A/D data must be synchronized with the faster
AD6620 CLK signal. This is achieved by having the ADC clock
rate an integer fraction of the AD6620 clock rate. AD6620 input
data is sampled at the slower ADC clock rate. In the Single
Channel Real Mode this is achieved by dynamically controlling
the A/B input and bringing it high before each CLK edge that
data is to be sampled on. A/B must be returned low before the
next high speed clock pulse and the duty cycle of the A/B signal
will therefore be equal to the data-to-clock ratio.
CLK
IN[15:0]
EXP[2:0]
A/BFigure 29.Fractional Rate Input Timing (4· CLK), Single
Channel Real Mode
Diversity Channel Real ModeIn the Diversity Channel Real mode the A/B pin serves not only
as an input enable but also to determine which channel is being
sampled on a given CLK edge. A high on the A/B pin marks
channel A data and a low on A/B marks channel B data. The
AD6620 only accepts the first sample after an A/B transition.
All subsequent samples are disregarded until A/B changes again.
When full rate input timing is employed in the Diversity Chan-
nel Real mode, A/B must toggle on every edge of CLK for new
data to be clocked into the AD6620.
CLK
IN[15:0]
EXP[2:0]
A/BFigure 30.Full Rate Input Timing, Diversity Channel Real
Mode
If fractional rate input timing is necessary in the Diversity Chan-
nel Real Mode, the A/B pin must toggle at half the rate of the
A/D sample clock. The timing diagram below shows a 3· pro-
cessing clock. In this situation there will be one ADC encode
pulse for every three AD6620 CLK pulses and data must be
taken on every third CLK pulse. The CLK edges that corre-
spond to the latching of A and B channel data are shown in
Figure 31.
CLK
IN[15:0]
EXP[2:0]
A/BFigure 31.Fractional Rate Input Timing (3· CLK), Diversity
Channel Real Mode
Single Channel Complex ModeIn the Single Channel Complex input mode, A/B high identi-
fies the in-phase samples and A/B low identifies quadrature
samples. The quadrature samples are paired with the previous
in-phase samples. The timing for this mode is the same as that
of the Diversity Channel Real Mode. This mode is useful for
accepting complex output data from another AD6620 or an-
other source to increase filtering and or decimation rates.
In the Single Channel Complex Mode the CIC2 decimation
must be set to two (MCIC2 = 2). This is necessary in order to
allow enough CLK cycles to process the complex input data as
described below.
First clock cycle:(A/B high).I data loaded from the input port.The I data-path gets I · cosine.The Q data-path gets I · sine.The first integrator of the CIC2 adds these values to its
previous sums.The rest of the CIC2 is idle.
Second clock cycle: (A/B low).Q data loaded from the input port.The I data-path gets Q · sine.The Q data-path gets Q · cosine.The first integrator of the I path of the CIC2 completes the
sum (I · cosine - Q · sine) and the first integrator of the Q
path of the CIC2 completes the sum j(I · sine + Q · cosine).The rest of the CIC2 operates on these sums, which is the
complete complex multiply. The data is then multiplexed
through the rest of the chip as if it were single channel real data.
AD6620
CLK
LOGIC "1"
SOFT RESET
IN[15:0]
EXP[2:0]
A/B
CLK
Simplified Input Data Port SchematicFigure 32 details a simplified schematic for the input data port.
The first thing to note is that IN[15:0], EXP[2:0] and A/B are
all synchronously latched with CLK. Note also that upon soft
reset, a seven pipeline delay (sample clock delay) exists in the
data path. This delay is synchronous with CLK, but is in fact
seven valid sample data delays. For instance, in single channel
real mode with full rate timing the delay is seven CLKs. If in-
stead the data rate is one-fourth CLK, then 28 CLKs (i.e.,
seven sample data delays, gated via A/B) occur before valid data
is passed to the NCO stage.
Interfacing AD6620 Inputs to +5 V Logic GatesNone of the inputs to the AD6620 are tolerant of +5 V logic
signals. When interfacing 5 V devices to this product, an interface
gate such as the 74LCX2244 is recommended. If latching must
be performed, 74LCX574 latches may be used. This gate runs
from the +3.3 V supply and is tolerant of +5 V inputs.
OUTPUT DATA PORT
Parallel Output Data PortThe AD6620 provides a choice of two output ports: a 16-bit
parallel port and a synchronous serial port. Output operation
using the serial port is discussed in the next section. The parallel
port is limited to 16 bits. Because pins are shared between the
parallel and serial output ports, only one output mode can be
used. The output mode must be set with a hard reset generated
by at least a 30 ns low time on the RESET pin. If the PAR/SER
line is high (Logic “1”), then parallel output data is activated.
The PAR/SER pin should remain static after the output mode
has been set (i.e., PAR/SER should only change when RESET is
low). Data out of the AD6620 is twos complement.
A scale factor is associated with the output port, which allows
the signal level to be adjusted. This scale factor is mapped to
location 309h, Bits 2–0 in the AD6620 internal address space.
This scalar controls the weight of the 16-bit data going to the
parallel port. The scale factor is discussed in the RAM Coeffi-
cient Filter (RCF) section.
The Parallel Mode provides a 16-bit output port, which consti-
tutes the I and Q data for either one or both channels. This port
can run at a maximum of 65 MHz (32.5 MHz I, 32.5 MHz Q).
This rate assumes that there is a minimum decimation of 2 in
the first filter stage (CIC2) or a 2· or greater CLK is used. This
decimation is required because for every input word there is
both an I and a Q output. When the data rate and clock rate are
the same (Full Rate Input Timing), the minimum decimation of
2 must occur in CIC2. Refer to CIC2 for more detail.
DVOUTDVOUT is provided to signal that valid data is present. If this
pin is high, there is a valid data word on the bus. DVOUT re-
mains high for two speed clock cycles in Single Channel Real
and Single Channel Complex Mode and for four clock cycles in
Diversity Channel Real mode. After DVOUT returns low the Q
data will remain until the next data sample.
I/QOUTWhen this pin is high the data word represents I data; when
I/QOUT is low Q data is present. This signal will also be low
when DVOUT is low since the last word of every data phase is Q
data.
A/BOUTIF DVOUT is low, A/BOUT is always low. When A/BOUT is high,
A Channel data is available on the output. If DVOUT remains
high while A/BOUT is low, then B Channel data is on the output
pins of the chip OUT[15:0].
CLK
OUT[15:0]
DVOUT
I/QOUT
A/BOUTFigure 33.Parallel Output Data Timing (Single-Channel
Mode)
CLK
OUT[15:0]
DVOUT
I/QOUT
A/BOUTFigure 34.Parallel Output Data Timing (Diversity Channel
Mode)
Serial Output Data PortThe AD6620 provides a choice of two output ports: a 16-bit
parallel port and a synchronous serial port. The advantage of
using the serial port is that all 23 bits of available data can be
output in the 24-bit or 32-bit mode. The serial output port
shares some of the same pins used by the parallel output port.
As a result, one or the other mode of output may be utilized,
but not both. The output mode must be set with a hard reset
generated by at least a 30 ns low time on the RESET pin. If the
PAR/SER line is low (logic “0”) upon reset, then serial output
data is activated. The PAR/SER pin should remain static after
the output mode has been set (i.e., PAR/SER should only change
when RESET is low).
Note that the AD6620 cannot be booted through the serial port.
The microport must be used to initialize the device, then serial
operation is supported.
Figure 35 shows the typical interconnections between an AD6620
in serial master mode and a DSP. Refer to the Serial Control
Port section for a detailed description of pin functions and pro-
cedures for writing and reading with relation to the serial port.
Note the 10 kW resistors connected to SDI and SDO. These
prevent the lines from toggling when the AD6620 or DSP
three-states these pins.
+3.3V4Figure 35.Typical Serial Data Output Interface to DSP
(Serial Master Mode, SBM = 1)
Figure 36 shows two AD6620s illustrating the cascade capability
for the chip. The first is connected as a serial master and the
second is configured in serial cascade mode. The SDFE signal
of the master is connected to the SDFS of the slave. This allows
the master AD6620 data to be obtained first by the DSP, fol-
lowed by the cascade AD6620 data.
+3.3V
10kV44Figure 36.Typical Serial Data Output Interface to DSP
(Serial Cascade Mode, SBM = 0)
AD6620The AD6620 also supports a serial slave mode, where the serial
clock and interface is provided by a DSP or ASIC that is set to
operate in the master mode. Note that the AD6620 cannot be
booted through the serial port. The microport must be used to
initialize the device, then serial operation is supported.
In the serial slave mode, DVOUT is valid and indicates the pres-
ence of a new word in the output buffers of the shift register.
This pin may thus be used by the DSP to generate an interrupt
to service the serial port. The DSP then generates an SFDS
pulse to drive the AD6620. The first serial clock rising edge
after SDFS makes the first bit available at SDO. The falling
edge of serial clock can be used to sample the data. The total
number of bits are then read from the AD6620 (determined by
the serial port word length). If the DSP has the ability to count
bits, the DSP will know when the complete frame is read. If not,
the DSP can monitor the SDFE pin to determine that the com-
plete frame is read.
The serial clock provided by the DSP can be asynchronous with
the AD6620 clock and input data. The only constraint is that
the clock be fast enough to read the serial frame prior to the
next frame coming available. Since the AD6620 output is syn-
chronous with its input sample rate the output update rate can
be determined by the user-programmed decimation rate. The
timing diagram in Figure 38 details how serial slave mode is
implemented.
10kV4Figure 37.Typical Serial Data Output Interface to DSP
(Serial Slave Mode, SBM = 0)
DVOUT
SCLK
SDFS
SDO
FIRST DATA IS AVAILABLE THE FIRST
RISING SCLK AFTER SDFS GOES HIGHFigure 38.Timing for Serial Slave Mode (SBM = 0)
FREQUENCY TRANSLATORThe first signal processing stage is a frequency translator con-
sisting of two multipliers and a 32-bit complex numerically
controlled oscillator (NCO). The NCO serves as a quadrature
local oscillator capable of producing any analytic frequency
between –fSAMP/2 and +fSAMP/2 with a resolution of fSAMP/232. In
the Single Channel Real input mode, fSAMP is equal to fCLK
multiplied by the fraction of CLK cycles that A/B is high. In the
Diversity Channel Real and Single Channel Complex input
modes, fSAMP is equal to fCLK multiplied by the fraction of CLK
cycles on which A/B has been toggled. The NCO worst case
discrete spur is better than –100 dBc for all output frequencies.
The control word, NCO_FREQ is interpreted as a 32-bit un-
signed integer. To translate a channel centered at fCH to dc,
calculate NCO_FREQ using the equation below. The mod
function is used here to allow for Super Nyquist sampling where
the IF carrier(fCH) is larger than the sample rate(fSAMP). The
mod removes the integer portion of the number and forces it
into the 32-bit NCO Frequency Register. If the fraction re-
maining is larger than 0.5, the NCO will be tuning above the
Nyquist rate. The corresponding signal is then aliased back into
the first Nyquist Zone as a negative frequency.
In both Single and Diversity Channel Real Input modes, the
output of the translation stage is the complex product of the real
input samples and the complex samples from the NCO. It is
necessary for the subsequent decimating filters to reject the
unwanted image of the channel of interest, as well as any un-
wanted neighboring signals (and their images) not rejected by
previous analog filters.
In the Diversity Channel Real Input mode, the same NCO
output words are used for both channel A and B streams, result-
ing in identical phase shifts. In Single Channel Complex mode
both I and Q inputs are multiplied by the quadrature outputs of
the NCO. The I and Q products of the multiply are then pro-
cessed in the AD6620 filter stages.
Phase DitherThe AD6620 provides a phase dither option for improving the
spurious performance of the NCO. This is controlled via the
NCO Control Register at address 301 hex. When phase dither is
enabled by setting Bit 1 of this register high, spurs due to phase
truncation in the NCO are randomized. The energy from these
spurs is spread into the noise floor and Spurious Free Dynamic
Range is increase at the expense of very slight decreases in the
SNR. Phase dither should be experimented with for each de-
sired NCO frequency and if it is seen to reduce spurs, it should
be considered. The choice of whether Phase Dither is used in a
system will ultimately be decided by the system goals. If lower
spurs are desired at the expense of a slightly raised noise floor, it
should be employed. If a low noise floor is desired and the higher
spurs can be tolerated or filtered by subsequent stages, then
Phase Dither is not needed.
Amplitude DitherThe second dither option is Amplitude Dither or “Complex
Dither.” Amplitude Dither is enabled by setting Bit 2 of the
NCO Control Register at address 0x301 high. Amplitude Dither
improves performance by randomizing the amplitude quantiza-
tion errors within the angular to Cartesian conversion of the
NCO. This dither will be particularly useful when the NCO
frequency is close to an integer submultiple of the Input Data
Rate. However, this option may reduce spurs at the expense of a
slightly raised noise floor. Amplitude Dither and Phase Dither
can be used together, separately or not at all.
Phase OffsetThe phase offset register adds an offset to the phase accumula-
tor of the NCO. This is a 16-bit register and is interpreted as a
16-bit unsigned integer. A 0 in this register corresponds to a 0
Radian offset and an FFFF hex corresponds to an offset of 2 p
(1 – 1/(2^16)) Radians. This register can be used to allow mul-
tiple AD6620s whose NCOs are synchronized to produce sine
waves with a known and steady phase difference.
NCO SynchronizationIn order to achieve phase coherence between several AD6620s,
a SYNC_NCO pin is provided. When the internal register bit,
SYNC_M/S (Bit 3 of internal register 0x300), is set high,
SYNC_NCO provides a synchronization pulse on the rising
edge of CLK. When the SYNC_M/S bit is low, SYNC_NCO
accepts an external synchronization signal sampled on the rising
edge of CLK. When the AD6620 is a slave, the SYNC_NCO
signal need not be a short pulse. It may be taken high and held
for more than a CLK cycle in which case the NCO will be held
inactive until this pin is again lowered. If the device is run as a
sync slave in Single Channel Mode, the SYNC_NCO pin must
be held low for one sample period, usually one clock cycle. If the
device is run in Diversity Channel Real mode, the SYNC_NCO
must be high for two sample periods (clock cycles). In a system
with an array of AD6620s it is not necessary to use one as a
master. It may be desirable to generate a synchronization signal
elsewhere in the system and use that to control the AD6620. An
example of this may be in systems that receive packets of data.
In this case, the NCO my be resynchronized prior to the begin-
ning of the packet, thus giving a consistent phase relationship on
each burst. This allows for ease of use in a large system where
many AD6620s need be synchronized accurately across a large
backplane or installation.
The frequency of the SYNC_NCO pulses, and therefore the
accuracy of the synchronization, is determined by the value of
the NCO Sync Control Register at address 302 hex. The value
in this register is the SYNC_MASK and is interpreted as a
32-bit unsigned integer. This value controls the window around
the zero crossing of the NCO output sine wave in which the
NCO will output a SYNC_NCO pulse as a master. As a slave,
the value in this register will determine the number of MSBs
of the output sine wave that are synchronized with the master.
The Master and all slaves should use the same SYNC_MASK
word. This value should almost always be written as all 1s
(FFFFFFFF hex).
CLK
IN[15:0]
E[2:0]
A/BFigure 39.SYNC_NCO Pin
Effects of A/B Input on the NCOIf the AD6620 is run in Single Channel Real mode using frac-
tional rate input timing, the A/B input is used to enable the
NCO advancement. If the A/B line is held high longer than one
clock period, the NCO will advance for each rising edge of the
CLK while A/B is high. This is not normally the desired result
and thus A/B must be taken low after the first CLK period to
prevent anomalous NCO results. See additional details under
Fractional Rate Timing.
Phase Continuous Tuning with the AD6620For synchronization purposes, the AD6620 NCO phase is reset
each time the NCO frequency register is either written to or
read from. This is accomplished by forcing an NCO Sync to
occur. Normally, phase-continuous tuning is required on the
transmit path to control spectral leakage. On the receive path
this in not usually a constraint. However, if phase-continuous
tuning is required with the AD6620, it can be accomplished by
configuring the AD6620 as a Sync Slave. In this manner, no
internal NCO sync is generated when the NCO frequency regis-
ter is written to. If multiple AD6620s are synchronized together,
a common external sync pulse can be used to lock each of the
receivers together at the appropriate point in time. It is also
possible to reconfigure the AD6620 after the NCO frequency
register has been written so that the chip is once again a Sync
Master. The next time the NCO phase cycles through 0 degrees,
the NCO sync is exerted and the chip is again synchronized.
2ND ORDER CASCADED INTEGRATOR COMB FILTERThe CIC2 filter is a fixed-coefficient, decimating filter. It is
constructed as a second order CIC filter whose characteristics
are defined only by the decimation rate chosen. This filter can
process signals at the full rate of the input port (65 MHz) in all
input modes. The output rate of this stage is given by the equa-
tion below.
AD6620The gain and pass band droop of the CIC2 should be calculated
by the equations above, as well as the filter transfer equations
that follow. If these are unacceptable, they can be compensated
for in subsequent stages.
CIC2 RejectionThe table below illustrates the amount of bandwidth in percent
of the data rate into the CIC2 stage. The data in this table may
be scaled to any other allowable sample rate up to 65 MHz in
Single Channel Mode or 32.5 MHz in Diversity Channel Mode.
The table can be used as a tool to decide how to distribute the
decimation between CIC2, CIC5 and the RCF.
Table III.SSB CIC2 Alias Rejection Table (fSAMP = 1)
Bandwidth Shown in Percentage of fSAMP
Example CalculationsGoal: Implement a filter with an Input Sample Rate of 10 MHz
requiring 100 dB of Alias Rejection for a –7 kHz pass band.
Solution: First determine the percentage of the sample rate that
is represented by the pass band.
The decimation ratio, MCIC2, is an unsigned integer that may
be between 1 and 16. This stage may be bypassed under certain
conditions by setting, MCIC2 equal to 1. For this to happen the
processing clock rate, fCLK must be two or more times the input
data rate, fSAMP. This is because the I and Q data is processed
in parallel within the CIC2 filter, and the I and Q output data is
then multiplexed through the same data pipe before it enters the
CIC5 filter.
The frequency response of the CIC2 filter is given by the follow-
ing equations.
The scale factor, SCIC2 is a programmable unsigned integer
between 0 and 6. This serves as an attenuator that can reduce
the gain of the CIC2 in 6 dB increments. For the best dynamic
range, SCIC2 should be set to the smallest value possible (i.e.,
lowest attenuation) without creating an overflow condition.
This can be safely accomplished using the equation below,
where input_level is the largest fraction of full scale possible at
the input to this AD6620 (normally 1). The CIC2 scale factor is
not ignored when the CIC2 is bypassed.
SYNC_NCO
PIN32
